dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks

Add definitions for USB2 PHY core clocks in the R9A09G047 CPG DT
bindings header file.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251001212709.579080-9-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index f165df8a6f5a3454dc9daaaf668e255f90467ae4..dab24740de3c1189b3081f899e53352fc02d84c8 100644 (file)
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -22,5 +22,7 @@
 #define R9A09G047_GBETH_1_CLK_PTP_REF_I                11
 #define R9A09G047_USB3_0_REF_ALT_CLK_P         12
 #define R9A09G047_USB3_0_CLKCORE               13
+#define R9A09G047_USB2_0_CLK_CORE0             14
+#define R9A09G047_USB2_0_CLK_CORE1             15
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */