--- /dev/null
+From f70b281b59a871545362a494d99a644153fbbaac Mon Sep 17 00:00:00 2001
+From: Juri Lelli <juri.lelli@arm.com>
+Date: Wed, 31 May 2017 17:59:27 +0100
+Subject: arm: remove wrong CONFIG_PROC_SYSCTL ifdef
+
+From: Juri Lelli <juri.lelli@arm.com>
+
+commit f70b281b59a871545362a494d99a644153fbbaac upstream.
+
+The sysfs cpu_capacity entry for each CPU has nothing to do with
+PROC_FS, nor it's in /proc/sys path.
+
+Remove such ifdef.
+
+Cc: Russell King <linux@arm.linux.org.uk>
+Reported-and-suggested-by: Sudeep Holla <sudeep.holla@arm.com>
+Fixes: 7e5930aaef5d ('ARM: 8622/3: add sysfs cpu_capacity attribute')
+Signed-off-by: Juri Lelli <juri.lelli@arm.com>
+Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/kernel/topology.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/arch/arm/kernel/topology.c
++++ b/arch/arm/kernel/topology.c
+@@ -57,7 +57,6 @@ static void set_capacity_scale(unsigned
+ per_cpu(cpu_scale, cpu) = capacity;
+ }
+
+-#ifdef CONFIG_PROC_SYSCTL
+ static ssize_t cpu_capacity_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+@@ -114,7 +113,6 @@ static int register_cpu_capacity_sysctl(
+ return 0;
+ }
+ subsys_initcall(register_cpu_capacity_sysctl);
+-#endif
+
+ #ifdef CONFIG_OF
+ struct cpu_efficiency {
--- /dev/null
+From 664b7c4728821767e0228ee161bab87db2be58f1 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Fri, 12 May 2017 08:47:57 -0700
+Subject: pinctrl: core: Fix warning by removing bogus code
+
+From: Tony Lindgren <tony@atomide.com>
+
+commit 664b7c4728821767e0228ee161bab87db2be58f1 upstream.
+
+Andre Przywara <andre.przywara@arm.com> noticed that we can get the
+following warning with -EPROBE_DEFER:
+
+"WARNING: CPU: 1 PID: 89 at drivers/base/dd.c:349
+driver_probe_device+0x2ac/0x2e8"
+
+Let's fix the issue by removing the indices as suggested by
+Tejun Heo <tj@kernel.org>. All we have to do here is kill the radix
+tree.
+
+I probably ended up with the indices after grepping for removal
+of all entries using radix_tree_for_each_slot() and the first
+match found was gmap_radix_tree_free(). Anyways, no need for
+indices here, and we can just do remove all the entries using
+radix_tree_for_each_slot() along how the item_kill_tree() test
+case does.
+
+Fixes: c7059c5ac70a ("pinctrl: core: Add generic pinctrl functions for managing groups")
+Fixes: a76edc89b100 ("pinctrl: core: Add generic pinctrl functions for managing groups")
+Reported-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Tested-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/core.c | 20 +++-----------------
+ drivers/pinctrl/pinmux.c | 21 ++++-----------------
+ 2 files changed, 7 insertions(+), 34 deletions(-)
+
+--- a/drivers/pinctrl/core.c
++++ b/drivers/pinctrl/core.c
+@@ -680,30 +680,16 @@ EXPORT_SYMBOL_GPL(pinctrl_generic_remove
+ * pinctrl_generic_free_groups() - removes all pin groups
+ * @pctldev: pin controller device
+ *
+- * Note that the caller must take care of locking.
++ * Note that the caller must take care of locking. The pinctrl groups
++ * are allocated with devm_kzalloc() so no need to free them here.
+ */
+ static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev)
+ {
+ struct radix_tree_iter iter;
+- struct group_desc *group;
+- unsigned long *indices;
+ void **slot;
+- int i = 0;
+-
+- indices = devm_kzalloc(pctldev->dev, sizeof(*indices) *
+- pctldev->num_groups, GFP_KERNEL);
+- if (!indices)
+- return;
+
+ radix_tree_for_each_slot(slot, &pctldev->pin_group_tree, &iter, 0)
+- indices[i++] = iter.index;
+-
+- for (i = 0; i < pctldev->num_groups; i++) {
+- group = radix_tree_lookup(&pctldev->pin_group_tree,
+- indices[i]);
+- radix_tree_delete(&pctldev->pin_group_tree, indices[i]);
+- devm_kfree(pctldev->dev, group);
+- }
++ radix_tree_delete(&pctldev->pin_group_tree, iter.index);
+
+ pctldev->num_groups = 0;
+ }
+--- a/drivers/pinctrl/pinmux.c
++++ b/drivers/pinctrl/pinmux.c
+@@ -826,30 +826,17 @@ EXPORT_SYMBOL_GPL(pinmux_generic_remove_
+ * pinmux_generic_free_functions() - removes all functions
+ * @pctldev: pin controller device
+ *
+- * Note that the caller must take care of locking.
++ * Note that the caller must take care of locking. The pinctrl
++ * functions are allocated with devm_kzalloc() so no need to free
++ * them here.
+ */
+ void pinmux_generic_free_functions(struct pinctrl_dev *pctldev)
+ {
+ struct radix_tree_iter iter;
+- struct function_desc *function;
+- unsigned long *indices;
+ void **slot;
+- int i = 0;
+-
+- indices = devm_kzalloc(pctldev->dev, sizeof(*indices) *
+- pctldev->num_functions, GFP_KERNEL);
+- if (!indices)
+- return;
+
+ radix_tree_for_each_slot(slot, &pctldev->pin_function_tree, &iter, 0)
+- indices[i++] = iter.index;
+-
+- for (i = 0; i < pctldev->num_functions; i++) {
+- function = radix_tree_lookup(&pctldev->pin_function_tree,
+- indices[i]);
+- radix_tree_delete(&pctldev->pin_function_tree, indices[i]);
+- devm_kfree(pctldev->dev, function);
+- }
++ radix_tree_delete(&pctldev->pin_function_tree, iter.index);
+
+ pctldev->num_functions = 0;
+ }
--- /dev/null
+From 97ba26b8a9343008504d4e3a87d212bc07b05212 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 1 Apr 2017 15:59:21 +0200
+Subject: pinctrl: meson: meson8b: fix the NAND DQS pins
+
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+commit 97ba26b8a9343008504d4e3a87d212bc07b05212 upstream.
+
+The nand_groups table uses different names for the NAND DQS pins than
+the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0).
+This prevents using the NAND DQS pins in the devicetree.
+
+Fix this by ensuring that the GROUP() definition and the
+meson8b_cbus_groups use the same name for these pins.
+
+Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Acked-by: Kevin Hilman <khilman@baylibre.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/meson/pinctrl-meson8b.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/meson/pinctrl-meson8b.c
++++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
+@@ -739,8 +739,8 @@ static const char * const sdxc_c_groups[
+ static const char * const nand_groups[] = {
+ "nand_io", "nand_io_ce0", "nand_io_ce1",
+ "nand_io_rb0", "nand_ale", "nand_cle",
+- "nand_wen_clk", "nand_ren_clk", "nand_dqs0",
+- "nand_dqs1"
++ "nand_wen_clk", "nand_ren_clk", "nand_dqs_0",
++ "nand_dqs_1"
+ };
+
+ static const char * const nor_groups[] = {
--- /dev/null
+From da6c2addf66d7ff7d0b090d6267d4292f951e4e6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Thu, 18 May 2017 11:23:55 +0200
+Subject: pinctrl: mxs: atomically switch mux and drive strength config
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+
+commit da6c2addf66d7ff7d0b090d6267d4292f951e4e6 upstream.
+
+To set the mux mode of a pin two bits must be set. Up to now this is
+implemented using the following idiom:
+
+ writel(mask, reg + CLR);
+ writel(value, reg + SET);
+
+. This however results in the mux mode being 0 between the two writes.
+
+On my machine there is an IC's reset pin connected to LCD_D20. The
+bootloader configures this pin as GPIO output-high (i.e. not holding the
+IC in reset). When Linux reconfigures the pin to GPIO the short time
+LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse
+the connected IC.
+
+The same problem is present for the pin's drive strength setting which is
+reset to low drive strength before using the right value.
+
+So instead of relying on the hardware to modify the register setting
+using two writes implement the bit toggling using read-modify-write.
+
+Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support")
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/freescale/pinctrl-mxs.c | 16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
++++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
+@@ -194,6 +194,16 @@ static int mxs_pinctrl_get_func_groups(s
+ return 0;
+ }
+
++static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
++{
++ u32 tmp;
++
++ tmp = readl(reg);
++ tmp &= ~(mask << shift);
++ tmp |= value << shift;
++ writel(tmp, reg);
++}
++
+ static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+ {
+@@ -211,8 +221,7 @@ static int mxs_pinctrl_set_mux(struct pi
+ reg += bank * 0x20 + pin / 16 * 0x10;
+ shift = pin % 16 * 2;
+
+- writel(0x3 << shift, reg + CLR);
+- writel(g->muxsel[i] << shift, reg + SET);
++ mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
+ }
+
+ return 0;
+@@ -279,8 +288,7 @@ static int mxs_pinconf_group_set(struct
+ /* mA */
+ if (config & MA_PRESENT) {
+ shift = pin % 8 * 4;
+- writel(0x3 << shift, reg + CLR);
+- writel(ma << shift, reg + SET);
++ mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
+ }
+
+ /* vol */
--- /dev/null
+From 3908632fb829d73317c64c3d04f584b49f62e4ae Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 29 Mar 2017 21:36:51 +0300
+Subject: pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signal
+
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+
+commit 3908632fb829d73317c64c3d04f584b49f62e4ae upstream.
+
+The R8A7791 PFC driver was apparently based on the preliminary revisions
+of the user's manual, which omitted the DVC_MUTE signal altogether in
+the PFC section. The modern manual has the signal described, so just add
+the necassary data to the driver...
+
+Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+@@ -203,7 +203,7 @@ enum {
+
+ /* IPSR6 */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+- FN_SCIF_CLK, FN_BPFCLK_E,
++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
+ FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
+ FN_SCIFA2_RXD, FN_FMIN_E,
+ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
+@@ -573,7 +573,7 @@ enum {
+
+ /* IPSR6 */
+ AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
+- SCIF_CLK_MARK, BPFCLK_E_MARK,
++ SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
+ AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
+ SCIFA2_RXD_MARK, FMIN_E_MARK,
+ AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
+@@ -1090,6 +1090,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
++ PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
+ PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
+ PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
+ PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
+@@ -5896,7 +5897,7 @@ static const struct pinmux_cfg_reg pinmu
+ 0, 0,
+ /* IP6_2_0 [3] */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+- FN_SCIF_CLK, 0, FN_BPFCLK_E,
++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
--- /dev/null
+From da7a692fbbab07f4e9798b5b52798f6e3256dd8f Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 29 Mar 2017 21:36:50 +0300
+Subject: pinctrl: sh-pfc: r8a7791: Add missing HSCIF1 pinmux data
+
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+
+commit da7a692fbbab07f4e9798b5b52798f6e3256dd8f upstream.
+
+The R8A7791 PFC driver was apparently based on the preliminary revisions
+of the user's manual, which omitted the HSCIF1 group E signals in the
+IPSR4 register description. This would cause HSCIF1's probe to fail with
+the messages like below:
+
+sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1989
+sh-sci e62c8000.serial: Error applying setting, reverse things back
+sh-sci: probe of e62c8000.serial failed with error -22
+
+Add the neceassary PINMUX_IPSR_MSEL() invocations for the HSCK1_E,
+HCTS1#_E, and HRTS1#_E signals...
+
+Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+@@ -1010,14 +1010,17 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
+ PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
++ PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
+ PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
+ PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
+ PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
+ PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
++ PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
+ PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
+ PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
+ PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
++ PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
+ PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
+ PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
+ PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
--- /dev/null
+From 58439280f84e6b39fd7d61f25ab30489c1aaf0a9 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 30 Mar 2017 23:20:48 +0300
+Subject: pinctrl: sh-pfc: r8a7791: Fix SCIF2 pinmux data
+
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+
+commit 58439280f84e6b39fd7d61f25ab30489c1aaf0a9 upstream.
+
+PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong
+1st argument -- most probably a result of cut&paste programming...
+
+Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+@@ -1099,7 +1099,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
+ PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
+- PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
++ PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
+ PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
--- /dev/null
+From 5f4c8cafe1148f8a91287072815df8f0b66f0e5c Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Tue, 4 Apr 2017 23:20:16 +0300
+Subject: pinctrl: sh-pfc: r8a7794: Swap ATA signals
+
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+
+commit 5f4c8cafe1148f8a91287072815df8f0b66f0e5c upstream.
+
+All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver
+has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this.
+
+Fixes: 43c4436e2f18 ("pinctrl: sh-pfc: add R8A7794 PFC support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+@@ -281,8 +281,8 @@ enum {
+ FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
+ FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
+ FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
+- FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
+- FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
++ FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
++ FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B,
+
+ /* IPSR13 */
+ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
+@@ -575,8 +575,8 @@ enum {
+ ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
+ VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
+ SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
+- ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
+- VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
++ ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
++ VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK,
+
+ /* IPSR13 */
+ SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
+@@ -1413,13 +1413,13 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
+ PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
+- PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),
++ PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
+ PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
+ PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
+ PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
+ PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
+- PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),
++ PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
+ PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
+
+ /* IPSR13 */
+@@ -4938,10 +4938,10 @@ static const struct pinmux_cfg_reg pinmu
+ 0, 0, 0, 0,
+ /* IP12_29_27 [3] */
+ FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
+- FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
++ FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
+ /* IP12_26_24 [3] */
+ FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
+- FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
++ FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
+ /* IP12_23_21 [3] */
+ FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
+ FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
--- /dev/null
+From 4324b6084f45b9faebda8d6563d8625d22b4b5df Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Sat, 11 Mar 2017 12:26:09 +0100
+Subject: pinctrl: sh-pfc: r8a7795: Fix hscif2_clk_b and hscif4_ctrl
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+commit 4324b6084f45b9faebda8d6563d8625d22b4b5df upstream.
+
+Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[].
+
+Fixes: a56069c46c102710 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+@@ -2167,7 +2167,7 @@ static const unsigned int hscif2_clk_b_p
+ RCAR_GP_PIN(6, 21),
+ };
+ static const unsigned int hscif2_clk_b_mux[] = {
+- HSCK1_B_MARK,
++ HSCK2_B_MARK,
+ };
+ static const unsigned int hscif2_ctrl_b_pins[] = {
+ /* RTS, CTS */
+@@ -2240,7 +2240,7 @@ static const unsigned int hscif4_ctrl_pi
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+ };
+ static const unsigned int hscif4_ctrl_mux[] = {
+- HRTS4_N_MARK, HCTS3_N_MARK,
++ HRTS4_N_MARK, HCTS4_N_MARK,
+ };
+
+ static const unsigned int hscif4_data_b_pins[] = {
--- /dev/null
+From 3091ae775fae17084013021d01513bc1ad274e6a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 9 Mar 2017 19:20:48 +0100
+Subject: pinctrl: sh-pfc: Update info pointer after SoC-specific init
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+commit 3091ae775fae17084013021d01513bc1ad274e6a upstream.
+
+Update the sh_pfc_soc_info pointer after calling the SoC-specific
+initialization function, as it may have been updated to e.g. handle
+different SoC revisions. This makes sure the correct subdriver name is
+printed later.
+
+Fixes: 0c151062f32c9db8 ("sh-pfc: Add support for SoC-specific initialization")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/core.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -586,6 +586,9 @@ static int sh_pfc_probe(struct platform_
+ ret = info->ops->init(pfc);
+ if (ret < 0)
+ return ret;
++
++ /* .init() may have overridden pfc->info */
++ info = pfc->info;
+ }
+
+ /* Enable dummy states for those platforms without pinctrl support */
--- /dev/null
+From b7c747d4627462f25b3daabf49c18895a6722faa Mon Sep 17 00:00:00 2001
+From: Alexandre TORGUE <alexandre.torgue@st.com>
+Date: Tue, 30 May 2017 16:43:04 +0200
+Subject: pinctrl: stm32: Fix bad function call
+
+From: Alexandre TORGUE <alexandre.torgue@st.com>
+
+commit b7c747d4627462f25b3daabf49c18895a6722faa upstream.
+
+In stm32_pconf_parse_conf function, stm32_pmx_gpio_set_direction is
+called with wrong parameter value. Indeed, using NULL value for range
+will raise an oops.
+
+Fixes: aceb16dc2da5 ("pinctrl: Add STM32 MCUs support")
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/stm32/pinctrl-stm32.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
++++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
+@@ -786,7 +786,7 @@ static int stm32_pconf_parse_conf(struct
+ break;
+ case PIN_CONFIG_OUTPUT:
+ __stm32_gpio_set(bank, offset, arg);
+- ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
++ ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
+ break;
+ default:
+ ret = -EINVAL;
--- /dev/null
+From 7903d4f5e1dec53963cba9b1bc472a76a3532e07 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Mon, 22 May 2017 14:25:49 +0800
+Subject: pinctrl: sunxi: Fix SPDIF function name for A83T
+
+From: Chen-Yu Tsai <wens@csie.org>
+
+commit 7903d4f5e1dec53963cba9b1bc472a76a3532e07 upstream.
+
+We use well known standard names for functions that have name, such as
+I2C, SPI, SPDIF, etc..
+
+Fix the function name of SPDIF, which was named OWA (One Wire Audio)
+based on Allwinner datasheets.
+
+Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller
+ support")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
+@@ -394,7 +394,7 @@ static const struct sunxi_desc_pin sun8i
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+- SUNXI_FUNCTION(0x3, "owa")), /* DOUT */
++ SUNXI_FUNCTION(0x3, "spdif")), /* DOUT */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
usb-usbip-set-buffer-pointers-to-null-after-free.patch
usb-fix-typo-in-the-definition-of-endpointrequest.patch
usb-core-fix-device-node-leak.patch
+arm-remove-wrong-config_proc_sysctl-ifdef.patch
+pinctrl-sh-pfc-r8a7794-swap-ata-signals.patch
+pinctrl-sh-pfc-r8a7791-fix-scif2-pinmux-data.patch
+pinctrl-sh-pfc-r8a7791-add-missing-dvc_mute-signal.patch
+pinctrl-sh-pfc-r8a7795-fix-hscif2_clk_b-and-hscif4_ctrl.patch
+pinctrl-meson-meson8b-fix-the-nand-dqs-pins.patch
+pinctrl-stm32-fix-bad-function-call.patch
+pinctrl-sunxi-fix-spdif-function-name-for-a83t.patch
+pinctrl-core-fix-warning-by-removing-bogus-code.patch
+pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch
+pinctrl-sh-pfc-r8a7791-add-missing-hscif1-pinmux-data.patch
+pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
