]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1
authorJudith Mendez <jm@ti.com>
Wed, 20 Aug 2025 19:30:47 +0000 (14:30 -0500)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 28 Aug 2025 14:34:35 +0000 (16:34 +0200)
commit d2d7a96b29ea6ab093973a1a37d26126db70c79f upstream.

This adds SDHCI_AM654_QUIRK_DISABLE_HS400 quirk which shall be used
to disable HS400 support. AM62P SR1.0 and SR1.1 do not support HS400
due to errata i2458 [0] so disable HS400 for these SoC revisions.

[0] https://www.ti.com/lit/er/sprz574a/sprz574a.pdf
Fixes: 37f28165518f ("arm64: dts: ti: k3-am62p: Add ITAP/OTAP values for MMC")
Cc: stable@vger.kernel.org
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20250820193047.4064142-1-jm@ti.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/mmc/host/sdhci_am654.c

index 9e94998e8df7d2d939f8d3e88825192bfb044e82..2173935727329003c0be907d409e1f359d381408 100644 (file)
@@ -156,6 +156,7 @@ struct sdhci_am654_data {
 
 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
 #define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1)
+#define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(2)
 };
 
 struct window {
@@ -765,6 +766,7 @@ static int sdhci_am654_init(struct sdhci_host *host)
 {
        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
        struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
+       struct device *dev = mmc_dev(host->mmc);
        u32 ctl_cfg_2 = 0;
        u32 mask;
        u32 val;
@@ -820,6 +822,12 @@ static int sdhci_am654_init(struct sdhci_host *host)
        if (ret)
                goto err_cleanup_host;
 
+       if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400 &&
+           host->mmc->caps2 & (MMC_CAP2_HS400 | MMC_CAP2_HS400_ES)) {
+               dev_info(dev, "HS400 mode not supported on this silicon revision, disabling it\n");
+               host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
+       }
+
        ret = __sdhci_add_host(host);
        if (ret)
                goto err_cleanup_host;
@@ -883,6 +891,12 @@ static int sdhci_am654_get_of_property(struct platform_device *pdev,
        return 0;
 }
 
+static const struct soc_device_attribute sdhci_am654_descope_hs400[] = {
+       { .family = "AM62PX", .revision = "SR1.0" },
+       { .family = "AM62PX", .revision = "SR1.1" },
+       { /* sentinel */ }
+};
+
 static const struct of_device_id sdhci_am654_of_match[] = {
        {
                .compatible = "ti,am654-sdhci-5.1",
@@ -975,6 +989,10 @@ static int sdhci_am654_probe(struct platform_device *pdev)
                goto err_pltfm_free;
        }
 
+       soc = soc_device_match(sdhci_am654_descope_hs400);
+       if (soc)
+               sdhci_am654->quirks |= SDHCI_AM654_QUIRK_DISABLE_HS400;
+
        host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch;
        host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;