riscv64: Add support for csrrc

diff --git a/README.riscv64 b/README.riscv64
index 04f2bc95728d53eb5db6adc7d95e393d7134ed65..6ce2a082f01af897628214e3b25abd064baf45a9 100644 (file)
--- a/README.riscv64
+++ b/README.riscv64
@@ -14,7 +14,7 @@ The following ISA base and extensions are currently supported:
 | RV64A        | Atomic                            |   22/22 | (2)      |
 | RV64F        | Single-precision floating-point   |   30/30 | (3)      |
 | RV64D        | Double-precision floating-point   |   32/32 |          |
-| RV64Zicsr    | Control & status register         |     2/6 | (4), (5) |
+| RV64Zicsr    | Control & status register         |     3/6 | (4), (5) |
 | RV64Zifencei | Instruction-fetch fence           |     0/1 | (6)      |
 | RV64C        | Compressed                        |   37/37 |          |
 
@@ -22,7 +22,7 @@ Notes:
 (1) MULHSU is not recognized.
 (2) LR and SC use the VEX "fallback" method which suffers from the ABA problem.
 (3) Operations do not check if the input operands are correctly NaN-boxed.
-(4) CSRRC, CSRRWI, CSRRSI and CSRRCI are not recognized.
+(4) CSRRWI, CSRRSI and CSRRCI are not recognized.
 (5) Only registers fflags, frm and fcsr are accepted.
 (6) FENCE.I is not recognized.
 

diff --git a/VEX/priv/guest_riscv64_toIR.c b/VEX/priv/guest_riscv64_toIR.c
index 1c8a845e82b092edf4519e5fdfb6f8ac3764cfcd..5d9b903c9b7fd3bc010fa3f0dff3e55e76ecf72d 100644 (file)
--- a/VEX/priv/guest_riscv64_toIR.c
+++ b/VEX/priv/guest_riscv64_toIR.c
@@ -3170,15 +3170,15 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
 {
    /* ------------ RV64Zicsr standard extension ------------- */
 
-   /* --------------- csrr{w,s} rd, csr, rs1 ---------------- */
+   /* -------------- csrr{w,s,c} rd, csr, rs1 --------------- */
    if (INSN(6, 0) == 0b1110011) {
       UInt rd     = INSN(11, 7);
       UInt funct3 = INSN(14, 12);
       UInt rs1    = INSN(19, 15);
       UInt csr    = INSN(31, 20);
-      if ((funct3 != 0b001 && funct3 != 0b010) ||
+      if ((funct3 != 0b001 && funct3 != 0b010 && funct3 != 0b011) ||
           (csr != 0x001 && csr != 0x002 && csr != 0x003)) {
-         /* Invalid CSRR{W,S}, fall through. */
+         /* Invalid CSRR{W,S,C}, fall through. */
       } else {
          switch (csr) {
          case 0x001: {
@@ -3201,6 +3201,11 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                expr = binop(Iop_Or32, mkexpr(fcsr),
                             binop(Iop_And32, getIReg32(rs1), mkU32(0x1f)));
                break;
+            case 0b011:
+               expr = binop(Iop_And32, mkexpr(fcsr),
+                            unop(Iop_Not32, binop(Iop_And32, getIReg32(rs1),
+                                                  mkU32(0x1f))));
+               break;
             default:
                vassert(0);
             }
@@ -3232,6 +3237,14 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                                   binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
                                   mkU8(5)));
                break;
+            case 0b011:
+               expr =
+                  binop(Iop_And32, mkexpr(fcsr),
+                        unop(Iop_Not32,
+                             binop(Iop_Shl32,
+                                   binop(Iop_And32, getIReg32(rs1), mkU32(0x7)),
+                                   mkU8(5))));
+               break;
             default:
                vassert(0);
             }
@@ -3254,6 +3267,11 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
                expr = binop(Iop_Or32, mkexpr(fcsr),
                             binop(Iop_And32, getIReg32(rs1), mkU32(0xff)));
                break;
+            case 0b011:
+               expr = binop(Iop_And32, mkexpr(fcsr),
+                            unop(Iop_Not32, binop(Iop_And32, getIReg32(rs1),
+                                                  mkU32(0xff))));
+               break;
             default:
                vassert(0);
             }
@@ -3272,6 +3290,9 @@ static Bool dis_RV64Zicsr(/*MB_OUT*/ DisResult* dres,
          case 0b010:
             name = "csrrs";
             break;
+         case 0b011:
+            name = "csrrc";
+            break;
          default:
             vassert(0);
          }

diff --git a/none/tests/riscv64/csr.c b/none/tests/riscv64/csr.c
index 48c9482aaf8e569692e8b2bd8841178aa8f1d4c5..41360be6def6816481ec3868d38c90f8b0c0c015 100644 (file)
--- a/none/tests/riscv64/csr.c
+++ b/none/tests/riscv64/csr.c
@@ -77,7 +77,38 @@ static void test_csr64_shared(void)
    TESTINST_1_1_CSR(4, "csrrs a0, fcsr, zero", 0xff, 0x00, a0, fcsr, zero);
 
    /* ----------------- csrrc rd, csr, rs1 ------------------ */
-   /* Not currently handled. */
+   /* fflags */
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0x01, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0x1f, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0xff, 0x1e, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0xff, 0x00, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, a1", 0x00, 0xff, a0, fcsr, a1);
+
+   TESTINST_1_1_CSR(4, "csrrc t5, fflags, t6", 0x00, 0x01, t5, fcsr, t6);
+   TESTINST_1_1_CSR(4, "csrrc zero, fflags, a1", 0xff, 0x01, zero, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fflags, zero", 0xff, 0x00, a0, fcsr, zero);
+
+   /* frm */
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0x1, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0x7, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0xff, 0x6, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0xff, 0x0, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, a1", 0x00, 0xff, a0, fcsr, a1);
+
+   TESTINST_1_1_CSR(4, "csrrc t5, frm, t6", 0x00, 0x1, t5, fcsr, t6);
+   TESTINST_1_1_CSR(4, "csrrc zero, frm, a1", 0xff, 0x1, zero, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, frm, zero", 0xff, 0x0, a0, fcsr, zero);
+
+   /* fcsr */
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0x01, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0xff, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0xff, 0xfe, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0xff, 0x00, a0, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, a1", 0x00, 0xff, a0, fcsr, a1);
+
+   TESTINST_1_1_CSR(4, "csrrc t5, fcsr, t6", 0x00, 0x01, t5, fcsr, t6);
+   TESTINST_1_1_CSR(4, "csrrc zero, fcsr, a1", 0xff, 0x01, zero, fcsr, a1);
+   TESTINST_1_1_CSR(4, "csrrc a0, fcsr, zero", 0xff, 0x00, a0, fcsr, zero);
 
    /* -------------- csrrwi rd, csr, uimm[4:0] -------------- */
    /* Not currently handled. */

diff --git a/none/tests/riscv64/csr.stdout.exp b/none/tests/riscv64/csr.stdout.exp
index 679a6b9a15d40eb9491abcedb5bf4d9bbc870cb1..e773e205cacc331cb63c6caa88cfeaf3b985e788 100644 (file)
--- a/none/tests/riscv64/csr.stdout.exp
+++ b/none/tests/riscv64/csr.stdout.exp
@@ -143,3 +143,75 @@ csrrs zero, fcsr, a1 ::
 csrrs a0, fcsr, zero ::
   inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
   output: a0=0x00000000000000ff, fcsr=0x00000000000000ff
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x000000000000001f, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x000000000000001e, fcsr=0x00000000000000ff
+  output: a0=0x000000000000001f, fcsr=0x00000000000000e1
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x000000000000001f, fcsr=0x00000000000000ff
+csrrc a0, fflags, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc t5, fflags, t6 ::
+  inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
+  output: t5=0x0000000000000000, fcsr=0x0000000000000000
+csrrc zero, fflags, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
+  output: zero=0x0000000000000000, fcsr=0x00000000000000fe
+csrrc a0, fflags, zero ::
+  inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x000000000000001f, fcsr=0x00000000000000ff
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000007, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000006, fcsr=0x00000000000000ff
+  output: a0=0x0000000000000007, fcsr=0x000000000000003f
+csrrc a0, frm, a1 ::
+  inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x0000000000000007, fcsr=0x00000000000000ff
+csrrc a0, frm, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc t5, frm, t6 ::
+  inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
+  output: t5=0x0000000000000000, fcsr=0x0000000000000000
+csrrc zero, frm, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
+  output: zero=0x0000000000000000, fcsr=0x00000000000000df
+csrrc a0, frm, zero ::
+  inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x0000000000000007, fcsr=0x00000000000000ff
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x00000000000000fe, fcsr=0x00000000000000ff
+  output: a0=0x00000000000000ff, fcsr=0x0000000000000001
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x00000000000000ff, fcsr=0x00000000000000ff
+csrrc a0, fcsr, a1 ::
+  inputs: a1=0x00000000000000ff, fcsr=0x0000000000000000
+  output: a0=0x0000000000000000, fcsr=0x0000000000000000
+csrrc t5, fcsr, t6 ::
+  inputs: t6=0x0000000000000001, fcsr=0x0000000000000000
+  output: t5=0x0000000000000000, fcsr=0x0000000000000000
+csrrc zero, fcsr, a1 ::
+  inputs: a1=0x0000000000000001, fcsr=0x00000000000000ff
+  output: zero=0x0000000000000000, fcsr=0x00000000000000fe
+csrrc a0, fcsr, zero ::
+  inputs: zero=0x0000000000000000, fcsr=0x00000000000000ff
+  output: a0=0x00000000000000ff, fcsr=0x00000000000000ff