perf/arm-cmn: Make cycle counts less surprising

By default, CMN has automatic clock-gating with the implication that
a DTC's cycle counter may not increment while the DTC is sufficiently
idle. Given that we may have up to 4 DTCs to choose from when scheduling
a cycles event, this may potentially lead to surprising results if
trying to measure metrics based on activity in a different DTC domain
from where cycles end up being counted. Furthermore, since the details
of internal clock gating are not documented, we can't even reason about
what "active" cycles for a DTC actually mean relative to the activity of
other nodes within the same nominal DTC domain.

Make the reasonable assumption that if the user wants to count cycles,
they almost certainly want to count all of the cycles, and disable clock
gating while a DTC's cycle counter is in use.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/c47cfdc09e907b1d7753d142a7e659982cceb246.1725296395.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c
index 5b0edeb693946bf0b9fcb4e14f6cd25cec431a07..2205c183ec1b8bab06145d025bd9db02016c12e8 100644 (file)
--- a/drivers/perf/arm-cmn.c
+++ b/drivers/perf/arm-cmn.c
@@ -119,6 +119,7 @@
 /* The DTC node is where the magic happens */
 #define CMN_DT_DTC_CTL                 0x0a00
 #define CMN_DT_DTC_CTL_DT_EN           BIT(0)
+#define CMN_DT_DTC_CTL_CG_DISABLE      BIT(10)
 
 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
 #define _CMN_DT_CNT_REG(n)             ((((n) / 2) * 4 + (n) % 2) * 4)
@@ -1546,9 +1547,12 @@ static void arm_cmn_event_start(struct perf_event *event, int flags)
        int i;
 
        if (type == CMN_TYPE_DTC) {
-               i = hw->dtc_idx[0];
-               writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
-               cmn->dtc[i].cc_active = true;
+               struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0];
+
+               writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE,
+                              dtc->base + CMN_DT_DTC_CTL);
+               writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
+               dtc->cc_active = true;
        } else if (type == CMN_TYPE_WP) {
                u64 val = CMN_EVENT_WP_VAL(event);
                u64 mask = CMN_EVENT_WP_MASK(event);
@@ -1577,8 +1581,10 @@ static void arm_cmn_event_stop(struct perf_event *event, int flags)
        int i;
 
        if (type == CMN_TYPE_DTC) {
-               i = hw->dtc_idx[0];
-               cmn->dtc[i].cc_active = false;
+               struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0];
+
+               dtc->cc_active = false;
+               writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
        } else if (type == CMN_TYPE_WP) {
                for_each_hw_dn(hw, dn, i) {
                        void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);