drm/i915: fix TLB invalidation for Gen12.50 video and compute engines

In case of Gen12.50 video and compute engines, TLB_INV registers are
masked - to modify one bit, corresponding bit in upper half of the register
must be enabled, otherwise nothing happens.

Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221214075439.402485-1-andrzej.hajda@intel.com
(cherry picked from commit 4d5cf7b1680a1e6db327e3c935ef58325cbedb2c)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 767e329e1cc5fd4eed40fd8cc6b969d5c4978cce..9c18b5f2e7892bd15cb54dc4d378d2f4f63911f4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1109,9 +1109,15 @@ static void mmio_invalidate_full(struct intel_gt *gt)
                        continue;
 
                if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+                       u32 val = BIT(engine->instance);
+
+                       if (engine->class == VIDEO_DECODE_CLASS ||
+                           engine->class == VIDEO_ENHANCEMENT_CLASS ||
+                           engine->class == COMPUTE_CLASS)
+                               val = _MASKED_BIT_ENABLE(val);
                        intel_gt_mcr_multicast_write_fw(gt,
                                                        xehp_regs[engine->class],
-                                                       BIT(engine->instance));
+                                                       val);
                } else {
                        rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
                        if (!i915_mmio_reg_offset(rb.reg))