clk: meson: meson8b: fix the naming of the APB clocks

Fix a typo in the APB clock names by renaming them from "abp" to "apb".
No functional changes.

Fixes: a7d19b05ce817d ("clk: meson: meson8b: add the CPU clock post divider clocks")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190210222603.6404-2-martin.blumenstingl@googlemail.com

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 23b1e355a849db695cf1784bc3fd8ed82107e5e5..576ad42252d04ec524e093d6e4b3ba686761c112 100644 (file)
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -804,16 +804,16 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
        },
 };
 
-static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 };
-static struct clk_regmap meson8b_abp_clk_sel = {
+static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
+static struct clk_regmap meson8b_apb_clk_sel = {
        .data = &(struct clk_regmap_mux_data){
                .offset = HHI_SYS_CPU_CLK_CNTL1,
                .mask = 0x7,
                .shift = 3,
-               .table = mux_table_abp,
+               .table = mux_table_apb,
        },
        .hw.init = &(struct clk_init_data){
-               .name = "abp_clk_sel",
+               .name = "apb_clk_sel",
                .ops = &clk_regmap_mux_ops,
                .parent_names = (const char *[]){ "cpu_clk_div2",
                                                  "cpu_clk_div3",
@@ -826,16 +826,16 @@ static struct clk_regmap meson8b_abp_clk_sel = {
        },
 };
 
-static struct clk_regmap meson8b_abp_clk_gate = {
+static struct clk_regmap meson8b_apb_clk_gate = {
        .data = &(struct clk_regmap_gate_data){
                .offset = HHI_SYS_CPU_CLK_CNTL1,
                .bit_idx = 16,
                .flags = CLK_GATE_SET_TO_DISABLE,
        },
        .hw.init = &(struct clk_init_data){
-               .name = "abp_clk_dis",
+               .name = "apb_clk_dis",
                .ops = &clk_regmap_gate_ro_ops,
-               .parent_names = (const char *[]){ "abp_clk_sel" },
+               .parent_names = (const char *[]){ "apb_clk_sel" },
                .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
@@ -1911,8 +1911,8 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
                [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
                [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
                [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
-               [CLKID_ABP_SEL]             = &meson8b_abp_clk_sel.hw,
-               [CLKID_ABP]                 = &meson8b_abp_clk_gate.hw,
+               [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
+               [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
                [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
                [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
                [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
@@ -2093,8 +2093,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
                [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
                [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
                [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
-               [CLKID_ABP_SEL]             = &meson8b_abp_clk_sel.hw,
-               [CLKID_ABP]                 = &meson8b_abp_clk_gate.hw,
+               [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
+               [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
                [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
                [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
                [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
@@ -2262,8 +2262,8 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
        &meson8b_fixed_pll_dco,
        &meson8b_hdmi_pll_dco,
        &meson8b_sys_pll_dco,
-       &meson8b_abp_clk_sel,
-       &meson8b_abp_clk_gate,
+       &meson8b_apb_clk_sel,
+       &meson8b_apb_clk_gate,
        &meson8b_periph_clk_sel,
        &meson8b_periph_clk_gate,
        &meson8b_axi_clk_sel,

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index f212e2304ff5bb4ae243a25ae6feb50f71a57665..b8c58faeae525cf588f36a10f6836a792c2a163f 100644 (file)
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -92,7 +92,7 @@
 #define CLKID_CPU_CLK_DIV6     120
 #define CLKID_CPU_CLK_DIV7     121
 #define CLKID_CPU_CLK_DIV8     122
-#define CLKID_ABP_SEL          123
+#define CLKID_APB_SEL          123
 #define CLKID_PERIPH_SEL       125
 #define CLKID_AXI_SEL          127
 #define CLKID_L2_DRAM_SEL      129