case 0xC8 ... 0xCF: /* FCMOVNE(NZ) ST(i), ST(0) */
r_src = (UInt)modrm - 0xC8;
- DIP("fcmovnz %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovnz %%st(%u), %%st(0)\n", r_src);
put_ST_UNCHECKED(
0,
IRExpr_Mux0X(
case 0xD0 ... 0xD7: /* FCMOVNBE ST(i), ST(0) */
r_src = (UInt)modrm - 0xD0;
- DIP("fcmovnbe %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovnbe %%st(%u), %%st(0)\n", r_src);
put_ST_UNCHECKED(
0,
IRExpr_Mux0X(
if (vex_streq(function_name, "x86g_calculate_eflags_all")) {
/* specialise calls to above "calculate_eflags_all" function */
- IRExpr *cc_op, *cc_dep1, *cc_dep2, *cc_ndep;
+ IRExpr *cc_op, *cc_dep1; /*, *cc_dep2, *cc_ndep; */
vassert(arity == 4);
cc_op = args[0];
cc_dep1 = args[1];
- cc_dep2 = args[2];
- cc_ndep = args[3];
+ /* cc_dep2 = args[2]; */
+ /* cc_ndep = args[3]; */
if (isU32(cc_op, X86G_CC_OP_COPY)) {
/* eflags after COPY are stored in DEP1. */
vpanic("doRegisterAllocation: "
"first event for vreg is Read");
}
- vreg_lrs[k].dead_before = ii + 1;
+ vreg_lrs[k].dead_before = toShort(ii + 1);
break;
case HRmWrite:
if (vreg_lrs[k].live_after == INVALID_INSTRNO)
- vreg_lrs[k].live_after = ii;
- vreg_lrs[k].dead_before = ii + 1;
+ vreg_lrs[k].live_after = toShort(ii);
+ vreg_lrs[k].dead_before = toShort(ii + 1);
break;
case HRmModify:
if (vreg_lrs[k].live_after == INVALID_INSTRNO) {
vpanic("doRegisterAllocation: "
"first event for vreg is Modify");
}
- vreg_lrs[k].dead_before = ii + 1;
+ vreg_lrs[k].dead_before = toShort(ii + 1);
break;
default:
vpanic("doRegisterAllocation(1)");
if (0)
vex_printf("FLUSH 1 (%d,%d)\n", flush_la, flush_db);
rreg_lrs[rreg_lrs_used].rreg = rreg;
- rreg_lrs[rreg_lrs_used].live_after = flush_la;
- rreg_lrs[rreg_lrs_used].dead_before = flush_db;
+ rreg_lrs[rreg_lrs_used].live_after = toShort(flush_la);
+ rreg_lrs[rreg_lrs_used].dead_before = toShort(flush_db);
rreg_lrs_used++;
}
vex_printf("FLUSH 2 (%d,%d)\n",
rreg_live_after[j], rreg_dead_before[j]);
rreg_lrs[rreg_lrs_used].rreg = available_real_regs[j];
- rreg_lrs[rreg_lrs_used].live_after = rreg_live_after[j];
- rreg_lrs[rreg_lrs_used].dead_before = rreg_dead_before[j];
+ rreg_lrs[rreg_lrs_used].live_after = toShort(rreg_live_after[j]);
+ rreg_lrs[rreg_lrs_used].dead_before = toShort(rreg_dead_before[j]);
rreg_lrs_used++;
}
/* This reflects LibVEX's hard-wired knowledge of the baseBlock
layout: the guest state, then an equal sized area following
it for shadow state, and then the spill area. */
- vreg_lrs[j].spill_offset = guest_sizeB * 2 + k * 8;
+ vreg_lrs[j].spill_offset = toShort(guest_sizeB * 2 + k * 8);
/* if (j > max_ss_no) */
/* max_ss_no = j; */