crypto: hisilicon/hpre - enable all clusters clock gating

Currently, the driver enables clock gating for only one cluster.
However, the new hardware has three clusters. Therefore, clock
gating needs to be enabled based on the number of clusters on the
current hardware.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c
index 6b536ad2ada52a4096457b626de0aef15311df95..23e8fb9414af3729ad56a275a5bc299eb1877b4f 100644 (file)
--- a/drivers/crypto/hisilicon/hpre/hpre_main.c
+++ b/drivers/crypto/hisilicon/hpre/hpre_main.c
@@ -593,6 +593,8 @@ static void hpre_close_sva_prefetch(struct hisi_qm *qm)
 
 static void hpre_enable_clock_gate(struct hisi_qm *qm)
 {
+       unsigned long offset;
+       u8 clusters_num, i;
        u32 val;
 
        if (qm->ver < QM_HW_V3)
@@ -606,17 +608,23 @@ static void hpre_enable_clock_gate(struct hisi_qm *qm)
        val |= HPRE_PEH_CFG_AUTO_GATE_EN;
        writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
 
-       val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
-       val |= HPRE_CLUSTER_DYN_CTL_EN;
-       writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
-
-       val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
-       val |= HPRE_CORE_GATE_EN;
-       writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
+       clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
+       for (i = 0; i < clusters_num; i++) {
+               offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL;
+               val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
+               val |= HPRE_CLUSTER_DYN_CTL_EN;
+               writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
+
+               val = readl(qm->io_base + offset + HPRE_CORE_SHB_CFG);
+               val |= HPRE_CORE_GATE_EN;
+               writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG);
+       }
 }
 
 static void hpre_disable_clock_gate(struct hisi_qm *qm)
 {
+       unsigned long offset;
+       u8 clusters_num, i;
        u32 val;
 
        if (qm->ver < QM_HW_V3)
@@ -630,13 +638,17 @@ static void hpre_disable_clock_gate(struct hisi_qm *qm)
        val &= ~HPRE_PEH_CFG_AUTO_GATE_EN;
        writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
 
-       val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
-       val &= ~HPRE_CLUSTER_DYN_CTL_EN;
-       writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
-
-       val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
-       val &= ~HPRE_CORE_GATE_EN;
-       writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
+       clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
+       for (i = 0; i < clusters_num; i++) {
+               offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL;
+               val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
+               val &= ~HPRE_CLUSTER_DYN_CTL_EN;
+               writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
+
+               val = readl(qm->io_base + offset + HPRE_CORE_SHB_CFG);
+               val &= ~HPRE_CORE_GATE_EN;
+               writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG);
+       }
 }
 
 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)