RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds integer arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	integer arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VADCVVM): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 90ea839457aaf160396f4ec7998ab1eaa7bd1d36..c5ad56e1e58085831218040f2442194860227658 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -982,3 +982,325 @@ Disassembly of section .text:
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+[      ]+[0-9a-f]+:[   ]+6ac22257[     ]+th.vmor.mm[   ]+v4,v12,v4
+[      ]+[0-9a-f]+:[   ]+62860257[     ]+th.vmseq.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+6285c257[     ]+th.vmseq.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+6287b257[     ]+th.vmseq.vi[  ]+v4,v8,15
+[      ]+[0-9a-f]+:[   ]+62883257[     ]+th.vmseq.vi[  ]+v4,v8,-16
+[      ]+[0-9a-f]+:[   ]+60860257[     ]+th.vmseq.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+6085c257[     ]+th.vmseq.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+6087b257[     ]+th.vmseq.vi[  ]+v4,v8,15,v0.t
+[      ]+[0-9a-f]+:[   ]+60883257[     ]+th.vmseq.vi[  ]+v4,v8,-16,v0.t
+[      ]+[0-9a-f]+:[   ]+66860257[     ]+th.vmsne.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+6685c257[     ]+th.vmsne.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+6687b257[     ]+th.vmsne.vi[  ]+v4,v8,15
+[      ]+[0-9a-f]+:[   ]+66883257[     ]+th.vmsne.vi[  ]+v4,v8,-16
+[      ]+[0-9a-f]+:[   ]+64860257[     ]+th.vmsne.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+6485c257[     ]+th.vmsne.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+6487b257[     ]+th.vmsne.vi[  ]+v4,v8,15,v0.t
+[      ]+[0-9a-f]+:[   ]+64883257[     ]+th.vmsne.vi[  ]+v4,v8,-16,v0.t
+[      ]+[0-9a-f]+:[   ]+6a860257[     ]+th.vmsltu.vv[         ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+6a85c257[     ]+th.vmsltu.vx[         ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+68860257[     ]+th.vmsltu.vv[         ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+6885c257[     ]+th.vmsltu.vx[         ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+6e860257[     ]+th.vmslt.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+6e85c257[     ]+th.vmslt.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+6c860257[     ]+th.vmslt.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+6c85c257[     ]+th.vmslt.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+72860257[     ]+th.vmsleu.vv[         ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+7285c257[     ]+th.vmsleu.vx[         ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+7287b257[     ]+th.vmsleu.vi[         ]+v4,v8,15
+[      ]+[0-9a-f]+:[   ]+72883257[     ]+th.vmsleu.vi[         ]+v4,v8,-16
+[      ]+[0-9a-f]+:[   ]+70860257[     ]+th.vmsleu.vv[         ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+7085c257[     ]+th.vmsleu.vx[         ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+7087b257[     ]+th.vmsleu.vi[         ]+v4,v8,15,v0.t
+[      ]+[0-9a-f]+:[   ]+70883257[     ]+th.vmsleu.vi[         ]+v4,v8,-16,v0.t
+[      ]+[0-9a-f]+:[   ]+76860257[     ]+th.vmsle.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+7685c257[     ]+th.vmsle.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+7687b257[     ]+th.vmsle.vi[  ]+v4,v8,15
+[      ]+[0-9a-f]+:[   ]+76883257[     ]+th.vmsle.vi[  ]+v4,v8,-16
+[      ]+[0-9a-f]+:[   ]+74860257[     ]+th.vmsle.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+7485c257[     ]+th.vmsle.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+7487b257[     ]+th.vmsle.vi[  ]+v4,v8,15,v0.t
+[      ]+[0-9a-f]+:[   ]+74883257[     ]+th.vmsle.vi[  ]+v4,v8,-16,v0.t
+[      ]+[0-9a-f]+:[   ]+7a85c257[     ]+th.vmsgtu.vx[         ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+7a87b257[     ]+th.vmsgtu.vi[         ]+v4,v8,15
+[      ]+[0-9a-f]+:[   ]+7a883257[     ]+th.vmsgtu.vi[         ]+v4,v8,-16
+[      ]+[0-9a-f]+:[   ]+7885c257[     ]+th.vmsgtu.vx[         ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+7887b257[     ]+th.vmsgtu.vi[         ]+v4,v8,15,v0.t
+[      ]+[0-9a-f]+:[   ]+78883257[     ]+th.vmsgtu.vi[         ]+v4,v8,-16,v0.t
+[      ]+[0-9a-f]+:[   ]+7e85c257[     ]+th.vmsgt.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+7e87b257[     ]+th.vmsgt.vi[  ]+v4,v8,15
+[      ]+[0-9a-f]+:[   ]+7e883257[     ]+th.vmsgt.vi[  ]+v4,v8,-16
+[      ]+[0-9a-f]+:[   ]+7c85c257[     ]+th.vmsgt.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+7c87b257[     ]+th.vmsgt.vi[  ]+v4,v8,15,v0.t
+[      ]+[0-9a-f]+:[   ]+7c883257[     ]+th.vmsgt.vi[  ]+v4,v8,-16,v0.t
+[      ]+[0-9a-f]+:[   ]+12860257[     ]+th.vminu.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+1285c257[     ]+th.vminu.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+10860257[     ]+th.vminu.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1085c257[     ]+th.vminu.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+16860257[     ]+th.vmin.vv[   ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+1685c257[     ]+th.vmin.vx[   ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+14860257[     ]+th.vmin.vv[   ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1485c257[     ]+th.vmin.vx[   ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+1a860257[     ]+th.vmaxu.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+1a85c257[     ]+th.vmaxu.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+18860257[     ]+th.vmaxu.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1885c257[     ]+th.vmaxu.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+1e860257[     ]+th.vmax.vv[   ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+1e85c257[     ]+th.vmax.vx[   ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+1c860257[     ]+th.vmax.vv[   ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+1c85c257[     ]+th.vmax.vx[   ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+96862257[     ]+th.vmul.vv[   ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+9685e257[     ]+th.vmul.vx[   ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+94862257[     ]+th.vmul.vv[   ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+9485e257[     ]+th.vmul.vx[   ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+9e862257[     ]+th.vmulh.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+9e85e257[     ]+th.vmulh.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+9c862257[     ]+th.vmulh.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+9c85e257[     ]+th.vmulh.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+92862257[     ]+th.vmulhu.vv[         ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+9285e257[     ]+th.vmulhu.vx[         ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+90862257[     ]+th.vmulhu.vv[         ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+9085e257[     ]+th.vmulhu.vx[         ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+9a862257[     ]+th.vmulhsu.vv[        ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+9a85e257[     ]+th.vmulhsu.vx[        ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+98862257[     ]+th.vmulhsu.vv[        ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+9885e257[     ]+th.vmulhsu.vx[        ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+ee862257[     ]+th.vwmul.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+ee85e257[     ]+th.vwmul.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+ec862257[     ]+th.vwmul.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+ec85e257[     ]+th.vwmul.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+e2862257[     ]+th.vwmulu.vv[         ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+e285e257[     ]+th.vwmulu.vx[         ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+e0862257[     ]+th.vwmulu.vv[         ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+e085e257[     ]+th.vwmulu.vx[         ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+ea862257[     ]+th.vwmulsu.vv[        ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+ea85e257[     ]+th.vwmulsu.vx[        ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+e8862257[     ]+th.vwmulsu.vv[        ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+e885e257[     ]+th.vwmulsu.vx[        ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+b6862257[     ]+th.vmacc.vv[  ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+b685e257[     ]+th.vmacc.vx[  ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+b4862257[     ]+th.vmacc.vv[  ]+v4,v12,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+b485e257[     ]+th.vmacc.vx[  ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+be862257[     ]+th.vnmsac.vv[         ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+be85e257[     ]+th.vnmsac.vx[         ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+bc862257[     ]+th.vnmsac.vv[         ]+v4,v12,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+bc85e257[     ]+th.vnmsac.vx[         ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+a6862257[     ]+th.vmadd.vv[  ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+a685e257[     ]+th.vmadd.vx[  ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+a4862257[     ]+th.vmadd.vv[  ]+v4,v12,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+a485e257[     ]+th.vmadd.vx[  ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+ae862257[     ]+th.vnmsub.vv[         ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+ae85e257[     ]+th.vnmsub.vx[         ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+ac862257[     ]+th.vnmsub.vv[         ]+v4,v12,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+ac85e257[     ]+th.vnmsub.vx[         ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+f2862257[     ]+th.vwmaccu.vv[        ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+f285e257[     ]+th.vwmaccu.vx[        ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+f0862257[     ]+th.vwmaccu.vv[        ]+v4,v12,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+f085e257[     ]+th.vwmaccu.vx[        ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+f6862257[     ]+th.vwmacc.vv[         ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+f685e257[     ]+th.vwmacc.vx[         ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+f4862257[     ]+th.vwmacc.vv[         ]+v4,v12,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+f485e257[     ]+th.vwmacc.vx[         ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+fa862257[     ]+th.vwmaccsu.vv[       ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+fa85e257[     ]+th.vwmaccsu.vx[       ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+f8862257[     ]+th.vwmaccsu.vv[       ]+v4,v12,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+f885e257[     ]+th.vwmaccsu.vx[       ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+fe85e257[     ]+th.vwmaccus.vx[       ]+v4,a1,v8
+[      ]+[0-9a-f]+:[   ]+fc85e257[     ]+th.vwmaccus.vx[       ]+v4,a1,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+82862257[     ]+th.vdivu.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+8285e257[     ]+th.vdivu.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+80862257[     ]+th.vdivu.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+8085e257[     ]+th.vdivu.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+86862257[     ]+th.vdiv.vv[   ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+8685e257[     ]+th.vdiv.vx[   ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+84862257[     ]+th.vdiv.vv[   ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+8485e257[     ]+th.vdiv.vx[   ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+8a862257[     ]+th.vremu.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+8a85e257[     ]+th.vremu.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+88862257[     ]+th.vremu.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+8885e257[     ]+th.vremu.vx[  ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+8e862257[     ]+th.vrem.vv[   ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+8e85e257[     ]+th.vrem.vx[   ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+8c862257[     ]+th.vrem.vv[   ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+8c85e257[     ]+th.vrem.vx[   ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+5c860257[     ]+th.vmerge.vvm[        ]+v4,v8,v12,v0
+[      ]+[0-9a-f]+:[   ]+5c85c257[     ]+th.vmerge.vxm[        ]+v4,v8,a1,v0
+[      ]+[0-9a-f]+:[   ]+5c87b257[     ]+th.vmerge.vim[        ]+v4,v8,15,v0
+[      ]+[0-9a-f]+:[   ]+5c883257[     ]+th.vmerge.vim[        ]+v4,v8,-16,v0
+[      ]+[0-9a-f]+:[   ]+5e060457[     ]+th.vmv.v.v[   ]+v8,v12
+[      ]+[0-9a-f]+:[   ]+5e05c457[     ]+th.vmv.v.x[   ]+v8,a1
+[      ]+[0-9a-f]+:[   ]+5e07b457[     ]+th.vmv.v.i[   ]+v8,15
+[      ]+[0-9a-f]+:[   ]+5e083457[     ]+th.vmv.v.i[   ]+v8,-16

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index d356c016c2fdebf12deda8a8aa47716f0cdf7151..9235de7069414aa70b8316219a6c3ff45c55d0ea 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1005,3 +1005,338 @@
        th.vlseg8eff.v v4, (a0)
        th.vlseg8eff.v v4, 0(a0)
        th.vlseg8eff.v v4, (a0), v0.t
+
+       th.vadd.vv v4, v8, v12
+       th.vadd.vx v4, v8, a1
+       th.vadd.vi v4, v8, 15
+       th.vadd.vi v4, v8, -16
+       th.vadd.vv v4, v8, v12, v0.t
+       th.vadd.vx v4, v8, a1, v0.t
+       th.vadd.vi v4, v8, 15, v0.t
+       th.vadd.vi v4, v8, -16, v0.t
+       th.vsub.vv v4, v8, v12
+       th.vsub.vx v4, v8, a1
+       th.vrsub.vx v4, v8, a1
+       th.vrsub.vi v4, v8, 15
+       th.vrsub.vi v4, v8, -16
+       th.vsub.vv v4, v8, v12, v0.t
+       th.vsub.vx v4, v8, a1, v0.t
+       th.vrsub.vx v4, v8, a1, v0.t
+       th.vrsub.vi v4, v8, 15, v0.t
+       th.vrsub.vi v4, v8, -16, v0.t
+
+       # Aliases
+       th.vwcvt.x.x.v v4, v8
+       th.vwcvtu.x.x.v v4, v8
+       th.vwcvt.x.x.v v4, v8, v0.t
+       th.vwcvtu.x.x.v v4, v8, v0.t
+
+       th.vwaddu.vv v4, v8, v12
+       th.vwaddu.vx v4, v8, a1
+       th.vwaddu.vv v4, v8, v12, v0.t
+       th.vwaddu.vx v4, v8, a1, v0.t
+       th.vwsubu.vv v4, v8, v12
+       th.vwsubu.vx v4, v8, a1
+       th.vwsubu.vv v4, v8, v12, v0.t
+       th.vwsubu.vx v4, v8, a1, v0.t
+       th.vwadd.vv v4, v8, v12
+       th.vwadd.vx v4, v8, a1
+       th.vwadd.vv v4, v8, v12, v0.t
+       th.vwadd.vx v4, v8, a1, v0.t
+       th.vwsub.vv v4, v8, v12
+       th.vwsub.vx v4, v8, a1
+       th.vwsub.vv v4, v8, v12, v0.t
+       th.vwsub.vx v4, v8, a1, v0.t
+       th.vwaddu.wv v4, v8, v12
+       th.vwaddu.wx v4, v8, a1
+       th.vwaddu.wv v4, v8, v12, v0.t
+       th.vwaddu.wx v4, v8, a1, v0.t
+       th.vwsubu.wv v4, v8, v12
+       th.vwsubu.wx v4, v8, a1
+       th.vwsubu.wv v4, v8, v12, v0.t
+       th.vwsubu.wx v4, v8, a1, v0.t
+       th.vwadd.wv v4, v8, v12
+       th.vwadd.wx v4, v8, a1
+       th.vwadd.wv v4, v8, v12, v0.t
+       th.vwadd.wx v4, v8, a1, v0.t
+       th.vwsub.wv v4, v8, v12
+       th.vwsub.wx v4, v8, a1
+       th.vwsub.wv v4, v8, v12, v0.t
+       th.vwsub.wx v4, v8, a1, v0.t
+
+       th.vadc.vvm v4, v8, v12, v0
+       th.vadc.vxm v4, v8, a1, v0
+       th.vadc.vim v4, v8, 15, v0
+       th.vadc.vim v4, v8, -16, v0
+       th.vmadc.vvm v4, v8, v12, v0
+       th.vmadc.vxm v4, v8, a1, v0
+       th.vmadc.vim v4, v8, 15, v0
+       th.vmadc.vim v4, v8, -16, v0
+       th.vsbc.vvm v4, v8, v12, v0
+       th.vsbc.vxm v4, v8, a1, v0
+       th.vmsbc.vvm v4, v8, v12, v0
+       th.vmsbc.vxm v4, v8, a1, v0
+
+       # Aliases
+       th.vnot.v v4, v8
+       th.vnot.v v4, v8, v0.t
+
+       th.vand.vv v4, v8, v12
+       th.vand.vx v4, v8, a1
+       th.vand.vi v4, v8, 15
+       th.vand.vi v4, v8, -16
+       th.vand.vv v4, v8, v12, v0.t
+       th.vand.vx v4, v8, a1, v0.t
+       th.vand.vi v4, v8, 15, v0.t
+       th.vand.vi v4, v8, -16, v0.t
+       th.vor.vv v4, v8, v12
+       th.vor.vx v4, v8, a1
+       th.vor.vi v4, v8, 15
+       th.vor.vi v4, v8, -16
+       th.vor.vv v4, v8, v12, v0.t
+       th.vor.vx v4, v8, a1, v0.t
+       th.vor.vi v4, v8, 15, v0.t
+       th.vor.vi v4, v8, -16, v0.t
+       th.vxor.vv v4, v8, v12
+       th.vxor.vx v4, v8, a1
+       th.vxor.vi v4, v8, 15
+       th.vxor.vi v4, v8, -16
+       th.vxor.vv v4, v8, v12, v0.t
+       th.vxor.vx v4, v8, a1, v0.t
+       th.vxor.vi v4, v8, 15, v0.t
+       th.vxor.vi v4, v8, -16, v0.t
+
+       th.vsll.vv v4, v8, v12
+       th.vsll.vx v4, v8, a1
+       th.vsll.vi v4, v8, 1
+       th.vsll.vi v4, v8, 31
+       th.vsll.vv v4, v8, v12, v0.t
+       th.vsll.vx v4, v8, a1, v0.t
+       th.vsll.vi v4, v8, 1, v0.t
+       th.vsll.vi v4, v8, 31, v0.t
+       th.vsrl.vv v4, v8, v12
+       th.vsrl.vx v4, v8, a1
+       th.vsrl.vi v4, v8, 1
+       th.vsrl.vi v4, v8, 31
+       th.vsrl.vv v4, v8, v12, v0.t
+       th.vsrl.vx v4, v8, a1, v0.t
+       th.vsrl.vi v4, v8, 1, v0.t
+       th.vsrl.vi v4, v8, 31, v0.t
+       th.vsra.vv v4, v8, v12
+       th.vsra.vx v4, v8, a1
+       th.vsra.vi v4, v8, 1
+       th.vsra.vi v4, v8, 31
+       th.vsra.vv v4, v8, v12, v0.t
+       th.vsra.vx v4, v8, a1, v0.t
+       th.vsra.vi v4, v8, 1, v0.t
+       th.vsra.vi v4, v8, 31, v0.t
+
+       th.vnsrl.vv v4, v8, v12
+       th.vnsrl.vx v4, v8, a1
+       th.vnsrl.vi v4, v8, 1
+       th.vnsrl.vi v4, v8, 31
+       th.vnsrl.vv v4, v8, v12, v0.t
+       th.vnsrl.vx v4, v8, a1, v0.t
+       th.vnsrl.vi v4, v8, 1, v0.t
+       th.vnsrl.vi v4, v8, 31, v0.t
+       th.vnsra.vv v4, v8, v12
+       th.vnsra.vx v4, v8, a1
+       th.vnsra.vi v4, v8, 1
+       th.vnsra.vi v4, v8, 31
+       th.vnsra.vv v4, v8, v12, v0.t
+       th.vnsra.vx v4, v8, a1, v0.t
+       th.vnsra.vi v4, v8, 1, v0.t
+       th.vnsra.vi v4, v8, 31, v0.t
+
+       # Aliases
+       th.vmsgt.vv v4, v8, v12
+       th.vmsgtu.vv v4, v8, v12
+       th.vmsge.vv v4, v8, v12
+       th.vmsgeu.vv v4, v8, v12
+       th.vmsgt.vv v4, v8, v12, v0.t
+       th.vmsgtu.vv v4, v8, v12, v0.t
+       th.vmsge.vv v4, v8, v12, v0.t
+       th.vmsgeu.vv v4, v8, v12, v0.t
+       th.vmslt.vi v4, v8, 16
+       th.vmslt.vi v4, v8, -15
+       th.vmsltu.vi v4, v8, 16
+       th.vmsltu.vi v4, v8, -15
+       th.vmsge.vi v4, v8, 16
+       th.vmsge.vi v4, v8, -15
+       th.vmsgeu.vi v4, v8, 16
+       th.vmsgeu.vi v4, v8, -15
+       th.vmslt.vi v4, v8, 16, v0.t
+       th.vmslt.vi v4, v8, -15, v0.t
+       th.vmsltu.vi v4, v8, 16, v0.t
+       th.vmsltu.vi v4, v8, -15, v0.t
+       th.vmsge.vi v4, v8, 16, v0.t
+       th.vmsge.vi v4, v8, -15, v0.t
+       th.vmsgeu.vi v4, v8, 16, v0.t
+       th.vmsgeu.vi v4, v8, -15, v0.t
+
+       # Macros
+       th.vmsge.vx v4, v8, a1
+       th.vmsgeu.vx v4, v8, a1
+       th.vmsge.vx v8, v12, a2, v0.t
+       th.vmsgeu.vx v8, v12, a2, v0.t
+       th.vmsge.vx v4, v8, a1, v0.t, v12
+       th.vmsgeu.vx v4, v8, a1, v0.t, v12
+
+       th.vmseq.vv v4, v8, v12
+       th.vmseq.vx v4, v8, a1
+       th.vmseq.vi v4, v8, 15
+       th.vmseq.vi v4, v8, -16
+       th.vmseq.vv v4, v8, v12, v0.t
+       th.vmseq.vx v4, v8, a1, v0.t
+       th.vmseq.vi v4, v8, 15, v0.t
+       th.vmseq.vi v4, v8, -16, v0.t
+       th.vmsne.vv v4, v8, v12
+       th.vmsne.vx v4, v8, a1
+       th.vmsne.vi v4, v8, 15
+       th.vmsne.vi v4, v8, -16
+       th.vmsne.vv v4, v8, v12, v0.t
+       th.vmsne.vx v4, v8, a1, v0.t
+       th.vmsne.vi v4, v8, 15, v0.t
+       th.vmsne.vi v4, v8, -16, v0.t
+       th.vmsltu.vv v4, v8, v12
+       th.vmsltu.vx v4, v8, a1
+       th.vmsltu.vv v4, v8, v12, v0.t
+       th.vmsltu.vx v4, v8, a1, v0.t
+       th.vmslt.vv v4, v8, v12
+       th.vmslt.vx v4, v8, a1
+       th.vmslt.vv v4, v8, v12, v0.t
+       th.vmslt.vx v4, v8, a1, v0.t
+       th.vmsleu.vv v4, v8, v12
+       th.vmsleu.vx v4, v8, a1
+       th.vmsleu.vi v4, v8, 15
+       th.vmsleu.vi v4, v8, -16
+       th.vmsleu.vv v4, v8, v12, v0.t
+       th.vmsleu.vx v4, v8, a1, v0.t
+       th.vmsleu.vi v4, v8, 15, v0.t
+       th.vmsleu.vi v4, v8, -16, v0.t
+       th.vmsle.vv v4, v8, v12
+       th.vmsle.vx v4, v8, a1
+       th.vmsle.vi v4, v8, 15
+       th.vmsle.vi v4, v8, -16
+       th.vmsle.vv v4, v8, v12, v0.t
+       th.vmsle.vx v4, v8, a1, v0.t
+       th.vmsle.vi v4, v8, 15, v0.t
+       th.vmsle.vi v4, v8, -16, v0.t
+       th.vmsgtu.vx v4, v8, a1
+       th.vmsgtu.vi v4, v8, 15
+       th.vmsgtu.vi v4, v8, -16
+       th.vmsgtu.vx v4, v8, a1, v0.t
+       th.vmsgtu.vi v4, v8, 15, v0.t
+       th.vmsgtu.vi v4, v8, -16, v0.t
+       th.vmsgt.vx v4, v8, a1
+       th.vmsgt.vi v4, v8, 15
+       th.vmsgt.vi v4, v8, -16
+       th.vmsgt.vx v4, v8, a1, v0.t
+       th.vmsgt.vi v4, v8, 15, v0.t
+       th.vmsgt.vi v4, v8, -16, v0.t
+
+       th.vminu.vv v4, v8, v12
+       th.vminu.vx v4, v8, a1
+       th.vminu.vv v4, v8, v12, v0.t
+       th.vminu.vx v4, v8, a1, v0.t
+       th.vmin.vv v4, v8, v12
+       th.vmin.vx v4, v8, a1
+       th.vmin.vv v4, v8, v12, v0.t
+       th.vmin.vx v4, v8, a1, v0.t
+       th.vmaxu.vv v4, v8, v12
+       th.vmaxu.vx v4, v8, a1
+       th.vmaxu.vv v4, v8, v12, v0.t
+       th.vmaxu.vx v4, v8, a1, v0.t
+       th.vmax.vv v4, v8, v12
+       th.vmax.vx v4, v8, a1
+       th.vmax.vv v4, v8, v12, v0.t
+       th.vmax.vx v4, v8, a1, v0.t
+
+       th.vmul.vv v4, v8, v12
+       th.vmul.vx v4, v8, a1
+       th.vmul.vv v4, v8, v12, v0.t
+       th.vmul.vx v4, v8, a1, v0.t
+       th.vmulh.vv v4, v8, v12
+       th.vmulh.vx v4, v8, a1
+       th.vmulh.vv v4, v8, v12, v0.t
+       th.vmulh.vx v4, v8, a1, v0.t
+       th.vmulhu.vv v4, v8, v12
+       th.vmulhu.vx v4, v8, a1
+       th.vmulhu.vv v4, v8, v12, v0.t
+       th.vmulhu.vx v4, v8, a1, v0.t
+       th.vmulhsu.vv v4, v8, v12
+       th.vmulhsu.vx v4, v8, a1
+       th.vmulhsu.vv v4, v8, v12, v0.t
+       th.vmulhsu.vx v4, v8, a1, v0.t
+
+       th.vwmul.vv v4, v8, v12
+       th.vwmul.vx v4, v8, a1
+       th.vwmul.vv v4, v8, v12, v0.t
+       th.vwmul.vx v4, v8, a1, v0.t
+       th.vwmulu.vv v4, v8, v12
+       th.vwmulu.vx v4, v8, a1
+       th.vwmulu.vv v4, v8, v12, v0.t
+       th.vwmulu.vx v4, v8, a1, v0.t
+       th.vwmulsu.vv v4, v8, v12
+       th.vwmulsu.vx v4, v8, a1
+       th.vwmulsu.vv v4, v8, v12, v0.t
+       th.vwmulsu.vx v4, v8, a1, v0.t
+
+       th.vmacc.vv v4, v12, v8
+       th.vmacc.vx v4, a1, v8
+       th.vmacc.vv v4, v12, v8, v0.t
+       th.vmacc.vx v4, a1, v8, v0.t
+       th.vnmsac.vv v4, v12, v8
+       th.vnmsac.vx v4, a1, v8
+       th.vnmsac.vv v4, v12, v8, v0.t
+       th.vnmsac.vx v4, a1, v8, v0.t
+       th.vmadd.vv v4, v12, v8
+       th.vmadd.vx v4, a1, v8
+       th.vmadd.vv v4, v12, v8, v0.t
+       th.vmadd.vx v4, a1, v8, v0.t
+       th.vnmsub.vv v4, v12, v8
+       th.vnmsub.vx v4, a1, v8
+       th.vnmsub.vv v4, v12, v8, v0.t
+       th.vnmsub.vx v4, a1, v8, v0.t
+
+       th.vwmaccu.vv v4, v12, v8
+       th.vwmaccu.vx v4, a1, v8
+       th.vwmaccu.vv v4, v12, v8, v0.t
+       th.vwmaccu.vx v4, a1, v8, v0.t
+       th.vwmacc.vv v4, v12, v8
+       th.vwmacc.vx v4, a1, v8
+       th.vwmacc.vv v4, v12, v8, v0.t
+       th.vwmacc.vx v4, a1, v8, v0.t
+       th.vwmaccsu.vv v4, v12, v8
+       th.vwmaccsu.vx v4, a1, v8
+       th.vwmaccsu.vv v4, v12, v8, v0.t
+       th.vwmaccsu.vx v4, a1, v8, v0.t
+       th.vwmaccus.vx v4, a1, v8
+       th.vwmaccus.vx v4, a1, v8, v0.t
+
+       th.vdivu.vv v4, v8, v12
+       th.vdivu.vx v4, v8, a1
+       th.vdivu.vv v4, v8, v12, v0.t
+       th.vdivu.vx v4, v8, a1, v0.t
+       th.vdiv.vv v4, v8, v12
+       th.vdiv.vx v4, v8, a1
+       th.vdiv.vv v4, v8, v12, v0.t
+       th.vdiv.vx v4, v8, a1, v0.t
+       th.vremu.vv v4, v8, v12
+       th.vremu.vx v4, v8, a1
+       th.vremu.vv v4, v8, v12, v0.t
+       th.vremu.vx v4, v8, a1, v0.t
+       th.vrem.vv v4, v8, v12
+       th.vrem.vx v4, v8, a1
+       th.vrem.vv v4, v8, v12, v0.t
+       th.vrem.vx v4, v8, a1, v0.t
+
+       th.vmerge.vvm v4, v8, v12, v0
+       th.vmerge.vxm v4, v8, a1, v0
+       th.vmerge.vim v4, v8, 15, v0
+       th.vmerge.vim v4, v8, -16, v0
+
+       th.vmv.v.v v8, v12
+       th.vmv.v.x v8, a1
+       th.vmv.v.i v8, 15
+       th.vmv.v.i v8, -16

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 58618a46b4d8b332ef40bc80a606e44dab550c2d..df4b7abcedb1f9f52041e458821ce6f5fa05d9fe 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2885,6 +2885,18 @@
 #define MASK_TH_VAMOMAXUWV 0xf800707f
 #define MATCH_TH_VAMOMAXUDV 0xe000702f
 #define MASK_TH_VAMOMAXUDV 0xf800707f
+#define MATCH_TH_VADCVVM 0x42000057
+#define MASK_TH_VADCVVM 0xfe00707f
+#define MATCH_TH_VADCVXM 0x42004057
+#define MASK_TH_VADCVXM 0xfe00707f
+#define MATCH_TH_VADCVIM 0x42003057
+#define MASK_TH_VADCVIM 0xfe00707f
+#define MATCH_TH_VSBCVVM 0x4a000057
+#define MASK_TH_VSBCVVM 0xfe00707f
+#define MATCH_TH_VSBCVXM 0x4a004057
+#define MASK_TH_VSBCVXM 0xfe00707f
+#define MATCH_TH_VWMACCSUVV 0xf8002057
+#define MASK_TH_VWMACCSUVV 0xfc00707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 51b9956ad96b974fbef8f3193caecfd7a7e21ee7..b0061ebb3f775eb6dce1404702a2b7703f6bc0f5 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2579,6 +2579,149 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vamominud.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF},
 {"th.vamomaxuw.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF},
 {"th.vamomaxud.v",  0, INSN_CLASS_XTHEADZVAMO,  "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF},
+{"th.vadd.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
+{"th.vadd.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
+{"th.vadd.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
+{"th.vsub.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
+{"th.vsub.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
+{"th.vrsub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
+{"th.vrsub.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
+{"th.vwcvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_opcode, INSN_ALIAS },
+{"th.vwcvtu.x.x.v",0,INSN_CLASS_XTHEADVECTOR,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_opcode, INSN_ALIAS },
+{"th.vwaddu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_opcode, 0 },
+{"th.vwaddu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_opcode, 0 },
+{"th.vwsubu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_opcode, 0 },
+{"th.vwsubu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_opcode, 0 },
+{"th.vwadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_opcode, 0 },
+{"th.vwadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_opcode, 0 },
+{"th.vwsub.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_opcode, 0 },
+{"th.vwsub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_opcode, 0 },
+{"th.vwaddu.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_opcode, 0 },
+{"th.vwaddu.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_opcode, 0 },
+{"th.vwsubu.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_opcode, 0 },
+{"th.vwsubu.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_opcode, 0 },
+{"th.vwadd.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_opcode, 0 },
+{"th.vwadd.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_opcode, 0 },
+{"th.vwsub.wv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_opcode, 0 },
+{"th.vwsub.wx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_opcode, 0 },
+{"th.vadc.vvm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_TH_VADCVVM, MASK_TH_VADCVVM, match_opcode, 0 },
+{"th.vadc.vxm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_TH_VADCVXM, MASK_TH_VADCVXM, match_opcode, 0 },
+{"th.vadc.vim",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vi,V0", MATCH_TH_VADCVIM, MASK_TH_VADCVIM, match_opcode, 0 },
+{"th.vmadc.vvm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
+{"th.vmadc.vxm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
+{"th.vmadc.vim",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vi,V0", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
+{"th.vsbc.vvm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_TH_VSBCVVM, MASK_TH_VSBCVVM, match_opcode, 0 },
+{"th.vsbc.vxm",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_TH_VSBCVXM, MASK_TH_VSBCVXM, match_opcode, 0 },
+{"th.vmsbc.vvm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
+{"th.vmsbc.vxm",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
+{"th.vnot.v",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
+{"th.vand.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
+{"th.vand.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
+{"th.vand.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
+{"th.vor.vv",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
+{"th.vor.vx",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
+{"th.vor.vi",     0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
+{"th.vxor.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
+{"th.vxor.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
+{"th.vxor.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
+{"th.vsll.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
+{"th.vsll.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
+{"th.vsll.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
+{"th.vsrl.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
+{"th.vsrl.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
+{"th.vsrl.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
+{"th.vsra.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
+{"th.vsra.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
+{"th.vsra.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
+{"th.vnsrl.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_opcode, 0 },
+{"th.vnsrl.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_opcode, 0 },
+{"th.vnsrl.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_opcode, 0 },
+{"th.vnsra.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_opcode, 0 },
+{"th.vnsra.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_opcode, 0 },
+{"th.vnsra.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_opcode, 0 },
+{"th.vmseq.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
+{"th.vmseq.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
+{"th.vmseq.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
+{"th.vmsne.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
+{"th.vmsne.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
+{"th.vmsne.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
+{"th.vmsltu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
+{"th.vmsltu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
+{"th.vmslt.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
+{"th.vmslt.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
+{"th.vmsleu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
+{"th.vmsleu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
+{"th.vmsleu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
+{"th.vmsle.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
+{"th.vmsle.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
+{"th.vmsle.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
+{"th.vmsgtu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
+{"th.vmsgtu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
+{"th.vmsgt.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
+{"th.vmsgt.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
+{"th.vmsgt.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
+{"th.vmsgtu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
+{"th.vmsge.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
+{"th.vmsgeu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
+{"th.vmslt.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
+{"th.vmsltu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
+{"th.vmsge.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
+{"th.vmsgeu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
+{"th.vmsge.vx",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsge.vx",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsgeu.vx",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsgeu.vx",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vminu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
+{"th.vminu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
+{"th.vmin.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
+{"th.vmin.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
+{"th.vmaxu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
+{"th.vmaxu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
+{"th.vmax.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
+{"th.vmax.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
+{"th.vmul.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
+{"th.vmul.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
+{"th.vmulh.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
+{"th.vmulh.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
+{"th.vmulhu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
+{"th.vmulhu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
+{"th.vmulhsu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
+{"th.vmulhsu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
+{"th.vwmul.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_opcode, 0 },
+{"th.vwmul.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_opcode, 0 },
+{"th.vwmulu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_opcode, 0 },
+{"th.vwmulu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_opcode, 0 },
+{"th.vwmulsu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_opcode, 0 },
+{"th.vwmulsu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_opcode, 0 },
+{"th.vmacc.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
+{"th.vmacc.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
+{"th.vnmsac.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
+{"th.vnmsac.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
+{"th.vmadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
+{"th.vmadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
+{"th.vnmsub.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
+{"th.vnmsub.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
+{"th.vwmaccu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_opcode, 0},
+{"th.vwmaccu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_opcode, 0},
+{"th.vwmacc.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_opcode, 0},
+{"th.vwmacc.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_opcode, 0},
+{"th.vwmaccsu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_TH_VWMACCSUVV, MASK_TH_VWMACCSUVV, match_opcode, 0},
+{"th.vwmaccsu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_opcode, 0},
+{"th.vwmaccus.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_opcode, 0},
+{"th.vdivu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
+{"th.vdivu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
+{"th.vdiv.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
+{"th.vdiv.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
+{"th.vremu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
+{"th.vremu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
+{"th.vrem.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
+{"th.vrem.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
+{"th.vmerge.vvm", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
+{"th.vmerge.vxm", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
+{"th.vmerge.vim", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
+{"th.vmv.v.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
+{"th.vmv.v.x",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
+{"th.vmv.v.i",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },