\f
/* Utilities on value constraint. */
-static inline int
-value_in_range_p (int64_t value, int low, int high)
+static inline bool
+value_in_range_p (int64_t value, int64_t low, int64_t high)
{
- return (value >= low && value <= high) ? 1 : 0;
+ return (low <= value) && (value <= high);
}
/* Return true if VALUE is a multiple of ALIGN. */
-static inline int
+static inline bool
value_aligned_p (int64_t value, int align)
{
return (value % align) == 0;
}
/* A signed value fits in a field. */
-static inline int
+static inline bool
value_fit_signed_field_p (int64_t value, unsigned width)
{
assert (width < 32);
{
int64_t lim = (uint64_t) 1 << (width - 1);
if (value >= -lim && value < lim)
- return 1;
+ return true;
}
- return 0;
+ return false;
}
/* An unsigned value fits in a field. */
-static inline int
+static inline bool
value_fit_unsigned_field_p (int64_t value, unsigned width)
{
assert (width < 32);
{
int64_t lim = (uint64_t) 1 << width;
if (value >= 0 && value < lim)
- return 1;
+ return true;
}
- return 0;
+ return false;
}
-/* Return 1 if OPERAND is SP or WSP. */
-int
+/* Return true if OPERAND is SP or WSP. */
+bool
aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
{
return ((aarch64_get_operand_class (operand->type)
OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
qualified by the qualifier TARGET. */
-static inline int
+static inline bool
operand_also_qualified_p (const struct aarch64_opnd_info *operand,
aarch64_opnd_qualifier_t target)
{
{
case AARCH64_OPND_QLF_W:
if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
- return 1;
+ return true;
break;
case AARCH64_OPND_QLF_X:
if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
- return 1;
+ return true;
break;
case AARCH64_OPND_QLF_WSP:
if (target == AARCH64_OPND_QLF_W
&& operand_maybe_stack_pointer (aarch64_operands + operand->type))
- return 1;
+ return true;
break;
case AARCH64_OPND_QLF_SP:
if (target == AARCH64_OPND_QLF_X
&& operand_maybe_stack_pointer (aarch64_operands + operand->type))
- return 1;
+ return true;
break;
default:
break;
}
- return 0;
+ return false;
}
/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
use a combination of error code, static string and some integer data to
represent an error. */
-static int
+static bool
operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
enum aarch64_opnd type,
const aarch64_opcode *opcode,
set_syntax_error (mismatch_detail, idx - 1,
_("second reg in pair should be xzr if first is"
" xzr"));
- return 0;
+ return false;
}
}
/* Check pair reg constraints for instructions taking a pair of
{
set_syntax_error (mismatch_detail, idx - 1,
_("reg pair must start from even reg"));
- return 0;
+ return false;
}
if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
{
set_syntax_error (mismatch_detail, idx,
_("reg pair must be contiguous"));
- return 0;
+ return false;
}
break;
}
&& !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
{
set_other_error (mismatch_detail, idx, _("extraneous register"));
- return 0;
+ return false;
}
if (!opnds[1].present
&& aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
{
set_other_error (mismatch_detail, idx, _("missing register"));
- return 0;
+ return false;
}
}
switch (qualifier)
{
set_other_error (mismatch_detail, idx,
_("stack pointer register expected"));
- return 0;
+ return false;
}
break;
default:
if (!check_reglane (opnd, mismatch_detail, idx,
"z", 0, (1 << shift) - 1,
0, (1u << (size - shift)) - 1))
- return 0;
+ return false;
break;
case AARCH64_OPND_SVE_Zm1_23_INDEX:
size = aarch64_get_qualifier_esize (opnd->qualifier);
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
0, 64 / size - 1))
- return 0;
+ return false;
break;
case AARCH64_OPND_SVE_Zn_5_INDEX:
size = aarch64_get_qualifier_esize (opnd->qualifier);
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
0, 16 / size - 1))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_PNn3_INDEX1:
size = get_operand_field_width (get_operand_from_code (type), 1);
if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15,
0, (1 << size) - 1))
- return 0;
+ return false;
break;
case AARCH64_OPND_SVE_Zm3_12_INDEX:
size = get_operand_fields_width (get_operand_from_code (type)) - 5;
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
0, (1 << size) - 1))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_Zm_INDEX1:
size = get_operand_fields_width (get_operand_from_code (type)) - 4;
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15,
0, (1 << size) - 1))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_Zm:
if (opnd->reg.regno > 15)
{
set_invalid_regno_error (mismatch_detail, idx, "z", 0, 15);
- return 0;
+ return false;
}
break;
max_value = 16 / size - 1;
if (!check_za_access (opnd, mismatch_detail, idx,
12, max_value, 1, 0, get_opcode_dependent_value (opcode)))
- return 0;
+ return false;
break;
default:
case AARCH64_OPND_SME_Znx4:
num = get_operand_specific_data (&aarch64_operands[type]);
if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
- return 0;
+ return false;
if ((opnd->reglist.first_regno % num) != 0)
{
set_other_error (mismatch_detail, idx,
_("start register out of range"));
- return 0;
+ return false;
}
break;
have a stride of 4. */
num = get_operand_specific_data (&aarch64_operands[type]);
if (!check_reglist (opnd, mismatch_detail, idx, num, 16 / num))
- return 0;
+ return false;
num = 16 | (opnd->reglist.stride - 1);
if ((opnd->reglist.first_regno & ~num) != 0)
{
set_other_error (mismatch_detail, idx,
_("start register out of range"));
- return 0;
+ return false;
}
break;
case AARCH64_OPND_SVE_ZtxN:
num = get_opcode_dependent_value (opcode);
if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
- return 0;
+ return false;
break;
default:
if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_off4:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_off3_0:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_off1x4:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 1, 4,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_off2x2:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_off2x4:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 4,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_off3x2:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_vrsb_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 7, 2,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_vrsh_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 2,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_vrss_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 2,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_vrsd_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 2,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_vrsb_2:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 4,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_vrsh_2:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 4,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_ARRAY4:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_array_vrss_2:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4,
get_opcode_dependent_value (opcode),
get_opcode_dependent_vg_status (opcode)))
- return 0;
+ return false;
break;
case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
max_value -= 1;
if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, num,
0, get_opcode_dependent_value (opcode)))
- return 0;
+ return false;
break;
default:
if (opnd->reg.regno < 8)
{
set_invalid_regno_error (mismatch_detail, idx, "pn", 8, 15);
- return 0;
+ return false;
}
break;
&& get_operand_fields_width (get_operand_from_code (type)) == 3)
{
set_invalid_regno_error (mismatch_detail, idx, "p", 0, 7);
- return 0;
+ return false;
}
break;
}
{
set_syntax_error (mismatch_detail, idx,
_("unexpected address writeback"));
- return 0;
+ return false;
}
break;
case ldst_imm10:
{
set_syntax_error (mismatch_detail, idx,
_("unexpected address writeback"));
- return 0;
+ return false;
}
break;
case ldst_imm9:
{
set_syntax_error (mismatch_detail, idx,
_("address writeback expected"));
- return 0;
+ return false;
}
break;
case rcpc3:
{
set_syntax_error (mismatch_detail, idx,
_("unexpected address writeback"));
- return 0;
+ return false;
}
break;
{
set_offset_out_of_range_error (mismatch_detail, idx,
-64 * size, 63 * size);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->addr.offset.imm, size))
{
set_unaligned_error (mismatch_detail, idx, size);
- return 0;
+ return false;
}
break;
case AARCH64_OPND_ADDR_OFFSET:
if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
{
set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
- return 0;
+ return false;
}
break;
if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
&& !value_aligned_p (opnd->addr.offset.imm, size))
|| value_in_range_p (opnd->addr.offset.imm, -256, -1))
- return 1;
+ return true;
set_other_error (mismatch_detail, idx,
_("negative or unaligned offset expected"));
- return 0;
+ return false;
case AARCH64_OPND_ADDR_SIMM10:
/* Scaled signed 10 bits immediate offset. */
if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
{
set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->addr.offset.imm, 8))
{
set_unaligned_error (mismatch_detail, idx, 8);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
{
set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->addr.offset.imm, 16))
{
set_unaligned_error (mismatch_detail, idx, 16);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
{
set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->addr.offset.imm, 16))
{
set_unaligned_error (mismatch_detail, idx, 16);
- return 0;
+ return false;
}
break;
if (opnd->addr.offset.is_reg)
{
if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
- return 1;
+ return true;
else
{
set_other_error (mismatch_detail, idx,
_("invalid register offset"));
- return 0;
+ return false;
}
}
else
{
set_other_error (mismatch_detail, idx,
_("invalid post-increment amount"));
- return 0;
+ return false;
}
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid shift amount"));
- return 0;
+ return false;
}
/* Only UXTW, LSL, SXTW and SXTX are the accepted extending
operators. */
default:
set_other_error (mismatch_detail, idx,
_("invalid extend/shift operator"));
- return 0;
+ return false;
}
break;
{
set_offset_out_of_range_error (mismatch_detail, idx,
0, 4095 * size);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->addr.offset.imm, size))
{
set_unaligned_error (mismatch_detail, idx, size);
- return 0;
+ return false;
}
break;
if (!value_aligned_p (imm, 4))
{
set_unaligned_error (mismatch_detail, idx, 4);
- return 0;
+ return false;
}
/* Right shift by 2 so that we can carry out the following check
canonically. */
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->addr.offset.imm, 0, 15))
{
set_offset_out_of_range_error (mismatch_detail, idx, 0, 15);
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid addressing mode"));
- return 0;
+ return false;
}
if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
{
set_offset_out_of_range_error (mismatch_detail, idx,
min_value, max_value);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->addr.offset.imm, num))
{
set_unaligned_error (mismatch_detail, idx, num);
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid addressing mode"));
- return 0;
+ return false;
}
if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
{
set_offset_out_of_range_error (mismatch_detail, idx,
min_value, max_value);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->addr.offset.imm, num))
{
set_unaligned_error (mismatch_detail, idx, num);
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("index register xzr is not allowed"));
- return 0;
+ return false;
}
if (((1 << opnd->shifter.kind) & modifiers) == 0
|| (opnd->shifter.amount
{
set_other_error (mismatch_detail, idx,
_("invalid addressing mode"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid addressing mode"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid increment amount"));
- return 0;
+ return false;
}
}
break;
if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
{
set_imm_out_of_range_error (mismatch_detail, idx, -256, 255);
- return 0;
+ return false;
}
default:
if (!value_in_range_p (opnd->reglist.index, 0, num))
{
set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
- return 0;
+ return false;
}
}
/* The opcode dependent area stores the number of elements in
/* Unless LD1/ST1, the number of registers should be equal to that
of the structure elements. */
if (num != 1 && !check_reglist (opnd, mismatch_detail, idx, num, 1))
- return 0;
+ return false;
break;
case AARCH64_OPND_LVt_AL:
case AARCH64_OPND_LEt:
/* The number of registers should be equal to that of the structure
elements. */
if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
- return 0;
+ return false;
break;
default:
break;
if (opnd->reglist.stride != 1)
{
set_reg_list_stride_error (mismatch_detail, idx, 1);
- return 0;
+ return false;
}
break;
set_imm_out_of_range_error (mismatch_detail, idx,
get_lower_bound (qualifier),
get_upper_bound (qualifier));
- return 0;
+ return false;
}
switch (type)
{
set_other_error (mismatch_detail, idx,
_("invalid shift operator"));
- return 0;
+ return false;
}
if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
{
set_other_error (mismatch_detail, idx,
_("shift amount must be 0 or 12"));
- return 0;
+ return false;
}
if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid shift operator"));
- return 0;
+ return false;
}
size = aarch64_get_qualifier_esize (opnds[0].qualifier);
if (!value_aligned_p (opnd->shifter.amount, 16))
{
set_other_error (mismatch_detail, idx,
_("shift amount must be a multiple of 16"));
- return 0;
+ return false;
}
if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
{
set_sft_amount_out_of_range_error (mismatch_detail, idx,
0, size * 8 - 16);
- return 0;
+ return false;
}
if (opnd->imm.value < 0)
{
set_other_error (mismatch_detail, idx,
_("negative immediate value not allowed"));
- return 0;
+ return false;
}
if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
break;
case OP_MOV_IMM_LOG:
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
break;
default:
assert (0);
- return 0;
+ return false;
}
}
break;
{
set_imm_out_of_range_error (mismatch_detail, idx, 0,
(1u << size) - 1);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->imm.value, 0, 1008))
{
set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->imm.value, 16))
{
set_unaligned_error (mismatch_detail, idx, 16);
- return 0;
+ return false;
}
break;
set_imm_out_of_range_error (mismatch_detail, idx,
-(1 << (size - 1)),
(1 << (size - 1)) - 1);
- return 0;
+ return false;
}
break;
{
set_imm_out_of_range_error (mismatch_detail, idx, 1,
size - opnds[idx-1].imm.value);
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
}
break;
{
set_other_error (mismatch_detail, idx,
_("immediate zero expected"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("rotate expected to be 0, 90, 180 or 270"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("rotate expected to be 90 or 270"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid shift amount"));
- return 0;
+ return false;
}
break;
{
set_imm_out_of_range_error (mismatch_detail, idx, 0,
size * 8 - 1);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->imm.value, 1, size * 8))
{
set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("invalid shift operator"));
- return 0;
+ return false;
}
break;
case AARCH64_OPND_QLF_MSL:
{
set_other_error (mismatch_detail, idx,
_("invalid shift operator"));
- return 0;
+ return false;
}
break;
case AARCH64_OPND_QLF_NIL:
{
set_other_error (mismatch_detail, idx,
_("shift is not permitted"));
- return 0;
+ return false;
}
break;
default:
assert (0);
- return 0;
+ return false;
}
/* Is the immediate valid? */
assert (idx == 1);
if (!value_in_range_p (opnd->imm.value, -128, 255))
{
set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
- return 0;
+ return false;
}
}
else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
ffffffffgggggggghhhhhhhh'. */
set_other_error (mismatch_detail, idx,
_("invalid value for immediate"));
- return 0;
+ return false;
}
/* Is the shift amount valid? */
switch (opnd->shifter.kind)
{
set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
(size - 1) * 8);
- return 0;
+ return false;
}
if (!value_aligned_p (opnd->shifter.amount, 8))
{
set_unaligned_error (mismatch_detail, idx, 8);
- return 0;
+ return false;
}
break;
case AARCH64_MOD_MSL:
{
set_other_error (mismatch_detail, idx,
_("shift amount must be 0 or 16"));
- return 0;
+ return false;
}
break;
default:
{
set_other_error (mismatch_detail, idx,
_("invalid shift operator"));
- return 0;
+ return false;
}
break;
}
{
set_other_error (mismatch_detail, idx,
_("floating-point immediate expected"));
- return 0;
+ return false;
}
/* The value is expected to be an 8-bit floating-point constant with
sign, 3-bit exponent and normalized 4 bits of precision, encoded
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
if (opnd->shifter.kind != AARCH64_MOD_NONE)
{
set_other_error (mismatch_detail, idx,
_("invalid shift operator"));
- return 0;
+ return false;
}
break;
set_other_error (mismatch_detail, idx,
_("no shift amount allowed for"
" 8-bit constants"));
- return 0;
+ return false;
}
}
else
{
set_other_error (mismatch_detail, idx,
_("shift amount must be 0 or 8"));
- return 0;
+ return false;
}
if (shift == 0 && (uvalue & 0xff) == 0)
{
{
set_other_error (mismatch_detail, idx,
_("immediate too big for element size"));
- return 0;
+ return false;
}
uvalue = (uvalue - min_value) & mask;
if (uvalue > 0xff)
{
set_other_error (mismatch_detail, idx,
_("invalid arithmetic immediate"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("floating-point value must be 0.5 or 1.0"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("floating-point value must be 0.5 or 2.0"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("floating-point value must be 0.0 or 1.0"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
}
break;
{
set_other_error (mismatch_detail, idx,
_("immediate out of range"));
- return 0;
+ return false;
}
if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
{
set_other_error (mismatch_detail, idx,
_("invalid replicated MOV immediate"));
- return 0;
+ return false;
}
}
break;
if (!value_in_range_p (opnd->shifter.amount, 1, 16))
{
set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
- return 0;
+ return false;
}
break;
{
set_imm_out_of_range_error (mismatch_detail, idx,
0, 8 * size - 1);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->imm.value, 1, size))
{
set_imm_out_of_range_error (mismatch_detail, idx, 1, size);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
{
set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->imm.value, 0, 56))
{
set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, 56);
- return 0;
+ return false;
}
if (opnd->imm.value % 8 != 0)
{
set_other_error (mismatch_detail, idx,
_("byte index must be a multiple of 8"));
- return 0;
+ return false;
}
break;
if (opnds[1].imm.value < 0 || opnds[1].imm.value > max_value)
{
set_imm_out_of_range_error (mismatch_detail, 1, 0, max_value);
- return 0;
+ return false;
}
break;
case AARCH64_OPND_PRFOP:
set_other_error (mismatch_detail, idx,
_("the register-index form of PRFM does"
" not accept opcodes in the range 24-31"));
- return 0;
+ return false;
}
break;
default:
if (!value_in_range_p (opnd->reglane.index, 0, num))
{
set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
- return 0;
+ return false;
}
/* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
<Vm> Is the vector register (V0-V31) or (V0-V15), whose
&& !value_in_range_p (opnd->reglane.regno, 0, 15))
{
set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
- return 0;
+ return false;
}
if (type == AARCH64_OPND_Em8
&& !value_in_range_p (opnd->reglane.regno, 0, 7))
{
set_other_error (mismatch_detail, idx,
_("extend operator expected"));
- return 0;
+ return false;
}
/* It is not optional unless at least one of "Rd" or "Rn" is '11111'
(i.e. SP), in which case it defaults to LSL. The LSL alias is
{
set_other_error (mismatch_detail, idx,
_("missing extend operator"));
- return 0;
+ return false;
}
else if (opnd->shifter.kind == AARCH64_MOD_LSL)
{
set_other_error (mismatch_detail, idx,
_("'LSL' operator not allowed"));
- return 0;
+ return false;
}
}
assert (opnd->shifter.operator_present /* Default to LSL. */
if (!value_in_range_p (opnd->shifter.amount, 0, 4))
{
set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
- return 0;
+ return false;
}
/* In the 64-bit form, the final register operand is written as Wm
for all but the (possibly omitted) UXTX/LSL and SXTX
&& opnd->shifter.kind != AARCH64_MOD_SXTX)
{
set_other_error (mismatch_detail, idx, _("W register expected"));
- return 0;
+ return false;
}
break;
{
set_other_error (mismatch_detail, idx,
_("shift operator expected"));
- return 0;
+ return false;
}
if (opnd->shifter.kind == AARCH64_MOD_ROR
&& opcode->iclass != log_shift)
{
set_other_error (mismatch_detail, idx,
_("'ROR' operator not allowed"));
- return 0;
+ return false;
}
num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
if (!value_in_range_p (opnd->shifter.amount, 0, num))
{
set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
- return 0;
+ return false;
}
break;
if (!value_in_range_p (opnd->shifter.amount, 0, 7))
{
set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 7);
- return 0;
+ return false;
}
break;
break;
}
- return 1;
+ return true;
}
/* Main entrypoint for the operand constraint checking.
Un-determined operand qualifiers may get established during the process. */
-int
+bool
aarch64_match_operands_constraint (aarch64_inst *inst,
aarch64_operand_error *mismatch_detail)
{
mismatch_detail->kind = AARCH64_OPDE_UNTIED_IMMS;
mismatch_detail->index = i;
}
- return 0;
+ return false;
}
break;
mismatch_detail->index = i;
mismatch_detail->error = NULL;
}
- return 0;
+ return false;
}
break;
}
mismatch_detail->error = NULL;
mismatch_detail->data[0].i = invalid_count;
}
- return 0;
+ return false;
}
/* Match operands' constraint. */
DEBUG_TRACE ("skip the incomplete operand %d", i);
continue;
}
- if (operand_general_constraint_met_p (inst->operands, i, type,
- inst->opcode, mismatch_detail) == 0)
+ if (!operand_general_constraint_met_p (inst->operands, i, type,
+ inst->opcode, mismatch_detail))
{
DEBUG_TRACE ("FAIL on operand %d", i);
- return 0;
+ return false;
}
}
DEBUG_TRACE ("PASS");
- return 1;
+ return true;
}
/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
projects / thirdparty / binutils-gdb.git / commitdiff
