net: sparx5: do some preparation work

The sparx5_port_init() does initial configuration of a variety of
different features and options for each port. Some are shared for all
types of devices, some are not. As it is now, common configuration is
done after configuration of low-speed devices. This will not work when
adding RGMII support in a subsequent patch.

In preparation for lan969x RGMII support, move a block of code, that
configures 2g5 devices, down. This ensures that the configuration common
to all devices is done before configuration of 2g5, 5g, 10g and 25g
devices.

Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Tested-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-1-fa8ba5dff732@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c
index f9d1a6bb9bfffd6074d4d217b9671f68260092a2..f39bf4878e11cc18efcbe29417fda9c8b4a158da 100644 (file)
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c
@@ -1067,24 +1067,6 @@ int sparx5_port_init(struct sparx5 *sparx5,
        if (err)
                return err;
 
-       /* Configure MAC vlan awareness */
-       err = sparx5_port_max_tags_set(sparx5, port);
-       if (err)
-               return err;
-
-       /* Set Max Length */
-       spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN),
-                DEV2G5_MAC_MAXLEN_CFG_MAX_LEN,
-                sparx5,
-                DEV2G5_MAC_MAXLEN_CFG(port->portno));
-
-       /* 1G/2G5: Signal Detect configuration */
-       spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) |
-               DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) |
-               DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena),
-               sparx5,
-               DEV2G5_PCS1G_SD_CFG(port->portno));
-
        /* Set Pause WM hysteresis */
        spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) |
                 QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop) |
@@ -1108,6 +1090,24 @@ int sparx5_port_init(struct sparx5 *sparx5,
                 ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS,
                 sparx5, ANA_CL_FILTER_CTRL(port->portno));
 
+       /* Configure MAC vlan awareness */
+       err = sparx5_port_max_tags_set(sparx5, port);
+       if (err)
+               return err;
+
+       /* Set Max Length */
+       spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN),
+                DEV2G5_MAC_MAXLEN_CFG_MAX_LEN,
+                sparx5,
+                DEV2G5_MAC_MAXLEN_CFG(port->portno));
+
+       /* 1G/2G5: Signal Detect configuration */
+       spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) |
+               DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) |
+               DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena),
+               sparx5,
+               DEV2G5_PCS1G_SD_CFG(port->portno));
+
        if (conf->portmode == PHY_INTERFACE_MODE_QSGMII ||
            conf->portmode == PHY_INTERFACE_MODE_SGMII) {
                err = sparx5_serdes_set(sparx5, port, conf);