drm/msm: Add CONTEXT_SWITCH_CNTL bitfields

Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml.

Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/618016/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index 97608603ea62d473069d204d7f775b7af4447935..2db425abf0f3cc4c1ab9ec233bbb695b70bdd62b 100644 (file)
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -2358,7 +2358,12 @@ to upconvert to 32b float internally?
                <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
        </array>
 
-       <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
+       <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL">
+               <bitfield name="STOP" pos="0" type="boolean"/>
+               <bitfield name="LEVEL" low="6" high="7"/>
+               <bitfield name="USES_GMEM" pos="8" type="boolean"/>
+               <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/>
+       </reg32>
        <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
        <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
        <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>