--- /dev/null
+From d6a8b72edc92471283925ceb4ba12799b67c3ff8 Mon Sep 17 00:00:00 2001
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Date: Wed, 5 Nov 2014 16:56:36 -0800
+Subject: drm/i915: Disable caches for Global GTT.
+
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+
+commit d6a8b72edc92471283925ceb4ba12799b67c3ff8 upstream.
+
+Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
+So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
+
+MOCS can still be used though. But if userspace is trusting PTE for
+cache selection the safest thing to do is to let caches disabled.
+
+BSpec: "For GGTT, there is NO pat_sel[2:0] from the entry,
+so RTL will always use the value corresponding to pat_sel = 000"
+
+- System agent ggtt writes (i.e. cpu gtt mmaps) already work before
+this patch, i.e. the same uncached + snooping access like on gen6/7
+seems to be in effect.
+- So this just fixes blitter/render access. Again it looks like it's
+not just uncached access, but uncached + snooping. So we can still
+hold onto all our assumptions wrt cpu clflushing on LLC machines.
+
+v2: Cleaner patch as suggested by Chris.
+v3: Add Daniel's comment
+
+Reference: https://bugs.freedesktop.org/show_bug.cgi?id=85576
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: James Ausmus <james.ausmus@intel.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Tested-by: James Ausmus <james.ausmus@intel.com>
+Reviewed-by: James Ausmus <james.ausmus@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
++++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
+@@ -1901,6 +1901,22 @@ static void bdw_setup_private_ppat(struc
+ GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
+ GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+
++ if (!USES_PPGTT(dev_priv->dev))
++ /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
++ * so RTL will always use the value corresponding to
++ * pat_sel = 000".
++ * So let's disable cache for GGTT to avoid screen corruptions.
++ * MOCS still can be used though.
++ * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
++ * before this patch, i.e. the same uncached + snooping access
++ * like on gen6/7 seems to be in effect.
++ * - So this just fixes blitter/render access. Again it looks
++ * like it's not just uncached access, but uncached + snooping.
++ * So we can still hold onto all our assumptions wrt cpu
++ * clflushing on LLC machines.
++ */
++ pat = GEN8_PPAT(0, GEN8_PPAT_UC);
++
+ /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
+ * write would work. */
+ I915_WRITE(GEN8_PRIVATE_PAT, pat);
--- /dev/null
+From 7809a61176b385ebb3299ea43c58b1bb31ffb8c0 Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Wed, 29 Oct 2014 11:03:26 +0200
+Subject: drm/i915/dp: only use training pattern 3 on platforms that support it
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit 7809a61176b385ebb3299ea43c58b1bb31ffb8c0 upstream.
+
+Ivybridge + 30" monitor prints a drm error on every modeset, since IVB
+doesn't support DP3 we should even bother trying to use it.
+
+This regression has been introduced in
+
+commit 06ea66b6bb445043dc25a9626254d5c130093199
+Author: Todd Previte <tprevite@gmail.com>
+Date: Mon Jan 20 10:19:39 2014 -0700
+
+ drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable
+devices
+
+Reported-by: Dave Airlie <airlied@redhat.com>
+Reference: http://mid.gmane.org/1414566170-9868-1-git-send-email-airlied@gmail.com
+Cc: Todd Previte <tprevite@gmail.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_dp.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -3354,9 +3354,10 @@ intel_dp_get_dpcd(struct intel_dp *intel
+ }
+ }
+
+- /* Training Pattern 3 support */
++ /* Training Pattern 3 support, both source and sink */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
+- intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
++ intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
++ (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)) {
+ intel_dp->use_tps3 = true;
+ DRM_DEBUG_KMS("Displayport TPS3 supported");
+ } else
--- /dev/null
+From e1c412e75754ab7b7002f3e18a2652d999c40d4b Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Wed, 5 Nov 2014 14:46:31 +0200
+Subject: drm/i915: safeguard against too high minimum brightness
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit e1c412e75754ab7b7002f3e18a2652d999c40d4b upstream.
+
+Never trust (your interpretation of) the VBT. Regression from
+
+commit 6dda730e55f412a6dfb181cae6784822ba463847
+Author: Jani Nikula <jani.nikula@intel.com>
+Date: Tue Jun 24 18:27:40 2014 +0300
+
+ drm/i915: respect the VBT minimum backlight brightness
+
+causing div by zero if VBT minimum brightness equals maximum brightness.
+
+Despite my attempts I've failed in my detective work to figure out what
+the root cause is. This is not the real fix, but we have to do
+something.
+
+Reported-by: Mike Auty <mike.auty@gmail.com>
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=86551
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_panel.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_panel.c
++++ b/drivers/gpu/drm/i915/intel_panel.c
+@@ -1074,12 +1074,25 @@ static u32 get_backlight_min_vbt(struct
+ struct drm_device *dev = connector->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_panel *panel = &connector->panel;
++ int min;
+
+ WARN_ON(panel->backlight.max == 0);
+
++ /*
++ * XXX: If the vbt value is 255, it makes min equal to max, which leads
++ * to problems. There are such machines out there. Either our
++ * interpretation is wrong or the vbt has bogus data. Or both. Safeguard
++ * against this by letting the minimum be at most (arbitrarily chosen)
++ * 25% of the max.
++ */
++ min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
++ if (min != dev_priv->vbt.backlight.min_brightness) {
++ DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",
++ dev_priv->vbt.backlight.min_brightness, min);
++ }
++
+ /* vbt value is a coefficient in range [0..255] */
+- return scale(dev_priv->vbt.backlight.min_brightness, 0, 255,
+- 0, panel->backlight.max);
++ return scale(min, 0, 255, 0, panel->backlight.max);
+ }
+
+ static int bdw_setup_backlight(struct intel_connector *connector)
--- /dev/null
+From 1c9498425453bb65ef339a57705c5ef59fe1541d Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied@redhat.com>
+Date: Tue, 11 Nov 2014 09:16:15 +1000
+Subject: drm/radeon: add locking around atombios scratch space usage
+
+From: Dave Airlie <airlied@redhat.com>
+
+commit 1c9498425453bb65ef339a57705c5ef59fe1541d upstream.
+
+While developing MST support I noticed I often got the wrong data
+back from a transaction, in a racy fashion. I noticed the scratch
+space wasn't locked against concurrent users.
+
+Based on a patch by Alex, but I've made it a bit more obvious when
+things are locked.
+
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atom.c | 11 ++++++++++-
+ drivers/gpu/drm/radeon/atom.h | 2 ++
+ drivers/gpu/drm/radeon/atombios_dp.c | 4 +++-
+ drivers/gpu/drm/radeon/atombios_i2c.c | 4 +++-
+ drivers/gpu/drm/radeon/radeon_device.c | 1 +
+ 5 files changed, 19 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atom.c
++++ b/drivers/gpu/drm/radeon/atom.c
+@@ -1217,7 +1217,7 @@ free:
+ return ret;
+ }
+
+-int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
++int atom_execute_table_scratch_unlocked(struct atom_context *ctx, int index, uint32_t * params)
+ {
+ int r;
+
+@@ -1238,6 +1238,15 @@ int atom_execute_table(struct atom_conte
+ return r;
+ }
+
++int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
++{
++ int r;
++ mutex_lock(&ctx->scratch_mutex);
++ r = atom_execute_table_scratch_unlocked(ctx, index, params);
++ mutex_unlock(&ctx->scratch_mutex);
++ return r;
++}
++
+ static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
+
+ static void atom_index_iio(struct atom_context *ctx, int base)
+--- a/drivers/gpu/drm/radeon/atom.h
++++ b/drivers/gpu/drm/radeon/atom.h
+@@ -125,6 +125,7 @@ struct card_info {
+ struct atom_context {
+ struct card_info *card;
+ struct mutex mutex;
++ struct mutex scratch_mutex;
+ void *bios;
+ uint32_t cmd_table, data_table;
+ uint16_t *iio;
+@@ -145,6 +146,7 @@ extern int atom_debug;
+
+ struct atom_context *atom_parse(struct card_info *, void *);
+ int atom_execute_table(struct atom_context *, int, uint32_t *);
++int atom_execute_table_scratch_unlocked(struct atom_context *, int, uint32_t *);
+ int atom_asic_init(struct atom_context *);
+ void atom_destroy(struct atom_context *);
+ bool atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
+--- a/drivers/gpu/drm/radeon/atombios_dp.c
++++ b/drivers/gpu/drm/radeon/atombios_dp.c
+@@ -100,6 +100,7 @@ static int radeon_process_aux_ch(struct
+ memset(&args, 0, sizeof(args));
+
+ mutex_lock(&chan->mutex);
++ mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
+
+ base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
+
+@@ -113,7 +114,7 @@ static int radeon_process_aux_ch(struct
+ if (ASIC_IS_DCE4(rdev))
+ args.v2.ucHPD_ID = chan->rec.hpd;
+
+- atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
++ atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+ *ack = args.v1.ucReplyStatus;
+
+@@ -147,6 +148,7 @@ static int radeon_process_aux_ch(struct
+
+ r = recv_bytes;
+ done:
++ mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
+ mutex_unlock(&chan->mutex);
+
+ return r;
+--- a/drivers/gpu/drm/radeon/atombios_i2c.c
++++ b/drivers/gpu/drm/radeon/atombios_i2c.c
+@@ -48,6 +48,7 @@ static int radeon_process_i2c_ch(struct
+ memset(&args, 0, sizeof(args));
+
+ mutex_lock(&chan->mutex);
++ mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
+
+ base = (unsigned char *)rdev->mode_info.atom_context->scratch;
+
+@@ -82,7 +83,7 @@ static int radeon_process_i2c_ch(struct
+ args.ucSlaveAddr = slave_addr << 1;
+ args.ucLineNumber = chan->rec.i2c_id;
+
+- atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
++ atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+ /* error */
+ if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
+@@ -95,6 +96,7 @@ static int radeon_process_i2c_ch(struct
+ radeon_atom_copy_swap(buf, base, num, false);
+
+ done:
++ mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
+ mutex_unlock(&chan->mutex);
+
+ return r;
+--- a/drivers/gpu/drm/radeon/radeon_device.c
++++ b/drivers/gpu/drm/radeon/radeon_device.c
+@@ -952,6 +952,7 @@ int radeon_atombios_init(struct radeon_d
+ }
+
+ mutex_init(&rdev->mode_info.atom_context->mutex);
++ mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
+ radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
+ atom_allocate_fb_scratch(rdev->mode_info.atom_context);
+ return 0;
--- /dev/null
+From f0d7bfb9407fccb6499ec01c33afe43512a439a2 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 5 Nov 2014 17:14:32 -0500
+Subject: drm/radeon: add missing crtc unlock when setting up the MC
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit f0d7bfb9407fccb6499ec01c33afe43512a439a2 upstream.
+
+Need to unlock the crtc after updating the blanking state.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -2556,6 +2556,7 @@ void evergreen_mc_stop(struct radeon_dev
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ }
+ } else {
+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
--- /dev/null
+From 8efe82ca908400785253c8f0dfcf301e6bd93488 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 3 Nov 2014 09:57:46 -0500
+Subject: drm/radeon: make sure mode init is complete in bandwidth_update
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 8efe82ca908400785253c8f0dfcf301e6bd93488 upstream.
+
+The power management code calls into the display code for
+certain things. If certain power management sysfs attributes
+are called before the driver has finished initializing all of
+the hardware we can run into problems with uninitialized
+modesetting state. Add a check to make sure modesetting
+init has completed to the bandwidth update callbacks to
+fix this. Can be triggered by the tlp and laptop start
+up scripts depending on the timing.
+
+bugs:
+https://bugzilla.kernel.org/show_bug.cgi?id=83611
+https://bugs.freedesktop.org/show_bug.cgi?id=85771
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cik.c | 3 +++
+ drivers/gpu/drm/radeon/evergreen.c | 3 +++
+ drivers/gpu/drm/radeon/r100.c | 3 +++
+ drivers/gpu/drm/radeon/rs600.c | 3 +++
+ drivers/gpu/drm/radeon/rs690.c | 3 +++
+ drivers/gpu/drm/radeon/rv515.c | 3 +++
+ drivers/gpu/drm/radeon/si.c | 3 +++
+ 7 files changed, 21 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -9447,6 +9447,9 @@ void dce8_bandwidth_update(struct radeon
+ u32 num_heads = 0, lb_size;
+ int i;
+
++ if (!rdev->mode_info.mode_config_initialized)
++ return;
++
+ radeon_update_display_priority(rdev);
+
+ for (i = 0; i < rdev->num_crtc; i++) {
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -2346,6 +2346,9 @@ void evergreen_bandwidth_update(struct r
+ u32 num_heads = 0, lb_size;
+ int i;
+
++ if (!rdev->mode_info.mode_config_initialized)
++ return;
++
+ radeon_update_display_priority(rdev);
+
+ for (i = 0; i < rdev->num_crtc; i++) {
+--- a/drivers/gpu/drm/radeon/r100.c
++++ b/drivers/gpu/drm/radeon/r100.c
+@@ -3204,6 +3204,9 @@ void r100_bandwidth_update(struct radeon
+ uint32_t pixel_bytes1 = 0;
+ uint32_t pixel_bytes2 = 0;
+
++ if (!rdev->mode_info.mode_config_initialized)
++ return;
++
+ radeon_update_display_priority(rdev);
+
+ if (rdev->mode_info.crtcs[0]->base.enabled) {
+--- a/drivers/gpu/drm/radeon/rs600.c
++++ b/drivers/gpu/drm/radeon/rs600.c
+@@ -879,6 +879,9 @@ void rs600_bandwidth_update(struct radeo
+ u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
+ /* FIXME: implement full support */
+
++ if (!rdev->mode_info.mode_config_initialized)
++ return;
++
+ radeon_update_display_priority(rdev);
+
+ if (rdev->mode_info.crtcs[0]->base.enabled)
+--- a/drivers/gpu/drm/radeon/rs690.c
++++ b/drivers/gpu/drm/radeon/rs690.c
+@@ -579,6 +579,9 @@ void rs690_bandwidth_update(struct radeo
+ u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
+ u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
+
++ if (!rdev->mode_info.mode_config_initialized)
++ return;
++
+ radeon_update_display_priority(rdev);
+
+ if (rdev->mode_info.crtcs[0]->base.enabled)
+--- a/drivers/gpu/drm/radeon/rv515.c
++++ b/drivers/gpu/drm/radeon/rv515.c
+@@ -1277,6 +1277,9 @@ void rv515_bandwidth_update(struct radeo
+ struct drm_display_mode *mode0 = NULL;
+ struct drm_display_mode *mode1 = NULL;
+
++ if (!rdev->mode_info.mode_config_initialized)
++ return;
++
+ radeon_update_display_priority(rdev);
+
+ if (rdev->mode_info.crtcs[0]->base.enabled)
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -2384,6 +2384,9 @@ void dce6_bandwidth_update(struct radeon
+ u32 num_heads = 0, lb_size;
+ int i;
+
++ if (!rdev->mode_info.mode_config_initialized)
++ return;
++
+ radeon_update_display_priority(rdev);
+
+ for (i = 0; i < rdev->num_crtc; i++) {
--- /dev/null
+From dc4edad6530a9b7b66c3d905e2bc06021a05dcad Mon Sep 17 00:00:00 2001
+From: Jammy Zhou <Jammy.Zhou@amd.com>
+Date: Mon, 3 Nov 2014 08:58:20 -0500
+Subject: drm/radeon: set correct CE ram size for CIK
+
+From: Jammy Zhou <Jammy.Zhou@amd.com>
+
+commit dc4edad6530a9b7b66c3d905e2bc06021a05dcad upstream.
+
+CE ram size is 32k/0k/0k for GFX/CS0/CS1 with CIK
+
+Ported from amdgpu driver.
+
+Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cik.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -4315,8 +4315,8 @@ static int cik_cp_gfx_start(struct radeo
+ /* init the CE partitions. CE only used for gfx on CIK */
+ radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
+ radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
+- radeon_ring_write(ring, 0xc000);
+- radeon_ring_write(ring, 0xc000);
++ radeon_ring_write(ring, 0x8000);
++ radeon_ring_write(ring, 0x8000);
+
+ /* setup clear context state */
+ radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
--- /dev/null
+From 0b021c5802fbe5addf6f89f5030f684adf04f7b7 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 3 Nov 2014 11:27:17 -0500
+Subject: drm/radeon: use gart for DMA IB tests
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 0b021c5802fbe5addf6f89f5030f684adf04f7b7 upstream.
+
+Use gart rather than vram to avoid having to deal with
+the HDP cache.
+
+Port of adfed2b0587289013f8143c54913ddfd44ac1fd3
+(drm/radeon: use gart memory for DMA ring tests)
+to the IB tests.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cik_sdma.c | 21 ++++++++++++---------
+ drivers/gpu/drm/radeon/r600_dma.c | 20 ++++++++++----------
+ 2 files changed, 22 insertions(+), 19 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/cik_sdma.c
++++ b/drivers/gpu/drm/radeon/cik_sdma.c
+@@ -666,17 +666,20 @@ int cik_sdma_ib_test(struct radeon_devic
+ {
+ struct radeon_ib ib;
+ unsigned i;
++ unsigned index;
+ int r;
+- void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
+ u32 tmp = 0;
++ u64 gpu_addr;
+
+- if (!ptr) {
+- DRM_ERROR("invalid vram scratch pointer\n");
+- return -EINVAL;
+- }
++ if (ring->idx == R600_RING_TYPE_DMA_INDEX)
++ index = R600_WB_DMA_RING_TEST_OFFSET;
++ else
++ index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
++
++ gpu_addr = rdev->wb.gpu_addr + index;
+
+ tmp = 0xCAFEDEAD;
+- writel(tmp, ptr);
++ rdev->wb.wb[index/4] = cpu_to_le32(tmp);
+
+ r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
+ if (r) {
+@@ -685,8 +688,8 @@ int cik_sdma_ib_test(struct radeon_devic
+ }
+
+ ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
+- ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
+- ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);
++ ib.ptr[1] = lower_32_bits(gpu_addr);
++ ib.ptr[2] = upper_32_bits(gpu_addr);
+ ib.ptr[3] = 1;
+ ib.ptr[4] = 0xDEADBEEF;
+ ib.length_dw = 5;
+@@ -703,7 +706,7 @@ int cik_sdma_ib_test(struct radeon_devic
+ return r;
+ }
+ for (i = 0; i < rdev->usec_timeout; i++) {
+- tmp = readl(ptr);
++ tmp = le32_to_cpu(rdev->wb.wb[index/4]);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+--- a/drivers/gpu/drm/radeon/r600_dma.c
++++ b/drivers/gpu/drm/radeon/r600_dma.c
+@@ -338,17 +338,17 @@ int r600_dma_ib_test(struct radeon_devic
+ {
+ struct radeon_ib ib;
+ unsigned i;
++ unsigned index;
+ int r;
+- void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
+ u32 tmp = 0;
++ u64 gpu_addr;
+
+- if (!ptr) {
+- DRM_ERROR("invalid vram scratch pointer\n");
+- return -EINVAL;
+- }
++ if (ring->idx == R600_RING_TYPE_DMA_INDEX)
++ index = R600_WB_DMA_RING_TEST_OFFSET;
++ else
++ index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
+
+- tmp = 0xCAFEDEAD;
+- writel(tmp, ptr);
++ gpu_addr = rdev->wb.gpu_addr + index;
+
+ r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
+ if (r) {
+@@ -357,8 +357,8 @@ int r600_dma_ib_test(struct radeon_devic
+ }
+
+ ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
+- ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
+- ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
++ ib.ptr[1] = lower_32_bits(gpu_addr);
++ ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
+ ib.ptr[3] = 0xDEADBEEF;
+ ib.length_dw = 4;
+
+@@ -374,7 +374,7 @@ int r600_dma_ib_test(struct radeon_devic
+ return r;
+ }
+ for (i = 0; i < rdev->usec_timeout; i++) {
+- tmp = readl(ptr);
++ tmp = le32_to_cpu(rdev->wb.wb[index/4]);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
mac80211-use-secondary-channel-offset-ie-also-beacons-during-csa.patch
mac80211-schedule-the-actual-switch-of-the-station-before-csa-count-0.patch
mac80211-fix-use-after-free-in-defragmentation.patch
+drm-i915-safeguard-against-too-high-minimum-brightness.patch
+drm-i915-disable-caches-for-global-gtt.patch
+drm-i915-dp-only-use-training-pattern-3-on-platforms-that-support-it.patch
+drm-radeon-set-correct-ce-ram-size-for-cik.patch
+drm-radeon-make-sure-mode-init-is-complete-in-bandwidth_update.patch
+drm-radeon-use-gart-for-dma-ib-tests.patch
+drm-radeon-add-missing-crtc-unlock-when-setting-up-the-mc.patch
+drm-radeon-add-locking-around-atombios-scratch-space-usage.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
