+2002-05-24 Zack Weinberg <zack@codesourcery.com>
+
+ * config.gcc: Remove all stanzas for previously obsoleted
+ systems. Where necessary, add explicit error stanzas to
+ prevent removed systems from being misidentified as something
+ else. Begin a fresh obsoletions list, with the systems that
+ were reprieved last round.
+ * doc/install.texi: Remove all mention of dead targets.
+ * fixinc/mkfixinc.sh: Likewise.
+
+ * config/arm/arm.h: Bit 31 of target_flags is no longer
+ reserved.
+
+ * config/1750a/1750a-protos.h, config/1750a/1750a.c,
+ config/1750a/1750a.h, config/1750a/1750a.md, config/1750a/ms1750.inc,
+ config/a29k/a29k-protos.h, config/a29k/a29k.c, config/a29k/a29k.h,
+ config/a29k/a29k.md, config/a29k/rtems.h, config/a29k/t-a29kbare,
+ config/a29k/t-vx29k, config/a29k/unix.h, config/a29k/vx29k.h,
+ config/alpha/osf12.h, config/alpha/osf2or3.h,
+ config/arm/arm-wince-pe.h, config/arm/arm.h, config/arm/riscix.h,
+ config/arm/riscix1-1.h, config/arm/rix-gas.h, config/arm/t-riscix,
+ config/clipper/clipper-protos.h, config/clipper/clipper.c,
+ config/clipper/clipper.h, config/clipper/clipper.md,
+ config/clipper/clix.h, config/convex/convex-protos.h,
+ config/convex/convex.c, config/convex/convex.h,
+ config/convex/convex.md, config/convex/fixinc.convex,
+ config/convex/proto.h, config/elxsi/elxsi-protos.h,
+ config/elxsi/elxsi.c, config/elxsi/elxsi.h, config/elxsi/elxsi.md,
+ config/i386/386bsd.h, config/i386/aix386.h, config/i386/aix386ng.h,
+ config/i386/bsd386.h, config/i386/dgux.h, config/i386/djgpp-rtems.h,
+ config/i386/isc.h, config/i386/iscdbx.h, config/i386/linux-oldld.h,
+ config/i386/next.h, config/i386/osf1-ci.asm, config/i386/osf1-cn.asm,
+ config/i386/osf1elf.h, config/i386/osf1elfgdb.h, config/i386/osfelf.h,
+ config/i386/osfrose.h, config/i386/rtems.h, config/i386/seq-gas.h,
+ config/i386/seq-sysv3.h, config/i386/seq2-sysv3.h,
+ config/i386/sequent.h, config/i386/sun.h, config/i386/sun386.h,
+ config/i386/t-dgux, config/i386/t-next, config/i386/t-osf,
+ config/i386/t-osf1elf, config/i860/bsd-gas.h, config/i860/bsd.h,
+ config/i860/fx2800.h, config/i860/i860-protos.h, config/i860/i860.c,
+ config/i860/i860.h, config/i860/i860.md, config/i860/mach.h,
+ config/i860/paragon.h, config/i860/sysv3.h, config/i860/sysv4.h,
+ config/i860/t-fx2800, config/i860/varargs.asm, config/m68k/a-ux.h,
+ config/m68k/altos3068.h, config/m68k/apollo68.h,
+ config/m68k/aux-crt1.c, config/m68k/aux-crt2.asm,
+ config/m68k/aux-crtn.asm, config/m68k/aux-exit.c,
+ config/m68k/aux-low.gld, config/m68k/aux-mcount.c,
+ config/m68k/auxas.h, config/m68k/auxgas.h, config/m68k/auxgld.h,
+ config/m68k/auxld.h, config/m68k/ctix.h, config/m68k/dpx2.h,
+ config/m68k/dpx2.ifile, config/m68k/dpx2cdbx.h, config/m68k/dpx2g.h,
+ config/m68k/isi-nfp.h, config/m68k/isi.h, config/m68k/lynx-ng.h,
+ config/m68k/lynx.h, config/m68k/math-3300.h, config/m68k/news.h,
+ config/m68k/news3.h, config/m68k/news3gas.h, config/m68k/newsgas.h,
+ config/m68k/next.h, config/m68k/next21.h, config/m68k/rtems.h,
+ config/m68k/t-aux, config/m68k/t-lynx, config/m68k/t-next,
+ config/m68k/x-next, config/m88k/dgux.h, config/m88k/dgux.ld,
+ config/m88k/dguxbcs.h, config/m88k/dolph.h, config/m88k/dolphin.ld,
+ config/m88k/luna.h, config/m88k/m88k-coff.h, config/m88k/sysv3.h,
+ config/m88k/t-bug, config/m88k/t-dgux, config/m88k/t-dgux-gas,
+ config/m88k/t-dguxbcs, config/m88k/t-dolph, config/m88k/t-m88k-gas,
+ config/m88k/t-tekXD88, config/m88k/tekXD88.h, config/m88k/tekXD88.ld,
+ config/mips/bsd-4.h, config/mips/bsd-5.h, config/mips/dec-bsd.h,
+ config/mips/dec-osf1.h, config/mips/elflorion.h,
+ config/mips/iris4loser.h, config/mips/mips-5.h, config/mips/news4.h,
+ config/mips/news5.h, config/mips/nws3250v4.h, config/mips/osfrose.h,
+ config/mips/svr3-4.h, config/mips/svr3-5.h, config/mips/svr4-4.h,
+ config/mips/svr4-5.h, config/mips/svr4-t.h, config/mips/t-bsd,
+ config/mips/t-bsd-gas, config/mips/t-svr3, config/mips/t-svr3-gas,
+ config/mips/t-svr4, config/mips/t-svr4-gas, config/mips/t-ultrix,
+ config/mips/ultrix.h, config/nextstep-protos.h, config/nextstep.c,
+ config/nextstep.h, config/nextstep21.h, config/ns32k/encore.h,
+ config/ns32k/merlin.h, config/ns32k/pc532-mach.h,
+ config/ns32k/pc532-min.h, config/ns32k/pc532.h,
+ config/ns32k/sequent.h, config/ns32k/tek6000.h,
+ config/ns32k/tek6100.h, config/ns32k/tek6200.h, config/pj/lib1funcs.S,
+ config/pj/linux.h, config/pj/pj-protos.h, config/pj/pj.c,
+ config/pj/pj.h, config/pj/pj.md, config/pj/pjl.h, config/pj/t-pj,
+ config/sparc/rtems.h, config/we32k/we32k-protos.h,
+ config/we32k/we32k.c, config/we32k/we32k.h, config/we32k/we32k.md:
+ Delete file.
+
2002-05-24 Richard Henderson <rth@redhat.com>
* flags.h (TLS_MODEL_GLOBAL_DYNAMIC): Set to 1.
2002-05-24 Richard Henderson <rth@redhat.com>
- * varasm.c (asm_output_bss): Always output one byte.
- * config/alpha/elf.h (ASM_OUTPUT_ALIGNED_LOCAL): Likewise.
+ * varasm.c (asm_output_bss): Always output one byte.
+ * config/alpha/elf.h (ASM_OUTPUT_ALIGNED_LOCAL): Likewise.
2002-05-24 Bryce McKinlay <bryce@waitaki.otago.ac.nz>
* config/i386/mingw32.h (CPP_SPEC): Remove -remap.
2002-05-23 Gabriel Dos Reis <gdr@codesourcery.com>
- Zack Weinberg <zack@codesourcery.com>
+ Zack Weinberg <zack@codesourcery.com>
* config/i386/mingw32.h (OUTPUT_QUOTED_STRING): Properly output
quoted strings.
dynamic linker.
(STARTFILE_PREFIX_SPEC): Define.
(STARTFILE_LINUX_SPEC, ENDFILE_LINUX_SPEC): Rewrite without
- absolute paths.
+ absolute paths.
2002-05-22 Kazu Hirata <kazu@cs.umass.edu>
enable_threads=$enable_threads_flag
# Obsolete configurations.
-# To avoid some tedious lists, we have a blacklist with a whitelist
-# embedded within it.
case $machine in
- 1750a-* \
- | a29k-* \
- | alpha*-*-osf[123]* \
- | arm-*-riscix* \
- | c*-convex-* \
- | clipper-* \
- | elxsi-* \
- | i860-* \
- | i?86-*-aix* \
- | i?86-*-bsd* \
- | i?86-*-chorusos* \
- | i?86-*-dgux* \
- | i?86-*-freebsd1.* \
- | i?86-*-isc* \
- | i?86-*-linux*oldld* \
- | i?86-*-osf1* \
- | i?86-*-osfrose* \
- | i?86-*-rtemscoff* \
- | i?86-*-sunos* \
- | i?86-go32-rtems* \
- | i?86-next-* \
- | i?86-sequent-bsd* \
- | i?86-sequent-ptx[12]* \
- | i?86-sequent-sysv3* \
- | m68[k0]*-*-lynxos* \
- | m68[k0]*-*-rtemscoff* \
- | m68[k0]*-*-sysv3* \
- | m68[k0]*-altos-* \
- | m68[k0]*-apollo-* \
- | m68[k0]*-apple-* \
- | m68[k0]*-bull-* \
- | m68[k0]*-convergent-* \
- | m68[k0]*-isi-* \
- | m68[k0]*-next-* \
- | m68[k0]*-sony-* \
- | m88k-* \
- | mips-*-bsd* \
- | mips-*-riscos* \
- | mips-*-sysv* \
- | mips-*-ultrix* \
- | mips-dec-* \
- | mips-sgi-irix[1234]* \
- | mips-sony-* \
- | mips-tandem-* \
- | ns32k-* \
- | pj-* \
- | pjl-* \
- | romp-* \
- | sparc-*-rtemsaout* \
- | we32k-* \
-)
- case $machine in
- mips-sni-sysv4 \
- | m88k-*-aout* | m88k-*-openbsd* | m88k-*-sysv4* \
- | ns32k-*-netbsd* | ns32k-*-openbsd* \
- | romp-*-openbsd* \
- )
- # Whitelisted.
- ;;
- *)
+ m88k-*-aout* \
+ | m88k-*-openbsd* \
+ | m88k-*-sysv4* \
+ | mips-sni-sysv4 \
+ | ns32k-*-netbsd* \
+ | ns32k-*-openbsd* \
+ | romp-*-openbsd* \
+ )
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration $machine is obsolete." >&2
echo "*** Specify --enable-obsolete to build it anyway." >&2
echo "*** unless a maintainer comes forward." >&2
exit 1
fi;;
- esac
esac
# Set default cpu_type, tm_file, tm_p_file and xm_file so it can be
xscale-*-*)
cpu_type=arm
;;
-c*-convex-*)
- cpu_type=convex
- extra_headers=proto.h
- ;;
i[34567]86-*-*)
cpu_type=i386
extra_headers="mmintrin.h xmmintrin.h"
mips*-*-*)
cpu_type=mips
;;
-pj*-*-*)
- cpu_type=pj
- ;;
powerpc*-*-*)
cpu_type=rs6000
extra_headers="ppc-asm.h altivec.h"
then tmake_file=${cpu_type}/t-$rest
fi
;;
-1750a-*-*)
- # 1750a is only supported as a target.
- case "$build,$host" in 1750a*,* | *,1750a* )
- echo "*** $machine is only supported as a target" >&2
- exit 1
- esac
- ;;
-a29k-*-bsd* | a29k-*-sym1*)
- tm_file="${tm_file} a29k/unix.h"
- xm_defines=POSIX
- use_collect2=yes
- ;;
-a29k-*-udi | a29k-*-coff)
- tm_file="${tm_file} dbxcoff.h"
- tmake_file=a29k/t-a29kbare
- ;;
-a29k*-*-rtems*)
- xm_defines=POSIX
- tm_file="a29k/a29k.h a29k/rtems.h rtems.h"
- tmake_file="a29k/t-a29kbare t-rtems"
- if test x$enable_threads = xyes; then
- thread_file='rtems'
- fi
- ;;
-a29k-wrs-vxworks*)
- tm_file="${tm_file} dbxcoff.h a29k/vx29k.h"
- tmake_file=a29k/t-vx29k
- extra_parts="crtbegin.o crtend.o"
- thread_file='vxworks'
- ;;
-a29k-*-*) # Default a29k environment.
- use_collect2=yes
- ;;
alpha*-*-unicosmk*)
use_collect2=yes
tm_file="${tm_file} alpha/unicosmk.h"
tmake_file="alpha/t-alpha alpha/t-ieee"
;;
-alpha*-dec-osf*)
+alpha*-dec-osf[45]*)
xm_defines=POSIX
if test x$stabs = xyes
then
extra_passes="mips-tfile mips-tdump"
fi
use_collect2=yes
- tmake_file="alpha/t-alpha alpha/t-ieee alpha/t-crtfm"
+ tmake_file="alpha/t-alpha alpha/t-ieee alpha/t-crtfm alpha/t-osf4"
+ tm_file="${tm_file} alpha/osf.h"
extra_headers=va_list.h
case $machine in
- *-*-osf1*)
- tm_file="${tm_file} alpha/osf.h alpha/osf12.h alpha/osf2or3.h"
- ;;
- *-*-osf[23]*)
- tm_file="${tm_file} alpha/osf.h alpha/osf2or3.h"
- ;;
*-*-osf4*)
- tm_file="${tm_file} alpha/osf.h"
- tmake_file="$tmake_file alpha/t-osf4"
# Some versions of OSF4 (specifically X4.0-9 296.7) have
# a broken tar, so we use cpio instead.
install_headers_dir=install-headers-cpio
+ # Set target_cpu_default except on 4.0a.
+ case $machine in
+ *-*-osf4.0a) ;;
+ *) target_cpu_default=MASK_SUPPORT_ARCH
+ esac
;;
*-*-osf5*)
- tm_file="${tm_file} alpha/osf.h alpha/osf5.h"
- tmake_file="$tmake_file alpha/t-osf4"
- float_format=i128
- ;;
- esac
- case $machine in
- *-*-osf4.0[b-z] | *-*-osf4.[1-9]* | *-*-osf5*)
+ tm_file="${tm_file} alpha/osf5.h"
target_cpu_default=MASK_SUPPORT_ARCH
+ float_format=i128
;;
esac
;;
tmake_file=arm/t-arm-coff
thread_file='vxworks'
;;
-arm-*-riscix1.[01]*) # Acorn RISC machine (early versions)
- tm_file="arm/riscix1-1.h arm/arm.h"
- use_collect2=yes
- ;;
-arm-*-riscix*) # Acorn RISC machine
- if test x$gas = xyes
- then
- tm_file="arm/riscix.h arm/rix-gas.h arm/arm.h"
- else
- tm_file="arm/riscix.h arm/arm.h"
- fi
- tmake_file=arm/t-riscix
- use_collect2=yes
- ;;
arm-semi-aout | armel-semi-aout)
tm_file="arm/semi.h arm/aout.h arm/arm.h"
tmake_file=arm/t-semi
;;
avr-*-*)
;;
-c1-convex-*) # Convex C1
- target_cpu_default=1
- use_collect2=yes
- ;;
-c2-convex-*) # Convex C2
- target_cpu_default=2
- use_collect2=yes
- ;;
-c32-convex-*)
- target_cpu_default=4
- use_collect2=yes
- ;;
-c34-convex-*)
- target_cpu_default=8
- use_collect2=yes
- ;;
-c38-convex-*)
- target_cpu_default=16
- use_collect2=yes
- ;;
c4x-*-rtems*)
xm_defines=POSIX
tmake_file="c4x/t-c4x t-rtems"
c_target_objs="c4x-c.o"
cxx_target_objs="c4x-c.o"
;;
-clipper-intergraph-clix*)
- tm_file="${tm_file} svr3.h clipper/clix.h"
- xm_defines=POSIX
- extra_parts="crtbegin.o crtend.o"
- install_headers_dir=install-headers-cpio
- ;;
cris-*-aout)
tm_file="dbxelf.h ${tm_file} cris/aout.h"
gas=yes
;;
dsp16xx-*)
;;
-elxsi-elxsi-*)
- use_collect2=yes
- ;;
fr30-*-elf)
tm_file="dbxelf.h elfos.h svr4.h ${tm_file}"
tmake_file=fr30/t-fr30
thread_file='posix'
fi
;;
-i[34567]86-*-chorusos*)
- xm_defines=POSIX
- tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h i386/i386elf.h chorus.h"
- tmake_file="i386/t-i386elf t-svr4"
- case x${enable_threads} in
- xyes | xpthreads | xposix)
- thread_file='posix'
- ;;
- esac
- ;;
i[34567]86-*-elf*)
xm_defines=POSIX
tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h i386/i386elf.h"
tmake_file="i386/t-i386elf t-svr4"
;;
-i[34567]86-ibm-aix*) # IBM PS/2 running AIX
- if test x$gas = xyes
- then
- tm_file="${tm_file} svr3.h i386/unix.h i386/att.h i386/aix386.h"
- extra_parts="crtbegin.o crtend.o"
- tmake_file=i386/t-crtstuff
- else
- tm_file="${tm_file} svr3.h i386/unix.h i386/att.h i386/aix386ng.h"
- use_collect2=yes
- fi
- xm_defines=POSIX
- ;;
i[34567]86-ncr-sysv4*) # NCR 3000 - ix86 running system V.4
xm_defines="POSIX SMALL_ARG_MAX"
if test x$stabs = xyes -a x$gas = xyes
extra_parts="crtbegin.o crtend.o"
tmake_file=i386/t-crtpic
;;
-i[34567]86-next-*)
- tm_p_file="${tm_p_file} nextstep-protos.h"
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h nextstep.h i386/next.h"
- tmake_file=i386/t-next
- extra_objs=nextstep.o
- extra_parts="crtbegin.o crtend.o"
- if test x$enable_threads = xyes; then
- thread_file='mach'
- fi
- ;;
i[34567]86-*-netware) # Intel 80386's running netware
tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h svr4.h i386/sysv4.h netware.h i386/netware.h"
tmake_file=i386/t-netware
;;
-i[34567]86-sequent-bsd*) # 80386 from Sequent
- use_collect2=yes
- if test x$gas = xyes
- then
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/sequent.h i386/seq-gas.h"
- else
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/sequent.h"
- fi
- ;;
-i[34567]86-sequent-ptx1*)
- xm_defines=POSIX
- tm_file="${tm_file} svr3.h i386/unix.h i386/att.h i386/sysv3.h i386/seq-sysv3.h"
- tmake_file=i386/t-crtstuff
- extra_parts="crtbegin.o crtend.o"
- install_headers_dir=install-headers-cpio
- ;;
-i[34567]86-sequent-ptx2* | i[34567]86-sequent-sysv3*)
- xm_defines=POSIX
- tm_file="${tm_file} svr3.h i386/unix.h i386/att.h i386/sysv3.h i386/seq-sysv3.h i386/seq2-sysv3.h"
- tmake_file=i386/t-crtstuff
- extra_parts="crtbegin.o crtend.o"
- install_headers_dir=install-headers-cpio
- ;;
i[34567]86-sequent-ptx4* | i[34567]86-sequent-sysv4*)
if test x$gas = xyes
then
extra_parts="crtbegin.o crtend.o"
install_headers_dir=install-headers-cpio
;;
-i386-sun-sunos*) # Sun i386 roadrunner
- xm_defines=POSIX
- tm_file="${tm_file} i386/unix.h i386/sun386.h i386/sun.h"
- use_collect2=yes
+i[34567]86-sequent-sysv*) # would otherwise be caught by i?86-*-sysv*
+ echo "*** Configuration $machine not supported" 1>&2
+ exit 1
;;
i[34567]86-wrs-vxworks*)
tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h i386/i386-aout.h i386/vxi386.h"
tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h svr4.h i386/beos-elf.h"
extra_parts='crtbegin.o crtend.o'
;;
-i[34567]86-*-bsdi* | i[34567]86-*-bsd386*)
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h i386/386bsd.h i386/bsd386.h"
-# tmake_file=t-libc-ok
- ;;
-i[34567]86-*-bsd*)
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h i386/386bsd.h"
-# tmake_file=t-libc-ok
-# Next line turned off because both 386BSD and BSD/386 use GNU ld.
-# use_collect2=yes
- ;;
-i[34567]86-*-freebsd[12] | i[34567]86-*-freebsd[12].* | i[34567]86-*-freebsd*aout*)
+i[34567]86-*-freebsd2 | i[34567]86-*-freebsd2.* | i[34567]86-*-freebsd*aout*)
tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h i386/freebsd-aout.h"
tmake_file=t-freebsd
;;
i[34567]86-*-coff*)
tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h dbxcoff.h i386/i386-coff.h"
;;
-i[34567]86-*-isc*) # 80386 running ISC system
- xm_defines=POSIX
- if test x$gas = xyes -a x$stabs = xyes
- then
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/svr3gas.h i386/svr3dbx.h i386/iscdbx.h"
- tmake_file=i386/t-svr3dbx
- extra_parts="svr3.ifile svr3z.ifile"
- else
- tm_file="${tm_file} svr3.h i386/unix.h i386/att.h i386/sysv3.h i386/isc.h"
- tmake_file=i386/t-crtstuff
- extra_parts="crtbegin.o crtend.o"
- fi
- install_headers_dir=install-headers-cpio
- ;;
-i[34567]86-*-linux*oldld*) # Intel 80386's running GNU/Linux
- # with a.out format using
- # pre BFD linkers
- tmake_file="t-linux-aout i386/t-crtstuff"
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h linux-aout.h i386/linux-oldld.h"
- gnu_ld=yes
- float_format=i386
+i[34567]86-*-linux*oldld*) # would otherwise be caught by i?86-*-linux*
+ echo "*** Configuration $machine not supported" 1>&2
+ exit 1
;;
i[34567]86-*-linux*aout*) # Intel 80386's running GNU/Linux
# with a.out format
# tmake_file=t-libc-ok
use_collect2=yes
;;
-i[34567]86-*-osfrose*) # 386 using OSF/rose
- if test x$elf = xyes
- then
- tm_file="${tm_file} halfpic.h i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h i386/osfrose.h i386/osfelf.h"
- use_collect2=
- else
- tm_file="${tm_file} halfpic.h i386/unix.h i386/bsd.h i386/gas.h i386/gstabs.h i386/osfrose.h"
- use_collect2=yes
- fi
- tmake_file=i386/t-osf
- extra_objs=halfpic.o
- ;;
-i[34567]86-go32-rtems*)
- xm_defines=POSIX
- tm_file="dbxcoff.h ${tm_file} i386/djgpp.h i386/djgpp-rtems.h rtems.h"
- tmake_file=t-rtems
- if test x$enable_threads = xyes; then
- thread_file='rtems'
- fi
- ;;
-i[34567]86-*-rtemscoff*)
- xm_defines=POSIX
- tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h dbxcoff.h i386/i386-coff.h i386/rtems.h rtems.h"
- tmake_file=t-rtems
- if test x$enable_threads = xyes; then
- thread_file='rtems'
- fi
+i[34567]86-go32-rtems* | i[34567]86-*-rtemscoff*)
+ # would otherwise be caught by i?86-*-rtems*
+ echo "*** Configuration $machine not supported" 1>&2
+ exit 1
;;
-i[34567]86-*-rtems*|i[34567]86-*-rtemself*)
+i[34567]86-*-rtems*)
xm_defines=POSIX
tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h i386/i386elf.h i386/rtemself.h rtems.h"
extra_parts="crtbegin.o crtend.o crti.o crtn.o"
extra_parts="crtbegin.o crtend.o"
install_headers_dir=install-headers-cpio
;;
-i[34567]86-*-osf1*) # Intel 80386's running OSF/1 1.3+
- xm_defines='POSIX USE_C_ALLOCA SMALL_ARG_MAX'
- if test x$stabs = xyes
- then
- tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h svr4.h i386/sysv4.h i386/osf1elf.h i386/osf1elfgdb.h"
- else
- tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h svr4.h i386/sysv4.h i386/osf1elf.h"
- fi
- tmake_file=i386/t-osf1elf
- extra_parts="crti.o crtn.o crtbegin.o crtend.o"
- ;;
i[34567]86-*-sysv*) # Intel 80386's running system V
xm_defines=POSIX
if test x$gas = xyes
then
tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/svr3gas.h i386/svr3dbx.h"
tmake_file=i386/t-svr3dbx
- extra_parts="svr3.ifile svr3z.rfile"
+ extra_parts="svr3.ifile svr3z.ifile"
else
tm_file="${tm_file} i386/unix.h i386/bsd.h i386/gas.h i386/svr3gas.h"
extra_parts="crtbegin.o crtend.o"
tm_file="${tm_file} dbxcoff.h"
fi
;;
-i[34567]86-dg-dgux*)
- xm_defines=POSIX
- tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h svr4.h i386/sysv4.h i386/dgux.h"
- tmake_file=i386/t-dgux
- install_headers_dir=install-headers-cpio
- ;;
-i860-alliant-*) # Alliant FX/2800
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h i860/sysv4.h i860/fx2800.h"
- tmake_file=i860/t-fx2800
- extra_parts="crtbegin.o crtend.o"
- ;;
-i860-*-bsd*)
- tm_file="${tm_file} i860/bsd.h"
- if test x$gas = xyes
- then
- tm_file="${tm_file} i860/bsd-gas.h"
- fi
- use_collect2=yes
- ;;
-i860-*-mach*)
- tm_file="${tm_file} i860/mach.h"
- tmake_file=t-libc-ok
- ;;
-i860-*-osf*) # Intel Paragon XP/S, OSF/1AD
- tm_file="${tm_file} svr3.h i860/paragon.h"
- xm_defines=POSIX
- ;;
-i860-*-sysv3*)
- tm_file="${tm_file} svr3.h i860/sysv3.h"
- xm_defines=POSIX
- extra_parts="crtbegin.o crtend.o"
- ;;
-i860-*-sysv4*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h i860/sysv4.h"
- xm_defines=POSIX
- tmake_file=t-svr4
- extra_parts="crtbegin.o crtend.o"
- ;;
i960-wrs-vxworks5 | i960-wrs-vxworks5.0*)
tm_file="${tm_file} i960/vx960.h"
tmake_file=i960/t-vxworks960
out_file="m68hc11/m68hc11.c"
tmake_file="m68hc11/t-m68hc11-gas"
;;
-m68000-convergent-sysv*)
- tm_file=m68k/ctix.h
- xm_defines=POSIX
- use_collect2=yes
- ;;
m68000-hp-bsd*) # HP 9000/200 running BSD
tm_file=m68k/hp2bsd.h
use_collect2=yes
fi
use_collect2=yes
;;
-m68k-apple-aux*) # Apple Macintosh running A/UX
- xm_defines=POSIX
- tmake_file=m68k/t-aux
- install_headers_dir=install-headers-cpio
- extra_parts="crt1.o mcrt1.o maccrt1.o crt2.o crtn.o"
- tm_file=
- if test "$gnu_ld" = yes
- then
- tm_file="${tm_file} m68k/auxgld.h"
- else
- tm_file="${tm_file} m68k/auxld.h"
- fi
- if test "$gas" = yes
- then
- tm_file="${tm_file} m68k/auxgas.h"
- else
- tm_file="${tm_file} m68k/auxas.h"
- fi
- tm_file="${tm_file} m68k/a-ux.h"
- float_format=m68k
- ;;
-m68k-apollo-*)
- tm_file=m68k/apollo68.h
- use_collect2=yes
- float_format=m68k
- ;;
-m68k-altos-sysv*) # Altos 3068
- if test x$gas = xyes
- then
- tm_file=m68k/altos3068.h
- xm_defines=POSIX
- else
- echo "The Altos is supported only with the GNU assembler" 1>&2
- exit 1
- fi
- ;;
-m68k-bull-sysv*) # Bull DPX/2
- if test x$gas = xyes
- then
- if test x$stabs = xyes
- then
- tm_file=m68k/dpx2cdbx.h
- else
- tm_file=m68k/dpx2g.h
- fi
- else
- tm_file=m68k/dpx2.h
- fi
- xm_defines=POSIX
- use_collect2=yes
- ;;
m68k-atari-sysv4*) # Atari variant of V.4.
tm_file=m68k/atari.h
xm_defines=POSIX
extra_parts="crtbegin.o crtend.o"
float_format=m68k
;;
+m68k-apollo-sysv* | m68k-bull-sysv*)
+ # can otherwise be caught by m68k-*-sysv4*
+ echo "*** Configuration $machine not supported" 1>&2
+ exit 1
+ ;;
m68k-motorola-sysv*)
tm_file=m68k/mot3300.h
xm_defines=POSIX
use_collect2=yes
float_format=m68k
;;
-m68k-isi-bsd*)
- if test x$with_fp = xno
- then
- tm_file=m68k/isi-nfp.h
- else
- tm_file=m68k/isi.h
- float_format=m68k
- fi
- use_collect2=yes
- ;;
m68k-hp-hpux7*) # HP 9000 series 300 running HPUX version 7.
xm_defines=POSIX
if test x$gas = xyes
use_collect2=yes
float_format=m68k
;;
-m68k-sony-newsos3*)
- if test x$gas = xyes
- then
- tm_file=m68k/news3gas.h
- else
- tm_file=m68k/news3.h
- fi
- use_collect2=yes
- float_format=m68k
- ;;
-m68k-sony-bsd* | m68k-sony-newsos*)
- if test x$gas = xyes
- then
- tm_file=m68k/newsgas.h
- else
- tm_file=m68k/news.h
- fi
- use_collect2=yes
- float_format=m68k
- ;;
-m68k-next-nextstep2*)
- tm_p_file="${tm_p_file} nextstep-protos.h"
- tm_file=m68k/next21.h
- tmake_file=m68k/t-next
- xmake_file=m68k/x-next
- extra_objs=nextstep.o
- use_collect2=yes
- float_format=m68k
- ;;
-m68k-next-nextstep[34]*)
- tm_p_file="${tm_p_file} nextstep-protos.h"
- tm_file=m68k/next.h
- tmake_file=m68k/t-next
- xmake_file=m68k/x-next
- extra_objs=nextstep.o
- extra_parts="crtbegin.o crtend.o"
- float_format=m68k
- if test x$enable_threads = xyes; then
- thread_file='mach'
- fi
- ;;
m68k-sun-sunos3*)
if test x$with_fp = xno
then
tmake_file=m68k/t-m68kelf
extra_parts="crtbegin.o crtend.o"
;;
-m68k-*-lynxos*)
- if test x$gas = xyes
- then
- tm_file=m68k/lynx.h
- else
- tm_file=m68k/lynx-ng.h
- fi
- tmake_file=m68k/t-lynx
- float_format=m68k
- ;;
m68010-*-netbsdelf* | m68k*-*-netbsdelf*)
tm_file="${tm_file} dbxelf.h elfos.h netbsd.h netbsd-elf.h m68k/netbsd-elf.h"
case $machine in
# we need collect2 until our bug is fixed...
use_collect2=yes
;;
-m68k-*-sysv3*) # Motorola m68k's running system V.3
- xm_defines=POSIX
- extra_parts="crtbegin.o crtend.o"
- float_format=m68k
- ;;
m68k-*-sysv4*) # Motorola m68k's running system V.4
tm_file=m68k/m68kv4.h
xm_defines=POSIX
tm_file=m68k/m68k-psos.h
float_format=m68k
;;
-m68k-*-rtemscoff*)
- xm_defines=POSIX
- tmake_file="m68k/t-m68kbare t-rtems"
- tm_file="m68k/m68k-coff.h m68k/rtems.h rtems.h"
- float_format=m68k
- if test x$enable_threads = xyes; then
- thread_file='rtems'
- fi
+m68k-*-rtemscoff*) # would otherwise be caught by m68k-*-rtems*
+ echo "*** Configuration $machine not supported" 1>&2
+ exit 1
;;
-m68k-*-rtemself*|m68k-*-rtems*)
+m68k-*-rtems*)
xm_defines=POSIX
tmake_file="m68k/t-m68kbare t-rtems m68k/t-crtstuff"
tm_file="m68k/m68k-none.h m68k/m68kelf.h dbxelf.h elfos.h m68k/m68kemb.h m68k/m68020-elf.h m68k/rtemself.h rtems.h"
thread_file='rtems'
fi
;;
-m88k-dg-dgux*)
- xm_defines=POSIX
- case $machine in
- m88k-dg-dguxbcs*)
- tm_file="dbxelf.h elfos.h svr4.h m88k/dgux.h m88k/dguxbcs.h"
- tmake_file="m88k/t-dgux m88k/t-dguxbcs"
- ;;
- *)
- tm_file="dbxelf.h elfos.h svr4.h m88k/dgux.h"
- tmake_file=m88k/t-dgux
- ;;
- esac
- extra_parts="crtbegin.o bcscrtbegin.o crtend.o m88kdgux.ld"
- if test x$gas = xyes
- then
- tmake_file=m88k/t-dgux-gas
- fi
- ;;
-m88k-dolphin-sysv3*)
- xm_defines=POSIX
- tm_file=m88k/dolph.h
- extra_parts="crtbegin.o crtend.o"
- tmake_file=m88k/t-dolph
- if test x$gas = xyes
- then
- tmake_file=m88k/t-m88k-gas
- fi
- ;;
-m88k-tektronix-sysv3)
- xm_defines=POSIX
- tm_file=m88k/tekXD88.h
- extra_parts="crtbegin.o crtend.o"
- tmake_file=m88k/t-tekXD88
- if test x$gas = xyes
- then
- tmake_file=m88k/t-m88k-gas
- fi
- ;;
m88k-*-aout*)
xm_defines=POSIX
tm_file=m88k/m88k-aout.h
;;
-m88k-*-coff*)
- xm_defines=POSIX
- tm_file=m88k/m88k-coff.h
- tmake_file=m88k/t-bug
- ;;
-m88k-*-luna*)
- tm_file=m88k/luna.h
- extra_parts="crtbegin.o crtend.o"
- if test x$gas = xyes
- then
- tmake_file=m88k/t-luna-gas
- else
- tmake_file=m88k/t-luna
- fi
- ;;
m88k-*-openbsd*)
tmake_file="${tmake_file} m88k/t-luna-gas"
tm_file="m88k/aout-dbx.h aoutos.h m88k/m88k.h openbsd.h ${tm_file}"
;;
-m88k-*-sysv3*)
- xm_defines=POSIX
- tm_file=m88k/sysv3.h
- extra_parts="crtbegin.o crtend.o"
- if test x$gas = xyes
- then
- tmake_file=m88k/t-m88k-gas
- fi
- ;;
m88k-*-sysv4*)
xm_defines=POSIX
tm_file="dbxelf.h elfos.h svr4.h m88k/sysv4.h"
# thread_file='irix'
# fi
;;
-mips-sgi-irix4loser*) # Mostly like a MIPS.
- tm_file="mips/iris4loser.h mips/iris3.h ${tm_file} mips/iris4.h"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- tmake_file=mips/t-iris
- xm_defines=POSIX
- if test x$gas = xyes
- then :
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
-# if test x$enable_threads = xyes; then
-# thread_file='irix'
-# fi
- ;;
-mips-sgi-irix4*) # Mostly like a MIPS.
- tm_file="mips/iris3.h ${tm_file} mips/iris4.h"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- tmake_file=mips/t-iris
- xm_defines=POSIX
- if test x$gas = xyes
- then :
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
-# if test x$enable_threads = xyes; then
-# thread_file='irix'
-# fi
- ;;
-mips-sgi-*) # Mostly like a MIPS.
- tm_file="mips/iris3.h ${tm_file}"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- xm_defines=POSIX
- if test x$gas = xyes
- then :
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-dec-osfrose*) # Decstation running OSF/1 reference port with OSF/rose.
- tm_file="mips/osfrose.h ${tm_file}"
- extra_objs=halfpic.o
- use_collect2=yes
- ;;
-mips-dec-osf*) # Decstation running OSF/1 as shipped by DIGITAL
- tm_file=mips/dec-osf1.h
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then :
- else
- tmake_file=mips/t-ultrix
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
+mips-sgi-*) # would otherwise be caught by mips-*-elf*
+ echo "*** Configuration $machine not supported" 1>&2
+ exit 1
;;
-mips-dec-bsd*) # Decstation running 4.4 BSD
- tm_file=mips/dec-bsd.h
- if test x$gas = xyes
- then :
- else
- tmake_file=mips/t-ultrix
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
mips*-*-netbsd*) # NetBSD/mips, either endian.
tm_file="elfos.h mips/netbsd.h"
case $machine in
target_cpu_default="MASK_GAS|MASK_ABICALLS"
tm_file="mips/openbsd-be.h ${tm_file}"
;;
-mips-sony-bsd* | mips-sony-newsos*) # Sony NEWS 3600 or risc/news.
- tm_file="mips/news4.h ${tm_file}"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then :
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-sony-sysv*) # Sony NEWS 3800 with NEWSOS5.0.
- # That is based on svr4.
- # t-svr4 is not right because this system doesn't use ELF.
- tm_file="mips/news5.h ${tm_file}"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- xm_defines=POSIX
- if test x$gas = xyes
- then :
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-tandem-sysv4*) # Tandem S2 running NonStop UX
- tm_file="mips/svr4-5.h mips/svr4-t.h"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- xm_defines=POSIX
- if test x$gas = xyes
- then
- extra_parts="crtbegin.o crtend.o"
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-ultrix* | mips-dec-mach3) # Decstation.
- tm_file="mips/ultrix.h ${tm_file}"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then :
- else
- tmake_file=mips/t-ultrix
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-riscos[56789]bsd*)
- tm_file=mips/bsd-5.h # MIPS BSD 4.3, RISC-OS 5.0
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then
- tmake_file=mips/t-bsd-gas
- else
- tmake_file=mips/t-bsd
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-bsd* | mips-*-riscosbsd* | mips-*-riscos[1234]bsd*)
- tm_file="mips/bsd-4.h ${tm_file}" # MIPS BSD 4.3, RISC-OS 4.0
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then
- tmake_file=mips/t-bsd-gas
- else
- tmake_file=mips/t-bsd
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-riscos[56789]sysv4*)
- tm_file=mips/svr4-5.h # MIPS System V.4., RISC-OS 5.0
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then
- tmake_file=mips/t-svr4-gas
- else
- tmake_file=mips/t-svr4
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-sysv4* | mips-*-riscos[1234]sysv4* | mips-*-riscossysv4*)
- tm_file="mips/svr4-4.h ${tm_file}"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- xm_defines=POSIX
- if test x$gas = xyes
- then
- tmake_file=mips/t-svr4-gas
- else
- tmake_file=mips/t-svr4
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-riscos[56789]sysv*)
- tm_file=mips/svr3-5.h # MIPS System V.3, RISC-OS 5.0
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- xm_defines=POSIX
- if test x$gas = xyes
- then
- tmake_file=mips/t-svr3-gas
- else
- tmake_file=mips/t-svr3
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-sysv* | mips-*-riscos*sysv*)
- tm_file="mips/svr3-4.h ${tm_file}"
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- xm_defines=POSIX
- if test x$gas = xyes
- then
- tmake_file=mips/t-svr3-gas
- else
- tmake_file=mips/t-svr3
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
-mips-*-riscos[56789]*) # Default MIPS RISC-OS 5.0.
- tm_file=mips/mips-5.h
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then :
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
mipsel-*-ecoff*)
tm_file=mips/ecoffl.h
if test x$stabs = xyes; then
tm_file="mips/r3900.h mips/elf.h mips/abi64.h"
tmake_file=mips/t-r3900
;;
-mips-*-*) # Default MIPS RISC-OS 4.0.
- if test x$stabs = xyes; then
- tm_file="${tm_file} dbx.h"
- fi
- if test x$gas = xyes
- then :
- else
- extra_passes="mips-tfile mips-tdump"
- fi
- if test x$gnu_ld != xyes
- then
- use_collect2=yes
- fi
- ;;
mmix-knuth-mmixware)
;;
mn10200-*-*)
fi
use_collect2=no
;;
-ns32k-encore-bsd*)
- tm_file=ns32k/encore.h
- use_collect2=yes
- ;;
-ns32k-sequent-bsd*)
- tm_file=ns32k/sequent.h
- use_collect2=yes
- ;;
-ns32k-tek6100-bsd*)
- tm_file=ns32k/tek6100.h
- use_collect2=yes
- ;;
-ns32k-tek6200-bsd*)
- tm_file=ns32k/tek6200.h
- use_collect2=yes
- ;;
-ns32k-merlin-*)
- tm_file=ns32k/merlin.h
- use_collect2=yes
- ;;
-ns32k-pc532-mach*)
- tm_file=ns32k/pc532-mach.h
- use_collect2=yes
- ;;
-ns32k-pc532-minix*)
- tm_file=ns32k/pc532-min.h
- xm_defines='POSIX HZ=60'
- use_collect2=yes
- ;;
ns32k-*-netbsdelf*)
echo "GCC does not yet support the ${machine} target"; exit 1
;;
ns32k-*-openbsd*)
# Nothing special
;;
-pj*-linux*)
- tm_file="dbxelf.h elfos.h svr4.h pj/linux.h ${tm_file}"
- ;;
-pj-*)
- ;;
-pjl-*)
- tm_file="dbxelf.h elfos.h svr4.h pj/pjl.h ${tm_file}"
- ;;
-
-romp-*-aos*)
- use_collect2=yes
- ;;
-romp-*-mach*)
- use_collect2=yes
- ;;
romp-*-openbsd*)
# Nothing special
;;
tmake_file="sh/t-sh sh/t-elf sh/t-sh64"
tm_file="${tm_file} sh/sh.h sh/embed-elf.h sh/sh64.h"
float_format=sh
- extra_headers="../../config/sh/shmedia.h ../../config/sh/ushmedia.h ../../config/sh/sshmedia.h"
+ extra_headers="shmedia.h ushmedia.h sshmedia.h"
# Not strictly necessary to check this, but a good idea anyway.
if test $machine = $target; then
target_requires_64bit_host_wide_int=yes
fi
tmake_file=sparc/t-sunos41
;;
-sparc-*-rtemsaout*)
- xm_defines=POSIX
- tmake_file="sparc/t-sparcbare t-rtems"
- tm_file="${tm_file} aoutos.h sparc/aout.h sparc/rtems.h rtems.h"
- if test x$enable_threads = xyes; then
- thread_file='rtems'
- fi
+sparc-*-rtemsaout*) # would otherwise be caught by sparc-*-rtems*
+ echo "*** Configuration $machine not supported" 1>&2
+ exit 1
;;
-sparc-*-rtems*|sparc-*-rtemself*)
+sparc-*-rtems*)
xm_defines=POSIX
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sol2.h sparc/elf.h sparc/rtemself.h rtems.h"
tmake_file="sparc/t-elf sparc/t-crtfm t-rtems"
vax-*-*) # VAX default entry
float_format=vax
;;
-we32k-att-sysv*)
- xm_defines=POSIX
- use_collect2=yes
- ;;
xscale-*-elf)
tm_file="arm/xscale-elf.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h"
tmake_file=arm/t-xscale-elf
fi
;;
*)
- echo "Configuration $machine not supported" 1>&2
+ echo "*** Configuration $machine not supported" 1>&2
exit 1
;;
esac
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Copyright (C) 2000 Free Software Foundation, Inc.
- Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifdef RTX_CODE
-#ifdef TREE_CODE
-extern struct rtx_def *function_arg PARAMS ((int, enum machine_mode, tree, int));
-#endif /* TREE_CODE */
-extern const char *movcnt_regno_adjust PARAMS ((rtx *));
-extern const char *mod_regno_adjust PARAMS ((const char *, rtx *));
-extern void notice_update_cc PARAMS ((rtx));
-extern int memop_valid PARAMS ((rtx));
-extern int mov_memory_operand PARAMS ((rtx, enum machine_mode));
-extern int small_nonneg_const PARAMS ((rtx, enum machine_mode));
-extern int zero_operand PARAMS ((rtx, enum machine_mode));
-extern int b_mode_operand PARAMS ((rtx));
-extern int unsigned_comparison_operator PARAMS ((rtx));
-extern int next_cc_user_is_unsigned PARAMS ((rtx));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-#endif /* RTX_CODE */
-
-extern const char *branch_or_jump PARAMS ((const char *, int));
-extern int find_jmplbl PARAMS ((int));
-extern int one_bit_set_p PARAMS ((int));
-extern void check_section PARAMS ((enum section));
-
-extern long real_value_to_target_single PARAMS((double));
-extern void real_value_to_target_double PARAMS((double, long[]));
+++ /dev/null
-/* Subroutines for insn-output.c for MIL-STD-1750.
- Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999,
- 2000 Free Software Foundation, Inc.
- Contributed by O.M.Kellogg, DASA (kellogg@space.otn.dasa.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define __datalbl
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "tree.h"
-#include "function.h"
-#include "expr.h"
-#define HAVE_cc0
-#include "conditions.h"
-#include "real.h"
-#include "regs.h"
-#include "output.h"
-#include "flags.h"
-#include "tm_p.h"
-#include "target.h"
-#include "target-def.h"
-
-struct datalabel_array datalbl[DATALBL_ARRSIZ];
-int datalbl_ndx = -1;
-struct jumplabel_array jmplbl[JMPLBL_ARRSIZ];
-int jmplbl_ndx = -1;
-int label_pending = 0, program_counter = 0;
-enum section current_section = Normal;
-const char *const sectname[4] =
-{"Init", "Normal", "Konst", "Static"};
-
-static int which_bit PARAMS ((int));
-static bool assemble_integer_1750a PARAMS ((rtx, unsigned int, int));
-static void output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_BYTE_OP
-#define TARGET_ASM_BYTE_OP "\tdata\t"
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\tdatal\t"
-#undef TARGET_ASM_ALIGNED_SI_OP
-#define TARGET_ASM_ALIGNED_SI_OP NULL
-#undef TARGET_ASM_INTEGER
-#define TARGET_ASM_INTEGER assemble_integer_1750a
-
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE output_function_epilogue
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* Generate the assembly code for function entry. FILE is a stdio
- stream to output the code to. SIZE is an int: how many units of
- temporary storage to allocate.
-
- Refer to the array `regs_ever_live' to determine which registers to
- save; `regs_ever_live[I]' is nonzero if register number I is ever
- used in the function. This function is responsible for knowing
- which registers should not be saved even if used. */
-
-static void
-output_function_prologue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- if (flag_verbose_asm)
- {
- int regno, regs_used = 0;
-
- fprintf (file, "\t; registers used: ");
- for (regno = 0; regno < 14; regno++)
- if (regs_ever_live[regno])
- {
- fprintf (file, " %s", reg_names[regno]);
- regs_used++;
- }
-
- if (regs_used == 0)
- fprintf (file, "(none)");
- }
-
- if (size > 0)
- {
- fprintf (file, "\n\t%s\tr15,%d",
- (size <= 16 ? "sisp" : "sim"), size);
- if (flag_verbose_asm)
- fprintf (file, " ; reserve local-variable space");
- }
-
- if (frame_pointer_needed)
- {
- fprintf(file, "\n\tpshm\tr14,r14");
- if (flag_verbose_asm)
- fprintf (file, " ; push old frame");
- fprintf (file, "\n\tlr\tr14,r15");
- if (flag_verbose_asm)
- fprintf (file, " ; set new frame");
- }
-
- fprintf (file, "\n");
- program_counter = 0;
- jmplbl_ndx = -1;
-}
-
-/* This function generates the assembly code for function exit.
- Args are as for output_function_prologue ().
-
- The function epilogue should not depend on the current stack
- pointer! It should use the frame pointer only. This is mandatory
- because of alloca; we also take advantage of it to omit stack
- adjustments before returning. */
-
-static void
-output_function_epilogue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- if (frame_pointer_needed)
- {
- fprintf (file, "\tlr\tr15,r14");
- if (flag_verbose_asm)
- fprintf (file, " ; set stack ptr to frame ptr");
- fprintf (file, "\n\tpopm\tr14,r14");
- if (flag_verbose_asm)
- fprintf (file, " ; restore previous frame ptr");
- fprintf (file, "\n");
- }
-
- if (size > 0)
- {
- fprintf (file, "\t%s\tr15,%d",
- (size <= 16 ? "aisp" : "aim"), size);
- if (flag_verbose_asm)
- fprintf (file, " ; free up local-var space");
- fprintf (file, "\n");
- }
-
- fprintf (file, "\turs\tr15\n\n");
-}
-
-void
-notice_update_cc (exp)
- rtx exp;
-{
- if (GET_CODE (exp) == SET)
- {
- enum rtx_code src_code = GET_CODE (SET_SRC (exp));
- /* Jumps do not alter the cc's. */
- if (SET_DEST (exp) == pc_rtx)
- return;
- /* Moving a register or constant into memory doesn't alter the cc's. */
- if (GET_CODE (SET_DEST (exp)) == MEM
- && (src_code == REG || src_code == CONST_INT))
- return;
- /* Function calls clobber the cc's. */
- if (src_code == CALL)
- {
- CC_STATUS_INIT;
- return;
- }
- /* Emulated longword bit-ops leave cc's incorrect */
- if (GET_MODE (SET_DEST (exp)) == HImode ?
- src_code == AND || src_code == IOR ||
- src_code == XOR || src_code == NOT : 0)
- {
- CC_STATUS_INIT;
- return;
- }
- /* Tests and compares set the cc's in predictable ways. */
- if (SET_DEST (exp) == cc0_rtx)
- {
- CC_STATUS_INIT;
- cc_status.value1 = SET_SRC (exp);
- return;
- }
- /* Anything else will set cc_status. */
- cc_status.flags = CC_NO_OVERFLOW;
- cc_status.value1 = SET_SRC (exp);
- cc_status.value2 = SET_DEST (exp);
- return;
- }
- else if (GET_CODE (exp) == PARALLEL
- && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
- {
- if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
- return;
- if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
- {
- CC_STATUS_INIT;
- cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
- return;
- }
- CC_STATUS_INIT;
- }
- else
- {
- CC_STATUS_INIT;
- }
-}
-
-
-rtx
-function_arg (cum, mode, type, named)
- int cum;
- enum machine_mode mode;
- tree type;
- int named ATTRIBUTE_UNUSED;
-{
- int size;
-
- if (MUST_PASS_IN_STACK (mode, type))
- return (rtx) 0;
- if (mode == BLKmode)
- size = int_size_in_bytes (type);
- else
- size = GET_MODE_SIZE (mode);
- if (cum + size < 12)
- return gen_rtx_REG (mode, cum);
- else
- return (rtx) 0;
-}
-
-const char *
-movcnt_regno_adjust (op)
- rtx *op;
-{
- static char outstr[80];
- int op0r = REGNO (op[0]), op1r = REGNO (op[1]), op2r = REGNO (op[2]);
-#define dstreg op0r
-#define srcreg op1r
-#define cntreg op2r
-#define cntreg_1750 (op0r + 1)
-
- if (cntreg == cntreg_1750)
- sprintf (outstr, "mov r%d,r%d", op0r, op1r);
- else if (dstreg + 1 == srcreg && cntreg > srcreg)
- sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d", op2r, op1r, op0r, op2r);
- else if (dstreg == cntreg + 1)
- sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d", op0r, op2r, op2r, op1r);
- else if (dstreg == srcreg + 1)
- sprintf (outstr, "xwr r%d,r%d\n\txwr r%d,r%d\n\tmov r%d,r%d",
- op0r, op1r, op0r, op2r, op1r, op2r);
- else if (cntreg + 1 == srcreg)
- sprintf (outstr, "xwr r%d,r%d\n\txwr r%d,r%d\n\tmov r%d,r%d",
- op2r, op1r, op0r, op2r, op2r, op0r);
- else if (cntreg == srcreg + 1)
- sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d", op0r, op1r, op1r, op0r);
- else
- sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d\n\txwr r%d,r%d",
- op2r, cntreg_1750, op0r, op1r, op2r, cntreg_1750);
- return outstr;
-}
-
-const char *
-mod_regno_adjust (instr, op)
- const char *instr;
- rtx *op;
-{
- static char outstr[40];
- const char *const r = (!strncmp (instr, "dvr", 3) ? "r" : "");
- int modregno_gcc = REGNO (op[3]), modregno_1750 = REGNO (op[0]) + 1;
-
- if (modregno_gcc == modregno_1750
- || (reg_renumber != NULL
- && reg_renumber[modregno_gcc] >= 0
- && reg_renumber[modregno_gcc] == reg_renumber[modregno_1750]))
- sprintf (outstr, "%s r%%0,%s%%2", instr, r);
- else
- sprintf (outstr, "lr r%d,r%d\n\t%s r%%0,%s%%2\n\txwr r%d,r%d",
- modregno_gcc, modregno_1750, instr, r, modregno_1750,
- modregno_gcc);
- return outstr;
-}
-
-
-/* Check if op is a valid memory operand for 1750A Load/Store instructions
- (memory indirection permitted.) */
-
-int
-memop_valid (op)
- rtx op;
-{
- static int recurred = 0;
- int valid_operand;
-
- if (GET_MODE (op) != Pmode && GET_MODE (op) != VOIDmode
- && GET_MODE (op) != QImode)
- return 0;
- switch (GET_CODE (op))
- {
- case MEM:
- if (!recurred && GET_CODE (XEXP (op, 0)) == REG)
- return 1;
- case MINUS:
- case MULT:
- case DIV:
- return 0;
- case PLUS:
- recurred = 1;
- valid_operand = memop_valid (XEXP (op, 0));
- if (valid_operand)
- valid_operand = memop_valid (XEXP (op, 1));
- recurred = 0;
- return valid_operand;
- case REG:
- if (REGNO (op) > 0)
- return 1;
- return 0;
- case CONST:
- case CONST_INT:
- case SYMBOL_REF:
- case SUBREG:
- return 1;
- default:
- printf ("memop_valid: code=%d\n", (int) GET_CODE (op));
- return 1;
- }
-}
-
-
-/* predicate for the MOV instruction: */
-int
-mov_memory_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG);
-}
-
-/* predicate for the STC instruction: */
-int
-small_nonneg_const (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- if (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) <= 15)
- return 1;
- return 0;
-}
-
-/* predicate for constant zero: */
-int
-zero_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return op == CONST0_RTX (mode);
-}
-
-
-/* predicate for 1750 `B' addressing mode (Base Register with Offset)
- memory operand */
-int
-b_mode_operand (op)
- rtx op;
-{
- if (GET_CODE (op) == MEM)
- {
- rtx inner = XEXP (op, 0);
- if (GET_CODE (inner) == REG && REG_OK_FOR_INDEX_P (inner))
- return 1;
- if (GET_CODE (inner) == PLUS)
- {
- rtx plus_op0 = XEXP (inner, 0);
- if (GET_CODE (plus_op0) == REG && REG_OK_FOR_INDEX_P (plus_op0))
- {
- rtx plus_op1 = XEXP (inner, 1);
- if (GET_CODE (plus_op1) == CONST_INT
- && INTVAL (plus_op1) >= 0
- && INTVAL (plus_op1) <= 255)
- return 1;
- }
- }
- }
- return 0;
-}
-
-
-/* Decide whether to output a conditional jump as a "Jump Conditional"
- or as a "Branch Conditional": */
-
-int
-find_jmplbl (labelnum)
- int labelnum;
-{
- int i, found = 0;
-
- for (i = 0; i <= jmplbl_ndx; i++)
- if (labelnum == jmplbl[i].num)
- {
- found = 1;
- break;
- }
- if (found)
- return i;
- return -1;
-}
-
-const char *
-branch_or_jump (condition, targetlabel_number)
- const char *condition;
- int targetlabel_number;
-{
- static char buf[30];
- int index;
-
- if ((index = find_jmplbl (targetlabel_number)) >= 0)
- if (program_counter - jmplbl[index].pc < 128)
- {
- sprintf (buf, "b%s %%l0", condition);
- return buf;
- }
- sprintf (buf, "jc %s,%%l0", condition);
- return buf;
-}
-
-
-int
-unsigned_comparison_operator (insn)
- rtx insn;
-{
- switch (GET_CODE (insn))
- {
- case GEU:
- case GTU:
- case LEU:
- case LTU:
- return 1;
- default:
- return 0;
- }
-}
-
-int
-next_cc_user_is_unsigned (insn)
- rtx insn;
-{
- if ( !(insn = next_cc0_user (insn)))
- abort ();
- else if (GET_CODE (insn) == JUMP_INSN
- && GET_CODE (PATTERN (insn)) == SET
- && GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE)
- return unsigned_comparison_operator (XEXP (SET_SRC (PATTERN (insn)), 0));
- else if (GET_CODE (insn) == INSN
- && GET_CODE (PATTERN (insn)) == SET)
- return unsigned_comparison_operator (SET_SRC (PATTERN (insn)));
- else
- abort ();
-}
-
-
-static int addr_inc;
-
-/* A C compound statement to output to stdio stream STREAM the
- assembler syntax for an instruction operand X. X is an RTL
- expression.
-
- CODE is a value that can be used to specify one of several ways
- of printing the operand. It is used when identical operands
- must be printed differently depending on the context. CODE
- comes from the `%' specification that was used to request
- printing of the operand. If the specification was just `%DIGIT'
- then CODE is 0; if the specification was `%LTR DIGIT' then CODE
- is the ASCII code for LTR.
-
- If X is a register, this macro should print the register's name.
- The names can be found in an array `reg_names' whose type is
- `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
-
- When the machine description has a specification `%PUNCT' (a `%'
- followed by a punctuation character), this macro is called with
- a null pointer for X and the punctuation character for CODE.
-
- The 1750 specific codes are:
- 'J' for the negative of a constant
- 'Q' for printing addresses in B mode syntax
- 'd' for the second register in a pair
- 't' for the third register in a triple
- 'b' for the bit number (using 1750 test bit convention)
- 'B' for the bit number of the 1's complement (for bit clear)
- 'w' for int - 16
-*/
-
-void
-print_operand (file, x, letter)
- FILE *file;
- rtx x;
- int letter;
-{
- switch (GET_CODE (x))
- {
- case REG:
- if (letter == 'd')
- fprintf (file, "%d", REGNO (x) + 1);
- else if (letter == 't')
- fprintf (file, "%d", REGNO (x) + 2);
- else
- fprintf (file, "%d", REGNO (x));
- break;
-
- case SYMBOL_REF:
- fprintf (file, "%s", XSTR (x, 0));
- if (letter == 'A')
- fprintf (file, "+1");
- break;
-
- case LABEL_REF:
- case CONST:
- case MEM:
- if (letter == 'Q')
- {
- rtx inner = XEXP (x, 0);
- switch (GET_CODE (inner))
- {
- case REG:
- fprintf (file, "r%d,0", REGNO (inner));
- break;
- case PLUS:
- fprintf (file, "r%d,%d", REGNO (XEXP (inner, 0)),
- INTVAL (XEXP (inner, 1)));
- break;
- default:
- fprintf (file, "[ill Q code=%d]", GET_CODE (inner));
- }
- }
- else
- {
- addr_inc = (letter == 'A' ? 1 : 0);
- output_address (XEXP (x, 0));
- }
- break;
-
- case CONST_DOUBLE:
- {
- REAL_VALUE_TYPE r;
- char buf[30];
-
- REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- REAL_VALUE_TO_DECIMAL (r, "%f", buf);
-
- fputs (buf, file);
- }
- break;
-
- case CONST_INT:
- if (letter == 'J')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, -INTVAL (x));
- else if (letter == 'b')
- fprintf (file, "%d", which_bit (INTVAL (x)));
- else if (letter == 'B')
- fprintf (file, "%d", which_bit (~INTVAL (x)));
- else if (letter == 'w')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) - 16);
- else
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
- break;
-
- case CODE_LABEL:
- fprintf (file, "L%d", XINT (x, 3));
- break;
-
- case CALL:
- fprintf (file, "CALL nargs=");
- fprintf (file, HOST_PTR_PRINTF, (PTR) XEXP (x, 1));
- fprintf (file, ", func is either '%s' or '%s'",
- XSTR (XEXP (XEXP (x, 0), 1), 0), XSTR (XEXP (x, 0), 1));
- break;
-
- case PLUS:
- {
- rtx op0 = XEXP (x, 0), op1 = XEXP (x, 1);
- int op0code = GET_CODE (op0), op1code = GET_CODE (op1);
- if (op1code == CONST_INT)
- switch (op0code)
- {
- case REG:
- fprintf (file, "%d,r%d ; p_o_PLUS for REG and CONST_INT",
- INTVAL (op1), REGNO (op0));
- break;
- case SYMBOL_REF:
- fprintf (file, "%d+%s", INTVAL (op1), XSTR (op0, 0));
- break;
- case MEM:
- fprintf (file, "%d,[mem:", INTVAL (op1));
- output_address (XEXP (op0, 0));
- fprintf (file, "] ;P_O plus");
- break;
- default:
- fprintf (file, "p_o_PLUS UFO, code=%d, with CONST=%d",
- (int) op0code, INTVAL (op1));
- }
- else if (op1code == SYMBOL_REF && op0code == REG)
- fprintf (file, "%s,r%d ; P_O: (plus reg sym)",
- XSTR (op1, 0), REGNO (op0));
- else
- fprintf (file, "p_o_+: op0code=%d, op1code=%d", op0code, op1code);
- }
- break;
-
- default:
- fprintf (file, "p_o_UFO code=%d", GET_CODE (x));
- }
-
- addr_inc = 0;
-}
-
-void
-print_operand_address (file, addr)
- FILE *file;
- rtx addr;
-{
- switch (GET_CODE (addr))
- {
- case REG:
- fprintf (file, "%d,r%d ; P_O_A", addr_inc, REGNO (addr));
- break;
- case PLUS:
- {
- register rtx x = XEXP (addr, 0), y = XEXP (addr, 1);
- switch (GET_CODE (x))
- {
- case REG:
- switch (GET_CODE (y))
- {
- case CONST:
- output_address (XEXP (y, 0));
- fprintf (file, ",r%d ;P_O_A reg + const expr", REGNO (x));
- break;
- case CONST_INT:
- fprintf (file, "%d,r%d", INTVAL (y) + addr_inc, REGNO (x));
- break;
- case SYMBOL_REF:
- fprintf (file, "%s", XSTR (y, 0));
- if (addr_inc)
- fprintf (file, "+%d", addr_inc);
- fprintf (file, ",r%d ; P_O_A reg + sym", REGNO (x));
- break;
- case LABEL_REF:
- output_address (XEXP (y, 0));
- fprintf (file, ",r%d ; P_O_A reg + label", REGNO (x));
- break;
- default:
- fprintf (file, "[P_O_A reg%d+UFO code=%d]",
- REGNO (x), GET_CODE (y));
- }
- break;
- case LABEL_REF:
- output_address (XEXP (x, 0));
- break;
- case SYMBOL_REF:
- switch (GET_CODE (y))
- {
- case CONST_INT:
- fprintf (file, "%d+%s", INTVAL (y) + addr_inc, XSTR (x, 0));
- break;
- case REG:
- fprintf (file, "%s,r%d ;P_O_A sym + reg",
- XSTR (x, 0), REGNO (y));
- break;
- default:
- fprintf (file, "P_O_A sym/lab+UFO[sym=%s,code(y)=%d]",
- XSTR (x, 0), GET_CODE (y));
- }
- break;
- case CONST:
- output_address (XEXP (x, 0));
- if (GET_CODE (y) == REG)
- fprintf (file, ",r%d ;P_O_A const + reg", REGNO (x));
- else
- fprintf (file, "P_O_A const+UFO code(y)=%d]", GET_CODE (y));
- break;
- case MEM:
- output_address (y);
- fprintf (file, ",[mem:");
- output_address (XEXP (x, 0));
- fprintf (file, "] ;P_O_A plus");
- break;
- default:
- fprintf (file, "P_O_A plus op1_UFO[code1=%d,code2=%d]",
- GET_CODE (x), GET_CODE (y));
- }
- }
- break;
- case CONST_INT:
- if (INTVAL (addr) < 0x10000 && INTVAL (addr) >= -0x10000)
- fprintf (file, "%d ; p_o_a const addr?!", INTVAL (addr));
- else
- {
- fprintf (file, "[p_o_a=ILLEGAL_CONST]");
- output_addr_const (file, addr);
- }
- break;
- case LABEL_REF:
- case SYMBOL_REF:
- fprintf (file, "%s", XSTR (addr, 0));
- if (addr_inc)
- fprintf (file, "+%d", addr_inc);
- break;
- case MEM:
- fprintf (file, "[memUFO:");
- output_address (XEXP (addr, 0));
- fprintf (file, "]");
- break;
- case CONST:
- output_address (XEXP (addr, 0));
- fprintf (file, " ;P_O_A const");
- break;
- case CODE_LABEL:
- fprintf (file, "L%d", XINT (addr, 3));
- break;
- default:
- fprintf (file, " p_o_a UFO, code=%d val=0x%x",
- (int) GET_CODE (addr), INTVAL (addr));
- break;
- }
- addr_inc = 0;
-}
-
-/* Target hook for assembling integer objects. The 1750a version needs to
- keep track of how many bytes have been written. */
-
-static bool
-assemble_integer_1750a (x, size, aligned_p)
- rtx x;
- unsigned int size;
- int aligned_p;
-{
- if (default_assemble_integer (x, size, aligned_p))
- {
- if (label_pending)
- label_pending = 0;
- datalbl[datalbl_ndx].size += size;
- return true;
- }
- return false;
-}
-
-
-/*
- * Return non zero if the LS 16 bits of the given value has just one bit set,
- * otherwise return zero. Note this function may be used to detect one
- * bit clear by inverting the param.
- */
-int
-one_bit_set_p (x)
- int x;
-{
- x &= 0xffff;
- return x && (x & (x - 1)) == 0;
-}
-
-
-/*
- * Return the number of the least significant bit set, using the same
- * convention for bit numbering as in the MIL-STD-1750 sb instruction.
- */
-static int
-which_bit (x)
- int x;
-{
- int b = 15;
-
- while (b > 0 && (x & 1) == 0)
- {
- b--;
- x >>= 1;
- }
-
- return b;
-}
-
-\f
-/* Convert a REAL_VALUE_TYPE to the target float format:
-
- MSB LSB MSB LSB
- ------------------------------------------------------
- |S| Mantissa | Exponent |
- ------------------------------------------------------
- 0 1 23 24 31
-
-*/
-
-long
-real_value_to_target_single(in)
- REAL_VALUE_TYPE in;
-{
- union {
- double d;
- struct {
-#if HOST_WORDS_BIG_ENDIAN
- unsigned int negative:1;
- unsigned int exponent:11;
- unsigned int mantissa0:20;
- unsigned int mantissa1:32;
-#else
- unsigned int mantissa1:32;
- unsigned int mantissa0:20;
- unsigned int exponent:11;
- unsigned int negative:1;
-#endif
- } s;
- } ieee;
-
- unsigned int mant;
- int exp;
-
- if (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT)
- abort ();
-
- ieee.d = in;
-
- /* Don't bother with NaN, Inf, 0 special cases, since they'll be handled
- by the over/underflow code below. */
- exp = ieee.s.exponent - 0x3ff;
- mant = 1 << 23 | ieee.s.mantissa0 << 3 | ieee.s.mantissa1 >> 29;
-
- /* The sign is actually part of the mantessa. Since we're comming from
- IEEE we know that either bit 23 is set or we have a zero. */
- if (! ieee.s.negative)
- {
- mant >>= 1;
- exp += 1;
- }
-
- /* Check for overflow. Crop to FLT_MAX. */
- if (exp > 127)
- {
- exp = 127;
- mant = (ieee.s.negative ? 0xffffff : 0x7fffff);
- }
- /* Underflow to zero. */
- else if (exp < -128)
- {
- exp = 0;
- mant = 0;
- }
-
- return mant << 8 | (exp & 0xff);
-}
-
-/* Convert a REAL_VALUE_TYPE to the target 1750a extended float format:
-
- ----------------------------------------------------
- | | Mantissa | | Mantissa |
- |S| MS |Exponent| LS |
- ----------------------------------------------------
- 0 1 23 24 31 32 47
-
-*/
-
-void
-real_value_to_target_double(in, out)
- REAL_VALUE_TYPE in;
- long out[];
-{
- union {
- double d;
- struct {
-#if HOST_WORDS_BIG_ENDIAN
- unsigned int negative:1;
- unsigned int exponent:11;
- unsigned int mantissa0:20;
- unsigned int mantissa1:32;
-#else
- unsigned int mantissa1:32;
- unsigned int mantissa0:20;
- unsigned int exponent:11;
- unsigned int negative:1;
-#endif
- } s;
- } ieee;
-
- unsigned int mant_h24, mant_l16;
- int exp;
-
- if (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT)
- abort ();
-
- ieee.d = in;
-
- /* Don't bother with NaN, Inf, 0 special cases, since they'll be handled
- by the over/underflow code below. */
- exp = ieee.s.exponent - 0x3ff;
- mant_h24 = 1 << 23 | ieee.s.mantissa0 << 3 | ieee.s.mantissa1 >> 29;
- mant_l16 = (ieee.s.mantissa1 >> 13) & 0xffff;
-
- /* The sign is actually part of the mantessa. Since we're comming from
- IEEE we know that either bit 23 is set or we have a zero. */
- if (! ieee.s.negative)
- {
- mant_l16 = mant_l16 >> 1 | (mant_h24 & 1) << 15;
- mant_h24 >>= 1;
- exp += 1;
- }
-
- /* Check for overflow. Crop to DBL_MAX. */
- if (exp > 127)
- {
- exp = 127;
- mant_h24 = (ieee.s.negative ? 0xffffff : 0x7fffff);
- mant_l16 = 0xffff;
- }
- /* Underflow to zero. */
- else if (exp < -128)
- {
- exp = 0;
- mant_h24 = 0;
- mant_l16 = 0;
- }
-
- out[0] = mant_h24 << 8 | (exp & 0xff);
- out[1] = mant_l16;
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002 Free Software Foundation, Inc.
- Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-/* See tm-sun3.h, tm-sun2.h, tm-isi68.h for different CPP_PREDEFINES. */
-#define CPP_PREDEFINES ""
-
-/* Print subsidiary information on the compiler version in use. */
-#ifdef IEEE
-#define TARGET_VERSION fprintf (stderr, " (1750A, IEEE syntax)");
-#else
-#define TARGET_VERSION fprintf (stderr, " (MIL-STD-1750A)");
-#endif
-
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-#define TARGET_SWITCHES \
- { {"vaxc-alignment", 2, N_("Use VAX-C alignment")}, \
- { "", TARGET_DEFAULT, NULL}}
-
-/* Default target_flags if no switches specified. */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-#endif
-
-/*****************************************************************************/
-
-/* SPECIAL ADDITION FOR MIL-STD-1750A by O.M.Kellogg, 15-Apr-1993 */
-/* See file aux-output.c for the actual data instances. */
-struct datalabel_array {
- char *name;
- char value[14];
- int size;
-};
-struct jumplabel_array {
- int pc;
- int num;
-};
-enum section { Init, Normal, Konst, Static };
-#define DATALBL_ARRSIZ 256
-#define JMPLBL_ARRSIZ 256
-#ifndef __datalbl
-extern struct datalabel_array datalbl[DATALBL_ARRSIZ];
-extern struct jumplabel_array jmplbl[JMPLBL_ARRSIZ];
-extern int datalbl_ndx, jmplbl_ndx, label_pending, program_counter;
-extern enum section current_section;
-extern const char *const sectname[4];
-#endif
-/*--------------------------------------------------------------------*/
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields.
- Though 1750 actually counts bits in big-endian fashion, the sign bit
- is still the most significant bit, which is leftmost. Therefore leaving
- this little-endian. Adjust short before assembler output when needed:
- e.g. in QImode, a GCC bit n is a 1750 bit (15-n). */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-/* For 1750 we can decide arbitrarily
- since there are no machine instructions for them. */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword value is lowest
- numbered.
- True for 1750. */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 16
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 1
-
-#define PTRDIFF_TYPE "int"
-
-/* Type to use for `size_t'. If undefined, uses `long unsigned int'. */
-#define SIZE_TYPE "int"
-
-/* 1750a preliminary. Ought to properly define the format in real.c. */
-#define TARGET_FLOAT_FORMAT UNKNOWN_FLOAT_FORMAT
-
-/* Allocation boundary (in *bits*) for storing pointers in memory. */
-#define POINTER_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-/* 1750: should have had to make this 32 when BITS_PER_WORD is 32. */
-#define PARM_BOUNDARY 16
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#define STACK_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* No data type wants to be aligned rounder than this. */
-#define BIGGEST_ALIGNMENT 16
-
-/* Define this to 1 if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 0
-
-/* Define number of bits in most basic integer type.
- (If undefined, default is BITS_PER_WORD).
- #define INT_TYPE_SIZE 16 */
-
-/* Define number of bits in short integer type.
- (If undefined, default is half of BITS_PER_WORD). */
-#define SHORT_TYPE_SIZE 16
-
-/* Define number of bits in long integer type.
- (If undefined, default is BITS_PER_WORD). */
-#define LONG_TYPE_SIZE 32
-
-/* Define number of bits in long long integer type.
- (If undefined, default is twice BITS_PER_WORD). */
-/* 1750 PRELIMINARY : no processor support for `long long', therefore
- need to check out the long-long opencodings ! */
-#define LONG_LONG_TYPE_SIZE 64
-
-/* Define number of bits in float type.
- (If undefined, default is BITS_PER_WORD). */
-#define FLOAT_TYPE_SIZE 32
-
-/* Define number of bits in double type.
- (If undefined, default is twice BITS_PER_WORD). */
-#define DOUBLE_TYPE_SIZE 48
-
-/*****************************************************************************/
-
-/* Standard register usage. */
-
-/* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
- R15 is the 1750A stack pointer. R14 is the frame pointer. */
-
-#define FIXED_REGISTERS \
- { 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 1, 1 }
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like.
- 1750: return value in R0 foll. (depending on size of retval).
- Should be possible to refine this (how many regs are actually used) */
-
-#define CALL_USED_REGISTERS \
- { 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* Order in which to allocate registers. Each register must be
- listed once, even those in FIXED_REGISTERS. List frame pointer
- late and fixed registers last. Note that, in general, we prefer
- registers listed in CALL_USED_REGISTERS, keeping the others
- available for storage of persistent values. */
-
-/* #define REG_ALLOC_ORDER \
- { 2, 0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
- */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers.
- All 1750 registers are one word long. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) 1
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-/* 1750A pc isn't overloaded on a register. */
-/* #define PC_REGNUM */
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 14
-
-/* Define this if successive args to a function occupy decreasing addresses
- on the stack.
- #define ARGS_GROW_DOWNWARD
-*/
-
-/* Register in which static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM 13
-
-/* Place in which caller passes the structure value address.
- 0 means push the value on the stack like an argument.
- #define STRUCT_VALUE 0
-*/
-
-/* Register in which address to store a structure value
- arrives in the function.
- #define STRUCT_VALUE_INCOMING 0
-*/
-
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM 12
-
-/* Define this to be 1 if all structure return values must be in memory. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/*****************************************************************************/
-
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
-/* 1750 note: The names (BASE_REGS/INDEX_REGS) are used in their *gcc sense*
- (i.e. *opposite* to the MIL-STD-1750A defined meanings). This means that
- R1..R15 are called "base" regs and R12..R15 are "index" regs.
- Index reg mode (in the gcc sense) is not yet implemented (these are the
- 1750 "Base with Index Reg" instructions, LBX etc. See 1750.md)
-
- Here's an example to drive this point home: in "LBX B12,R5"
- B12 shall be called the "index" reg and R5 shall be the "base" reg.
- This naming inversion is due to the GCC defined capabilities of
- "Base" vs. "Index" regs. */
-
-enum reg_class { NO_REGS, R2, R0_1, INDEX_REGS, BASE_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Since GENERAL_REGS is the same class as ALL_REGS,
- don't give it a different class number; just make it an alias. */
-#define GENERAL_REGS ALL_REGS
-
-/* Give names of register classes as strings for dump file. */
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", "R2", "R0_1", "INDEX_REGS", "BASE_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES.
- 1750 "index" (remember, in the *GCC* sense!) regs are R12 through R15.
- The only 1750 register not usable as BASE_REG is R0. */
-
-#define REG_CLASS_CONTENTS { {0}, {0x0004}, {0x0003}, {0xf000}, {0xfffe}, {0xffff} }
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-#define REGNO_REG_CLASS(REGNO) ((REGNO) == 2 ? R2 : (REGNO) == 0 ? R0_1 : \
- (REGNO) >= 12 ? INDEX_REGS : (REGNO) > 0 ? BASE_REGS : ALL_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-
-#define BASE_REG_CLASS BASE_REGS
-#define INDEX_REG_CLASS INDEX_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.
- For the 1750, we have 'z' for R0_1, 't' for R2, 'b' for gcc Base regs
- and 'x' for gcc Index regs. */
-
-#define REG_CLASS_FROM_LETTER(C) ((C) == 't' ? R2 : \
- (C) == 'z' ? R0_1 : \
- (C) == 'b' ? BASE_REGS : \
- (C) == 'x' ? INDEX_REGS : NO_REGS)
-
-/* The letters I,J,K,.. to P in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- For the 1750A,
- `I' is used for ISP mode instructions,
- `J' is used for ISN mode instructions,
- `K' is used for the STC instruction's constant range,
- `L' is used for unsigned 8-bit address displacements in instructions
- of addressing mode "Base Relative",
- `M' is for IM mode instructions et al.,
- `O' is a synonym for (const_int 0). */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 16 : \
- (C) == 'J' ? (VALUE) < 0 && (VALUE) >= -16 : \
- (C) == 'K' ? (VALUE) >= 0 && (VALUE) <= 15 : \
- (C) == 'L' ? (VALUE) >= 0 && (VALUE) <= 0xFF : \
- (C) == 'M' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
- (C) == 'O' ? (VALUE) == 0 : 0)
-
-/* Similar, but for floating constants, and defining letter 'G'.
- Here VALUE is the CONST_DOUBLE rtx itself. */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? ((VALUE) == CONST0_RTX (HFmode) \
- || (VALUE) == CONST0_RTX (TQFmode)) : 0)
-
-/* Optional extra constraints for this machine.
-
- For the 1750, `Q' means that this is a memory operand consisting
- of the sum of an Index Register (in the GCC sense, i.e. R12..R15)
- and a constant in the range 0..255. This constraint is used for
- the Base Register with Offset address mode instructions (LB,STB,AB,..) */
-
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'Q' && b_mode_operand (OP))
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS.
- On the 1750A, this is the size of MODE in words,
- since class doesn't make any difference. */
-#define CLASS_MAX_NREGS(CLASS,MODE) GET_MODE_SIZE(MODE)
-
-/*****************************************************************************/
-
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD 1
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- goes at a more negative offset in the frame.
- #define FRAME_GROWS_DOWNWARD
-*/
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated.
-*/
-#define STARTING_FRAME_OFFSET 1
-
-/* This is the default anyway:
- #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) FRAMEADDR
-*/
-
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by.
- 1750 note: what GCC calls a "byte" is really a 16-bit word,
- because BITS_PER_UNIT is 16. */
-
-#define PUSH_ROUNDING(BYTES) (BYTES)
-
-/* Define this macro if functions should assume that stack space has
- been allocated for arguments even when their values are passed in
- registers.
- Size, in bytes, of the area reserved for arguments passed in
- registers for the function represented by FNDECL.
- #define REG_PARM_STACK_SPACE(FNDECL) 14 */
-
-/* Define this if it is the responsibility of the caller to allocate
- the area reserved for arguments passed in registers.
- #define OUTGOING_REG_PARM_STACK_SPACE */
-
-/* Offset of first parameter from the argument pointer register value.
- 1750 note:
- Parameters appear in reversed order on the frame (so when they are
- popped, they come off in the normal left-to-right order.)
- Computed as follows:
- one word for the caller's (PC+1) (i.e. the return address)
- plus total size of called function's "auto" variables
- plus one word for the caller's frame pointer (i.e. the old FP) */
-
-#define FIRST_PARM_OFFSET(FNDECL) \
- (1 + get_frame_size() + 1)
-
-/* Value is 1 if returning from a function call automatically
- pops the arguments described by the number-of-args field in the call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
-*/
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-/* 1750 note: no libcalls yet */
-
-#define LIBCALL_VALUE(MODE) printf("LIBCALL_VALUE called!\n"), \
- gen_rtx_REG (MODE, 0)
-
-/* 1 if N is a possible register number for a function value. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* 1 if the tree TYPE should be returned in memory instead of in regs.
- #define RETURN_IN_MEMORY(TYPE) \
- (int_size_in_bytes(TYPE) > 12)
-*/
-
-/* Define this if PCC uses the nonreentrant convention for returning
- structure and union values.
- #define PCC_STATIC_STRUCT_RETURN */
-
-/* 1 if N is a possible register number for function argument passing. */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
-
-/*****************************************************************************/
-
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go.
-
- For 1750A, this is a single integer, which is a number of words
- of arguments scanned so far. */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0.
-
- For 1750A, the offset starts at 0. */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.)
-
- 1750 note: "int_size_in_bytes()" returns a unit relative to
- BITS_PER_UNIT, so in our case not bytes, but 16-bit words. */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- ((CUM) += (MODE) == BLKmode ? int_size_in_bytes(TYPE) : GET_MODE_SIZE(MODE))
-
-/* Define where to put the arguments to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis). */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) function_arg (CUM,MODE,TYPE,NAMED)
-
-/* Define the following macro if function calls on the target machine
- do not preserve any registers; in other words, if `CALL_USED_REGISTERS'
- has 1 for all registers. This macro enables `-fcaller-saves' by
- default. Eventually that option will be enabled by default on all
- machines and both the option and this macro will be eliminated. */
-
-#define DEFAULT_CALLER_SAVES
-
-/************* 1750: PROFILER HANDLING NOT YET DONE !!!!!!! *************/
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "; got into FUNCTION_PROFILER with label # %d\n", (LABELNO))
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 0
-
-/* If the memory address ADDR is relative to the frame pointer,
- correct it to be relative to the stack pointer instead.
- This is for when we don't use a frame pointer.
- ADDR should be a variable name.
-
- #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH)
-*/
-
-/* Store in the variable DEPTH the initial difference between the
- frame pointer reg contents and the stack pointer reg contents,
- as of the start of the function body. This depends on the layout
- of the fixed parts of the stack frame and on how registers are saved.
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) DEPTH = 0
-*/
-
-#define ELIMINABLE_REGS { \
- { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM } }
-
-#define CAN_ELIMINATE(FROM, TO) 1
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
- OFFSET = (TO == STACK_POINTER_REGNUM) ? -1 : 0
-
-
-/* Output assembler code for a block containing the constant parts
- of a trampoline, leaving space for the variable parts. */
-
-#define TRAMPOLINE_TEMPLATE(FILE) fprintf(FILE,"TRAMPOLINE_TEMPLATE called\n")
-
-/* Length in units of the trampoline for entering a nested function. */
-
-#define TRAMPOLINE_SIZE 2
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) printf("INITIALIZE_TRAMPO called\n")
-/* { \
- emit_move_insn (gen_rtx_MEM (QImode, plus_constant (TRAMP, 1)), CXT); \
- emit_move_insn (gen_rtx_MEM (QImode, plus_constant (TRAMP, 6)), FNADDR); \
-} */
-
-
-/*****************************************************************************/
-
-/* Addressing modes, and classification of registers for them. */
-
-/* 1750 doesn't have a lot of auto-incr./decr. - just for the stack ptr. */
-
-/* #define HAVE_POST_INCREMENT 0 just for R15 (stack pointer) */
-/* #define HAVE_POST_DECREMENT 0 */
-/* #define HAVE_PRE_DECREMENT 0 just for R15 (stack pointer) */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c.
- 1750 note: The words BASE and INDEX are used in their GCC senses:
- The "Index Registers", R12 through R15, are used in the 1750
- instructions LB,STB,AB,SBB,MB,DB,LBX,STBX,...
- */
-
-#define REGNO_OK_FOR_BASE_P(REGNO) \
- (((REGNO) > 0 && (REGNO) <= 15) || \
- (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] <= 15))
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
- (((REGNO) >= 12 && (REGNO) <= 15) || \
- (reg_renumber[REGNO] >= 12 && reg_renumber[REGNO] <= 15))
-
-/* Now macros that check whether X is a register and also,
- strictly, whether it is in a specified class. */
-
-/* 1 if X is an address register */
-
-#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
-
-/* Maximum number of registers that can appear in a valid memory address. */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
-#ifdef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P(REGNO(X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P(REGNO(X))
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) (REGNO (X) >= 12)
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) (REGNO (X) > 0)
-
-#endif
-
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
- The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.
-
- 1750 note: Currently we don't implement address expressions that use
- GCC "Index"-class regs. To be expanded to handle the 1750 "Base with Index"
- instructions (see also MAX_REGS_PER_ADDRESS and others). */
-
-#define GO_IF_BASED_ADDRESS(X, ADDR) { \
- if ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P(X))) \
- goto ADDR; \
- if (GET_CODE (X) == PLUS) \
- { register rtx x0 = XEXP(X,0), x1 = XEXP(X,1); \
- if ((REG_P(x0) && REG_OK_FOR_BASE_P(x0) && CONSTANT_ADDRESS_P(x1)) \
- || (REG_P(x1) && REG_OK_FOR_BASE_P(x1) && CONSTANT_ADDRESS_P(x0))) \
- goto ADDR; } }
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) { \
- if (CONSTANT_ADDRESS_P(X)) goto ADDR; \
- GO_IF_BASED_ADDRESS(X,ADDR) }
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for.
- On the 68000, only predecrement and postincrement address depend thus
- (the amount of decrement or increment being the length of the operand). */
-/* 1750: not used. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/*****************************************************************************/
-
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE QImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this as 1 if `char' should by default be signed; else as 0. */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
- in one reasonably fast instruction. */
-#define MOVE_MAX 65536
-
-/* If a memory-to-memory move would take MOVE_RATIO or more simple
- move-instruction pairs, we will do a movstr or libcall instead. */
-#define MOVE_RATIO 4
-
-/* Nonzero if access to memory by bytes is slow and undesirable. */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
- which implies one can omit a sign-extension or zero-extension
- of a shift count. */
-/* #define SHIFT_COUNT_TRUNCATED 1 */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
- and some other value for true. This is the value stored for true. */
-
-#define STORE_FLAG_VALUE 1
-
-/* When a prototype says `char' or `short', really pass an `int'.
- 1750: for now, `char' is 16 bits wide anyway. */
-#define PROMOTE_PROTOTYPES 0
-
-/* Specify the machine mode that pointers have.
- After generation of rtl, the compiler makes no further distinction
- between pointers and any other objects of this machine mode. */
-#define Pmode QImode
-
-/* A function address in a call instruction
- is a 16-bit address (for indexing purposes) */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST_INT: \
- return (INTVAL(RTX) >= -16 && INTVAL(RTX) <= 16) ? 1 : 3; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 3; \
- case CONST_DOUBLE: \
- return 4;
-
-#define ADDRESS_COST(ADDRESS) (memop_valid (ADDRESS) ? 3 : 10)
-
-#define REGISTER_MOVE_COST(MODE,FROM,TO) 2
-
-#define MEMORY_MOVE_COST(M,C,I) 4
-
-/* Tell final.c how to eliminate redundant test instructions. */
-
-/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). */
-/* MIL-STD-1750: none -- just has the garden variety C,P,Z,N flags. */
-
-/* Store in cc_status the expressions
- that the condition codes will describe
- after execution of an instruction whose pattern is EXP.
- Do not alter them if the instruction would not alter the cc's.
- 1750: See file out-1750a.c for notice_update_cc(). */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP)
-
-/**********************************************/
-/* Produce debugging info in the DWARF format
- #define DWARF_DEBUGGING_INFO
-*/
-
-/*****************************************************************************/
-
-/* Control the assembler format that we output. */
-
-/* Output at beginning of assembler file. */
-
-#define ASM_FILE_START(FILE) { \
- char *p2, name[40]; \
- const char *p; \
- if ((p = strrchr(main_input_filename,'/')) != NULL ? 1 : \
- (p = strrchr(main_input_filename,']')) != NULL) \
- p++; \
- else \
- p = main_input_filename; \
- strcpy(name,p); \
- if ((p2 = strchr(name,'.'))) \
- *p2 = '\0'; \
- fputs ("\tname ", FILE); \
- output_clean_symbol_name (FILE, name); \
- putc ('\n', FILE); \
- fprintf(FILE,"\tnolist\n\tinclude \"ms1750.inc\"\n\tlist\n\n"); \
- fprintf(FILE,"\tglobal\t__main\n\n"); }
-
-/* Output at end of assembler file.
- For 1750, we copy the data labels accrued in datalbl[] from the Constants
- section (Konst) to the Writable-Data section (Static). */
-
-#define ASM_FILE_END(FILE) \
- do { \
- if (datalbl_ndx >= 0) { \
- int i, cum_size=0; \
- fprintf(FILE,"\n\tstatic\ninit_srel\n"); \
- for (i = 0; i <= datalbl_ndx; i++) { \
- if (datalbl[i].name == NULL) \
- { \
- fprintf(stderr, "asm_file_end internal datalbl err\n"); \
- exit (0); \
- } \
- fprintf(FILE,"%s \tblock %d\n", \
- datalbl[i].name,datalbl[i].size); \
- cum_size += datalbl[i].size; \
- } \
- fprintf(FILE,"\n\tinit\n"); \
- fprintf(FILE,"\tlim\tr0,init_srel\n"); /* destin. */ \
- fprintf(FILE,"\tlim\tr1,%d\n",cum_size); /* count */ \
- fprintf(FILE,"\tlim\tr2,K%s\n",datalbl[0].name); /* source */ \
- fprintf(FILE,"\tmov\tr0,r2\n"); \
- fprintf(FILE,"\n\tnormal\n"); \
- datalbl_ndx = -1; /* reset stuff */ \
- for (i = 0; i < DATALBL_ARRSIZ; i++) \
- datalbl[i].size = 0; \
- } \
- fprintf(FILE,"\n\tend\n"); \
- } while (0)
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#define ASM_APP_ON "; ASM_APP_ON\n"
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#define ASM_APP_OFF "; ASM_APP_OFF\n"
-
-#define EXTRA_SECTION_FUNCTIONS \
- void check_section(sect) \
- enum section sect; \
- { \
- if (current_section != sect) { \
- fprintf(asm_out_file,"\t%s\n",sectname[(int)sect]); \
- current_section = sect; \
- } \
- switch (sect) { \
- case Init: \
- case Normal: \
- in_section = in_text; \
- break; \
- case Static: \
- in_section = in_data; \
- break; \
- case Konst: \
- in_section = in_readonly_data; \
- break; \
- } \
- }
-
-#define READONLY_DATA_SECTION_ASM_OP "\tkonst"
-
-/* Output before program init section */
-#define INIT_SECTION_ASM_OP "\n\tinit ; init_section\n"
-
-/* Output before program text section */
-#define TEXT_SECTION_ASM_OP "\n\tnormal ; text_section\n"
-
-/* Output before writable data.
- 1750 Note: This is actually read-only data. The copying from read-only
- to writable memory is done elsewhere (in ASM_FILE_END.)
- */
-#define DATA_SECTION_ASM_OP "\n\tkonst ; data_section\n"
-
-/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
-
-#define REGISTER_NAMES \
- { "0", "1", "2", "3", "4", "5", "6", "7", \
- "8", "9","10","11","12","13","14","15" }
-
-/****************** Assembler output formatting **********************/
-
-#define ASM_COMMENT_START ";"
-
-#define ASM_OUTPUT_OPCODE(FILE,PTR) do { \
- while (*(PTR) != '\0' && *(PTR) != ' ') { \
- putc (*(PTR), FILE); \
- (PTR)++; \
- } \
- while (*(PTR) == ' ') \
- (PTR)++; \
- putc ('\t', FILE); \
- program_counter += 2; \
- } while (0)
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
- fprintf(FILE,"%s\n",NAME)
-
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-/* 1750 note: Labels are prefixed with a 'K'. This is because handling
- has been changed for labels to be output in the "Constants" section
- (named "Konst"), and special initialization code takes care of copying
- the Const-section data into the writable data section (named "Static").
- In the Static section we therefore have the true label names (i.e.
- not prefixed with 'K'). */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { if (NAME[0] == '.') { \
- fprintf(stderr,"Oops! label %s can't begin with '.'\n",NAME); \
- abort(); \
- } \
- else { \
- check_section(Konst); \
- fprintf(FILE,"K%s\n",NAME); \
- fflush(FILE); \
- datalbl[++datalbl_ndx].name = (char *)xstrdup (NAME);\
- datalbl[datalbl_ndx].size = 0; \
- label_pending = 1; \
- } \
- } while (0)
-
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) do { \
- fprintf (FILE, "\tglobal %s\t; export\n", NAME); \
- } while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- do { \
- if (strcmp(PREFIX,"LC") == 0) { \
- label_pending = 1; \
- datalbl[++datalbl_ndx].name = (char *) xmalloc (9);\
- sprintf(datalbl[datalbl_ndx].name,"LC%d",NUM); \
- datalbl[datalbl_ndx].size = 0; \
- check_section(Konst); \
- fprintf(FILE,"K%s%d\n",PREFIX,NUM); \
- } \
- else if (find_jmplbl(NUM) < 0) { \
- jmplbl[++jmplbl_ndx].num = NUM; \
- jmplbl[jmplbl_ndx].pc = program_counter; \
- fprintf(FILE, "%s%d\n", PREFIX, NUM); \
- } \
- fflush(FILE); \
- } while (0)
-
-
-/* This is how to store into the string LABEL
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, "%s%d", PREFIX, NUM)
-
-/* Output at the end of a jump table.
- 1750: To be uncommented when we can put jump tables in Konst.
- #define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \
- fprintf (FILE, "\tnormal\t; case_end\n")
- */
-
-/* Currently, it is not possible to put jump tables in section Konst.
- This is because there is a one-to-one relation between sections Konst
- and Static (i.e., all Konst data are copied to Static, and the order
- of data is the same between the two sections.) However, jump tables are
- not copied to Static, which destroys the equivalence between Konst and
- Static. When a more intelligent Konst-to-Static copying mechanism is
- implemented (i.e. one that excludes the copying of jumptables), then
- ASM_OUTPUT_CASE_END shall be defined, and JUMP_LABELS_IN_TEXT_SECTION
- shall be undefined. */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* This is how to output an assembler line defining a string constant. */
-
-#define ASM_OUTPUT_ASCII(FILE, PTR, LEN) do { \
- int i; \
- if (label_pending) \
- label_pending = 0; \
- datalbl[datalbl_ndx].size += LEN; \
- for (i = 0; i < (int) LEN; i++) { \
- if ((i % 15) == 0) { \
- if (i != 0) \
- fprintf(FILE,"\n"); \
- fprintf(FILE,"\tdata\t"); \
- } \
- else \
- fprintf(FILE,","); \
- if (PTR[i] >= 32 && PTR[i] < 127) \
- fprintf(FILE,"'%c'",PTR[i]); \
- else \
- fprintf(FILE,"%d",PTR[i]); \
- } \
- fprintf(FILE,"\n"); \
- } while (0)
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tPSHM R%s,R%s\n", reg_names[REGNO], "FIXME: missing arg")
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tPOPM R%s,R%s\n", reg_names[REGNO], "FIXME: missing arg")
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- fprintf (FILE, "\tdata\tL%d ;addr_vec_elt\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative. */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\tdata\tL%d-L%d ;addr_diff_elt\n", VALUE,REL)
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- fprintf(FILE,"; in ASM_OUTPUT_ALIGN: pwr_of_2_bytcnt=%d\n",LOG)
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf(FILE,"; in ASM_OUTPUT_SKIP: size=%d\n",SIZE)
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) do { \
- check_section(Static); \
- fprintf (FILE, "\tcommon %s,%d\n", NAME, SIZE); \
- } while (0)
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) do { \
- fprintf (FILE, "\tglobal %s\t; import\n", NAME); \
- } while (0)
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) do { \
- check_section (Static); \
- fprintf(FILE,"%s \tblock %d\t; local common\n",NAME,SIZE); \
- } while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
- CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
- For `%' followed by punctuation, CODE is the punctuation and X is null.
- 1750 note: there are three special CODE characters:
- 'D', 'E': print a reference to a floating point constant (D=double,
- E=single precision) label name
- 'F': print a label defining a floating-point constant value
- 'J': print the absolute value of a negative INT_CONST
- (this is used in LISN/CISN/MISN/SISP and others)
- 'Q': print a 1750 Base-Register-with-offset instruction's operands
- */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE,X,CODE)
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE,ADDR)
-
-/* Convert a REAL_VALUE_TYPE to the target 1750a float format. */
-#define REAL_VALUE_TO_TARGET_SINGLE(IN, OUT) \
- ((OUT) = real_value_to_target_single(IN))
-
-/* Convert a REAL_VALUE_TYPE to the target 1750a extended float format. */
-#define REAL_VALUE_TO_TARGET_DOUBLE(IN, OUT) \
- real_value_to_target_double((IN), (OUT))
+++ /dev/null
-;;- Machine description for GNU compiler
-;;- MIL-STD-1750A version.
-;; Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999,
-;; 2000 Free Software Foundation, Inc.
-;; Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- instruction definitions
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- When naming insn's (operand 0 of define_insn) be careful about using
-;;- names from other targets machine descriptions.
-
-;; MIL-STD-1750 specific remarks:
-;;
-;; 1) BITS_PER_UNIT = 16
-;;
-;; 2) GCC to MIL-STD-1750 data type mappings:
-;; QImode => single integer (16 bits or 1 reg).
-;; HImode => double integer (32 bits or 2 regs).
-;; HFmode => single precision float (32 bits or 2 regs).
-;; TQFmode => extended precision float (48 bits or 3 regs).
-;;
-;; 3) Immediate integer operands Constraints:
-;; 'I' 1 .. 16
-;; 'J' -1 ..-16
-;; 'K' 0 .. 15
-;; 'L' 0 .. 255
-;; 'M' -32768 .. 32767
-;; 'O' => 0 (for optimizations and GCC quirks)
-;;
-;; Further notes:
-;;- Assembly output ending in ".M" are macros in file M1750.INC
-
-
-;; stackpush
-(define_insn ""
- [(set (match_operand:QI 0 "push_operand" "=<")
- (match_operand:QI 1 "general_operand" "r"))]
- ""
- "pshm r%1,r%1")
-
-(define_insn ""
- [(set (match_operand:HI 0 "push_operand" "=<")
- (match_operand:HI 1 "general_operand" "r"))]
- ""
- "pshm r%1,r%d1")
-
-(define_insn ""
- [(set (match_operand:HF 0 "push_operand" "=<")
- (match_operand:HF 1 "general_operand" "r"))]
- ""
- "pshm r%1,r%d1")
-
-(define_insn ""
- [(set (match_operand:TQF 0 "push_operand" "=<")
- (match_operand:TQF 1 "general_operand" "r"))]
- ""
- "pshm r%1,r%t1")
-
-;; stackpop
-(define_insn ""
- [(set (match_operand:QI 0 "general_operand" "=r")
- (match_operand:QI 1 "push_operand" ">"))]
- ""
- "popm r%1,r%1")
-
-(define_insn ""
- [(set (match_operand:HI 0 "general_operand" "=r")
- (match_operand:HI 1 "push_operand" ">"))]
- ""
- "popm r%1,r%d1")
-
-(define_insn ""
- [(set (match_operand:HF 0 "general_operand" "=r")
- (match_operand:HF 1 "push_operand" ">"))]
- ""
- "popm r%1,r%d1")
-
-(define_insn ""
- [(set (match_operand:TQF 0 "general_operand" "=r")
- (match_operand:TQF 1 "push_operand" ">"))]
- ""
- "popm r%1,r%t1")
-
-
-;; Test operations.
-
-(define_insn "tstqi"
- [(set (cc0)
- (match_operand:QI 0 "register_operand" "r"))]
- ""
- "lr r%0,r%0 ; from tstqi")
-
-(define_insn "tsthi"
- [(set (cc0)
- (match_operand:HI 0 "register_operand" "r"))]
- ""
- "dlr r%0,r%0 ; from tsthi")
-
-; With 1750A floats, testing the most significant word suffices.
-
-(define_insn "tsthf"
- [(set (cc0)
- (match_operand:HF 0 "register_operand" "r"))]
- ""
- "lr r%0,r%0 ; tsthf")
-
-(define_insn "tsttqf"
- [(set (cc0)
- (match_operand:TQF 0 "register_operand" "r"))]
- ""
- "lr r%0,r%0 ; tsttqf")
-
-
-;; block move.
-
-(define_insn "movstrqi"
- [(set (match_operand:BLK 0 "mov_memory_operand" "=m")
- (match_operand:BLK 1 "mov_memory_operand" "m"))
- (use (match_operand:QI 2 "general_operand" "r"))
- (match_operand 3 "" "")
- (clobber (match_dup 0))
- (clobber (match_dup 1))
- (clobber (match_dup 2))]
- ""
- "*
- {
- rtx regops[3];
-
- regops[0] = XEXP (operands[0], 0);
- regops[1] = XEXP (operands[1], 0);
- regops[2] = operands[2];
-
- return movcnt_regno_adjust (regops);
- } ")
-
-
-;; compare instructions.
-
-(define_insn "cmpqi"
- [(set (cc0)
- (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
- (match_operand:QI 1 "general_operand" "I,J,i,r,m")))]
- ""
- "*
- {
- if (next_cc_user_is_unsigned (insn))
- switch (which_alternative)
- {
- case 0:
- case 1:
- case 2:
- return \"ucim.m %0,%1\";
- case 3:
- return \"ucr.m %0,%1\";
- case 4:
- return \"uc.m %0,%1\";
- default:
- abort();
- }
- else
- switch (which_alternative)
- {
- case 0:
- return \"cisp r%0,%1\";
- case 1:
- return \"cisn r%0,%J1\";
- case 2:
- return \"cim r%0,%1\";
- case 3:
- return \"cr r%0,r%1\";
- case 4:
- return \"c r%0,%1\";
- default:
- abort();
- }
- } ")
-
-(define_insn "cmphi"
- [(set (cc0)
- (compare (match_operand:HI 0 "general_operand" "r,r")
- (match_operand:HI 1 "general_operand" "r,m")))]
- ""
- "*
- {
- if (next_cc_user_is_unsigned (insn))
- {
- if (which_alternative == 0)
- return \"ducr.m %0,%1\";
- return \"duc.m %0,%1\";
- }
- else
- {
- if (which_alternative == 0)
- return \"dcr r%0,r%1\";
- return \"dc r%0,%1\";
- }
- } ")
-
-(define_insn "cmphf"
- [(set (cc0)
- (compare (match_operand:HF 0 "general_operand" "r,r")
- (match_operand:HF 1 "general_operand" "r,m")))]
- ""
- "@
- fcr r%0,r%1
- fc r%0,%1 ")
-
-(define_insn "cmptqf"
- [(set (cc0)
- (compare (match_operand:TQF 0 "general_operand" "r,r")
- (match_operand:TQF 1 "general_operand" "r,m")))]
- ""
- "@
- efcr r%0,r%1
- efc r%0,%1 ")
-
-
-;; truncation instructions
-;;- 1750: any needed?
-
-(define_insn "trunchiqi2"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (truncate:QI (match_operand:HI 1 "register_operand" "r")))]
- ""
- "lr r%0,r%d1")
-
-
-;; zero extension instructions: not defined, GCC can synthesize
-
-;; sign extension instructions
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m")) )]
- ""
- "*
- if (which_alternative == 0)
- {
- if (REGNO (operands [0]) != REGNO (operands [1]))
- output_asm_insn (\"lr r%0,r%1\", operands);
- }
- else
- output_asm_insn (\"l r%0,%1\", operands);
- return \"dsra r%0,16 ;extendqihi2\";
- ")
-
-
-;; Conversions between float and double.
-
-; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
-(define_insn "extendhftqf2"
- [(set (match_operand:TQF 0 "register_operand" "=r,r")
- (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))]
- ""
- "*
- output_asm_insn(\"xorr r%t0,r%t0 ;extendhftqf2\", operands);
- if (which_alternative == 0)
- {
- if (REGNO (operands[1]) != REGNO (operands[0]))
- return \"dlr r%0,r%1\";
- else
- return \";\";
- }
- else
- return \"dl r%0,%1\";
- ")
-
-; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
-(define_insn "trunctqfhf2"
- [(set (match_operand:HF 0 "register_operand" "=r,r")
- (float_truncate:HF
- (match_operand:TQF 1 "general_operand" "r,m")))]
- ""
- "@
- dlr r%0,r%1 ;trunctqfhf2
- dl r%0,%1 ;trunctqfhf2 ")
-
-
-;; Conversion between fixed point and floating point.
-
-(define_insn "floatqihf2"
- [(set (match_operand:HF 0 "register_operand" "=r")
- (float:HF (match_operand:QI 1 "register_operand" "r")))]
- ""
- "flt r%0,r%1")
-
-(define_insn "floathitqf2"
- [(set (match_operand:TQF 0 "register_operand" "=r")
- (float:TQF (match_operand:HI 1 "register_operand" "r")))]
- ""
- "eflt r%0,r%1")
-
-
-;; Convert floats to ints
-
-(define_insn "fix_trunchfqi2"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
- ""
- "fix r%0,r%1")
-
-(define_insn "fix_trunctqfhi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
- ""
- "efix r%0,r%1")
-
-
-;; Move instructions
-
-;; We can't deal with normal byte-size characters, only with WIDE characters!
-;; This may appear as a serious restriction, but it also opens the doors
-;; for ISO 10646 :-)
-
-;; 16-bit moves
-
-; memory indirect to reg
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (mem:QI (match_operand 1 "memory_operand" "m")))]
- ""
- "li r%0,%1")
-
-; reg/const to memory indirect
-(define_insn ""
- [(set (mem:QI (match_operand 0 "memory_operand" "=m,m"))
- (match_operand:QI 1 "nonmemory_operand" "r,K"))]
- ""
- "@
- sti r%1,%0
- stci %1,%0")
-
-; general case
-(define_insn "movqi"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m")
- (match_operand:QI 1 "general_operand" "O,I,J,i,r,m,r,K"))]
- ""
- "@
- xorr r%0,r%0
- lisp r%0,%1
- lisn r%0,%J1
- lim r%0,%1
- lr r%0,r%1
- l r%0,%1
- st r%1,%0
- stc %1,%0 ")
-
-;; 32-bit moves
-
-; memory indirect to reg
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (mem:HI (match_operand 1 "memory_operand" "m")))]
- ""
- "dli r%0,%1")
-
-; reg to memory indirect
-(define_insn ""
- [(set (mem:HI (match_operand 0 "memory_operand" "=m"))
- (match_operand:HI 1 "register_operand" "r"))]
- ""
- "dsti r%1,%0")
-
-; general case
-(define_insn ""
- [(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m")
- (match_operand:HI 1 "general_operand" "O,I,J,r,m,r,K"))]
- ""
- "@
- xorr r%0,r%0\;xorr r%d0,r%d0
- xorr r%0,r%0\;lisp r%d0,%1
- lisn r%0,1 \;lisn r%d0,%J1
- dlr r%0,r%1
- dl r%0,%1
- dst r%1,%0
- stc 0,%0 \;stc %1,%A0 ")
-
-(define_expand "movhi"
- [(set (match_operand:HI 0 "general_operand" "=g")
- (match_operand:HI 1 "general_operand" "g"))]
- ""
- "
- {
- rtx op1 = operands[1];
- if (GET_CODE (operands[0]) == MEM)
- {
- if (GET_CODE (op1) == MEM
- || (GET_CODE (op1) == CONST_INT
- && (INTVAL (op1) < 0 || INTVAL (op1) > 15)))
- operands[1] = force_reg (HImode, operands[1]);
- }
- else if (GET_CODE (op1) == CONST_INT
- && (INTVAL (op1) < -16 || INTVAL (op1) > 16))
- operands[1] = force_const_mem (HImode, operands[1]);
- }")
-
-
-;; Single-Float moves
-
-(define_insn ""
- [(set (match_operand:HF 0 "general_operand" "=r,r,m,m")
- (match_operand:HF 1 "general_operand" "r,m,r,G"))]
- ""
- "@
- dlr r%0,r%1
- dl r%0,%1
- dst r%1,%0
- stc 0,%0 \;stc 0,%A0 ")
-
-(define_expand "movhf"
- [(set (match_operand:HF 0 "general_operand" "")
- (match_operand:HF 1 "general_operand" ""))]
- ""
- "
- {
- enum rtx_code op1code = GET_CODE (operands[1]);
- if (GET_CODE (operands[0]) == MEM)
- {
- if (op1code == MEM || (op1code == CONST_DOUBLE
- && !rtx_equal_p (operands[1], CONST0_RTX (HFmode))))
- operands[1] = force_reg (HFmode, operands[1]);
- }
- else if (op1code == CONST_DOUBLE)
- operands[1] = force_const_mem (HFmode, operands[1]);
- }")
-
-
-;; Longfloat moves
-
-(define_insn ""
- [(set (match_operand:TQF 0 "general_operand" "=r,r,m")
- (match_operand:TQF 1 "general_operand" "r,m,r"))]
- ""
- "@
- eflr.m %0,%1
- efl r%0,%1
- efst r%1,%0 ")
-
-(define_expand "movtqf"
- [(set (match_operand:TQF 0 "general_operand" "")
- (match_operand:TQF 1 "general_operand" ""))]
- ""
- "
- {
- enum rtx_code op1code = GET_CODE (operands[1]);
- if (GET_CODE (operands[0]) == MEM)
- {
- if (op1code == MEM || op1code == CONST_DOUBLE)
- operands[1] = force_reg (TQFmode, operands[1]);
- }
- else if (op1code == CONST_DOUBLE)
- operands[1] = force_const_mem (TQFmode, operands[1]);
- }")
-
-
-;; add instructions
-
-;; single integer
-
-(define_insn "addqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
- (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))]
- ""
- "*
- switch (which_alternative)
- {
- case 0:
- return \"aisp r%0,%2\";
- case 1:
- return \"sisp r%0,%J2\";
- case 2:
- if (INTVAL(operands[2]) < 0)
- return \"sim r%0,%J2\";
- else
- return \"aim r%0,%2\";
- case 3:
- return \"ar r%0,r%2\";
- case 4:
- return \"a r%0,%2\";
- case 5:
- return \"incm %2,%0\";
- case 6:
- return \"decm %J2,%0\";
- default:
- abort();
- } ")
-
-;; double integer
-(define_insn "addhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "r,m")))]
- ""
- "@
- dar r%0,r%2
- da r%0,%2 ")
-
-(define_insn "addhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,r")
- (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
- (match_operand:HF 2 "general_operand" "r,m")))]
- ""
- "@
- far r%0,r%2
- fa r%0,%2 ")
-
-(define_insn "addtqf3"
- [(set (match_operand:TQF 0 "register_operand" "=r,r")
- (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
- (match_operand:TQF 2 "general_operand" "r,m")))]
- ""
- "@
- efar r%0,r%2
- efa r%0,%2 ")
-
-
-;; subtract instructions
-
-;; single integer
-(define_insn "subqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
- (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "I,i,r,m,I")))]
- ""
- "@
- sisp r%0,%2
- sim r%0,%2
- sr r%0,r%2
- s r%0,%2
- decm %2,%0 ")
-
-;; double integer
-(define_insn "subhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (minus:HI (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:HI 2 "general_operand" "r,m")))]
- ""
- "@
- dsr r%0,r%2
- ds r%0,%2 ")
-
-(define_insn "subhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,r")
- (minus:HF (match_operand:HF 1 "register_operand" "0,0")
- (match_operand:HF 2 "general_operand" "r,m")))]
- ""
- "@
- fsr r%0,r%2
- fs r%0,%2 ")
-
-(define_insn "subtqf3"
- [(set (match_operand:TQF 0 "register_operand" "=r,r")
- (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
- (match_operand:TQF 2 "general_operand" "r,m")))]
- ""
- "@
- efsr r%0,r%2
- efs r%0,%2 ")
-
-
-;; multiply instructions
-
-(define_insn "mulqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
- (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "I,J,M,r,m")))]
- ""
- "@
- misp r%0,%2
- misn r%0,%J2
- msim r%0,%2
- msr r%0,r%2
- ms r%0,%2 ")
-
-
-; 32-bit product
-(define_insn "mulqihi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r")
- (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%r,r,r"))
- (sign_extend:HI (match_operand:QI 2 "general_operand" "r,m,i"))))]
- ""
- "*
- if (REGNO (operands[1]) != REGNO (operands[0]))
- output_asm_insn (\"lr r%0,r%1\", operands);
-
- switch (which_alternative)
- {
- case 0:
- return \"mr r%0,r%2\";
- case 1:
- return \"m r%0,%2\";
- case 2:
- return \"mim r%0,%2\";
- default:
- abort();
- }
- ")
-
-
-(define_insn "mulhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "r,m")))]
- ""
- "@
- dmr r%0,r%2
- dm r%0,%2 ")
-
-; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
-
-(define_insn "mulhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,r")
- (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
- (match_operand:HF 2 "general_operand" "r,m")))]
- ""
- "@
- fmr r%0,r%2
- fm r%0,%2 ")
-
-(define_insn "multqf3"
- [(set (match_operand:TQF 0 "register_operand" "=r,r")
- (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
- (match_operand:TQF 2 "general_operand" "r,m")))]
- ""
- "@
- efmr r%0,r%2
- efm r%0,%2 ")
-
-
-;; divide instructions
-;; The 1750 16bit integer division instructions deliver a 16-bit
-;; quotient and a 16-bit remainder, where the remainder is in the next higher
-;; register number above the quotient. For now, we haven't found a way
-;; to give the reload pass knowledge of this property. So we make do with
-;; whatever registers the allocator wants, and willy-nilly output a pair of
-;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
-;; A comment in the description of `divmodM4' suggests that one leave the divM3
-;; undefined when there is a divmodM4 available.
-
-(define_insn "divmodqi4"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
- (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "I,J,M,r,m")))
- (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
- (mod:QI (match_dup 1) (match_dup 2)))]
- ""
- "*
- {
- const char *istr;
- switch(which_alternative)
- {
- case 0:
- istr = \"disp\";
- break;
- case 1:
- {
- rtx new_opnds[4];
- new_opnds[0] = operands[0];
- new_opnds[1] = operands[1];
- new_opnds[2] = GEN_INT (-INTVAL(operands[2]));
- new_opnds[3] = operands[3];
- istr = \"disn\";
- return mod_regno_adjust (istr, new_opnds);
- }
- break;
- case 2:
- istr = \"dvim\";
- break;
- case 3:
- istr = \"dvr \";
- break;
- case 4:
- istr = \"dv \";
- break;
- default:
- abort();
- }
- return mod_regno_adjust (istr, operands);
- }")
-
-;; Division for other types is straightforward.
-
-(define_insn "divhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (div:HI (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:HI 2 "general_operand" "r,m")))]
- ""
- "@
- ddr r%0,r%2
- dd r%0,%2 ")
-
-(define_insn "divhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,r")
- (div:HF (match_operand:HF 1 "register_operand" "0,0")
- (match_operand:HF 2 "general_operand" "r,m")))]
- ""
- "@
- fdr r%0,r%2
- fd r%0,%2 ")
-
-(define_insn "divtqf3"
- [(set (match_operand:TQF 0 "register_operand" "=r,r")
- (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
- (match_operand:TQF 2 "general_operand" "r,m")))]
- ""
- "@
- efdr r%0,r%2
- efd r%0,%2 ")
-
-
-;; Other arithmetic instructions:
-
-;; Absolute value
-
-(define_insn "absqi2"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (abs:QI (match_operand:QI 1 "register_operand" "r")))]
- ""
- "abs r%0,r%1")
-
-(define_insn "abshi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (abs:HI (match_operand:HI 1 "register_operand" "r")))]
- ""
- "dabs r%0,r%1")
-
-(define_insn "abshf2"
- [(set (match_operand:HF 0 "register_operand" "=r")
- (abs:HF (match_operand:HF 1 "register_operand" "r")))]
- ""
- "fabs r%0,r%1")
-
-
-;; Negation
-
-(define_insn "negqi2"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (neg:QI (match_operand:QI 1 "register_operand" "r")))]
- ""
- "neg r%0,r%1")
-
-(define_insn "neghi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (neg:HI (match_operand:HI 1 "register_operand" "r")))]
- ""
- "dneg r%0,r%1")
-
-(define_insn "neghf2"
- [(set (match_operand:HF 0 "register_operand" "=r")
- (neg:HF (match_operand:HF 1 "register_operand" "r")))]
- ""
- "fneg r%0,r%1")
-
-; The 1750A does not have an extended float negate instruction, so simulate.
-(define_expand "negtqf2"
- [(set (match_operand:TQF 0 "register_operand" "=&r")
- (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
- ""
- "
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], CONST0_RTX (TQFmode)));
- emit_insn (gen_rtx_SET (VOIDmode, operands[0],
- gen_rtx_MINUS (TQFmode, operands[0], operands[1])));
- DONE;
- ")
-
-
-;; bit-logical instructions
-
-;; Set Bit
-(define_insn ""
- [(set (match_operand:QI 0 "general_operand" "=r,m")
- (ior:QI (match_operand:QI 1 "general_operand" "0,0")
- (match_operand:QI 2 "const_int_operand" "i,i")))]
- "one_bit_set_p (INTVAL (operands [2]))"
- "@
- sbr %b2,r%0
- sb %b2,%0")
-
-;; Reset Bit
-(define_insn ""
- [(set (match_operand:QI 0 "general_operand" "=r,m")
- (and:QI (match_operand:QI 1 "general_operand" "0,0")
- (match_operand:QI 2 "const_int_operand" "i,i")))]
- "one_bit_set_p ((~INTVAL (operands [2])) & 0xffff)"
- "@
- rbr %B2,r%0
- rb %B2,%0")
-
-;; Set Variable Bit
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ior:QI (match_operand:QI 1 "register_operand" "0")
- (lshiftrt:QI (const_int 32768)
- (match_operand:QI 2 "register_operand" "r"))))]
- ""
- "svbr r%2,%r0")
-
-;; Reset Variable Bit
-(define_insn ""
- [(set (match_operand:QI 0 "general_operand" "=r")
- (and:QI (match_operand:QI 1 "general_operand" "0")
- (not:QI (lshiftrt:QI (const_int 32768)
- (match_operand:QI 2 "register_operand" "r")))))]
- ""
- "rvbr r%2,%r0")
-
-
-;; AND
-
-(define_insn "andqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r")
- (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "M,r,m")))]
- ""
- "@
- andm r%0,%2
- andr r%0,r%2
- and r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "andhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (and:HI (match_operand:HI 1 "register_operand" "%0")
- (match_operand:HI 2 "register_operand" "r")))]
- ""
- "danr.m %0,%2")
-
-;; OR
-
-(define_insn "iorqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r")
- (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "M,r,m")))]
- ""
- "@
- orim r%0,%2
- orr r%0,r%2
- or r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "iorhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ior:HI (match_operand:HI 1 "register_operand" "%0")
- (match_operand:HI 2 "register_operand" "r")))]
- ""
- "dorr.m %0,%2")
-
-;; XOR
-
-(define_insn "xorqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r")
- (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "M,r,m")))]
- ""
- "@
- xorm r%0,%2
- xorr r%0,r%2
- xor r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "xorhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (xor:HI (match_operand:HI 1 "register_operand" "%0")
- (match_operand:HI 2 "register_operand" "r")))]
- ""
- "dxrr.m %0,%2")
-
-;; NAND
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r,r,r")
- (ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
- (not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
- ""
- "@
- nim r%0,%2
- nr r%0,r%2
- n r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
- (not:HI (match_operand:HI 2 "register_operand" "r"))))]
- ""
- "dnr.m %0,%2")
-
-;; NOT
-
-(define_insn "one_cmplqi2"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (not:QI (match_operand:QI 1 "register_operand" "0")))]
- ""
- "nr r%0,r%0")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "one_cmplhi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (not:HI (match_operand:HI 1 "register_operand" "0")))]
- ""
- "dnr.m %0,%0")
-
-
-;; Shift instructions
-
-; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
-(define_insn "ashlqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r")
- (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "I,r")))]
- ""
- "@
- sll r%0,%2
- slr r%0,r%2 ")
-
-(define_insn "ashlhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "L,r")))]
- "" ; the 'L' constraint is a slight imprecise...
- "*
- if (which_alternative == 1)
- return \"dslr r%0,r%2\";
- else if (INTVAL(operands[2]) <= 16)
- return \"dsll r%0,%2\";
- else
- {
- output_asm_insn (\"dsll r%0,16 ; ashlhi3 shiftcnt > 16\", operands);
- return \"sll r%0,%w2\";
- }
- ")
-
-
-;; Right shift by a variable shiftcount works by negating the shift count,
-;; then emitting a right shift with the shift count negated. This means
-;; that all actual shift counts in the RTL will be positive. This
-;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
-;; which isn't valid.
-(define_expand "lshrqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "g")))]
- ""
- "
-{
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
-}")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I")))]
- ""
- "srl r%0,%2")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
- (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
- ""
- "slr r%0,r%2 ")
-
-;; Same thing for HImode.
-
-(define_expand "lshrhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "g")))]
- ""
- "
- {
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
- }")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "L")))]
- ""
- "*
- if (INTVAL (operands[2]) <= 16)
- return \"dsrl r%0,%2\";
- output_asm_insn (\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\", operands);
- return \"srl r%d0,%w2\";
- ")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
- (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
- ""
- "dslr r%0,r%2 ")
-
-;; Same applies for arithmetic shift right.
-(define_expand "ashrqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "g")))]
- ""
- "
- {
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
- }")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "I")))]
- ""
- "sra r%0,%2")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
- (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
- ""
- "sar r%0,r%2 ")
-
-;; HImode arithmetic shift right.
-(define_expand "ashrhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "g")))]
- ""
- "
- {
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
- }")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "L")))]
- ""
- "*
- if (INTVAL (operands[2]) <= 16)
- return \"dsra r%0,%2\";
- output_asm_insn (\"dsra r%0,16 ; ashrhi3 shiftcount > 16\", operands);
- return \"sra r%d0,%w2\";
- ")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
- (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
- ""
- "dsar r%0,r%2 ")
-
-
-;; rotate instructions
-
-(define_insn "rotlqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r")
- (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "I,r")))]
- ""
- "@
- slc r%0,%2
- scr r%0,r%2 ")
-
-(define_insn "rotlhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "I,r")))]
- ""
- "@
- dslc r%0,%2
- dscr r%0,r%2 ")
-
-(define_insn "rotrqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (rotatert:QI (match_operand:QI 1 "register_operand" "0")
- (match_operand:QI 2 "register_operand" "r")))]
- ""
- "neg r%2,r%2\;scr r%0,r%2 ")
-
-(define_insn "rotrhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (rotatert:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "r")))]
- ""
- "neg r%2,r%2\;dscr r%0,r%2 ")
-
-
-
-;; Special cases of bit-field insns which we should
-;; recognize in preference to the general case.
-;; These handle aligned 8-bit and 16-bit fields,
-;; which can usually be done with move instructions.
-; 1750: t.b.d.
-;********************
-
-;; Bit field instructions, general cases.
-;; "o,d" constraint causes a nonoffsettable memref to match the "o"
-;; so that its address is reloaded.
-
-;; (define_insn "extv" ...
-
-;; (define_insn "extzv" ...
-
-;; (define_insn "insv" ...
-
-;; Now recognize bit field insns that operate on registers
-;; (or at least were intended to do so).
-;[unnamed only]
-
-;; Special patterns for optimizing bit-field instructions.
-;**************************************
-
-; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
-; [(set (match_operand:QI 0 "general_operand" "=d")
-; (leu (cc0) (const_int 0)))]
-; ""
-; "* cc_status = cc_prev_status;
-; return \"sls %0\"; ")
-
-
-;; Basic conditional jump instructions.
-
-(define_insn "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-
-; no unsigned branches available on 1750. But GCC still needs them, so faking:
-
-(define_insn "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jc gt,%l0 ; Warning: this should be an *unsigned* test!")
-
-(define_insn "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jc lt,%l0 ; Warning: this should be an *unsigned* test!")
-
-(define_insn "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jc ge,%l0 ; Warning: this should be an *unsigned* test!")
-
-(define_insn "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jc le,%l0 ; Warning: this should be an *unsigned* test!")
-
-
-;; Negated conditional jump instructions.
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
- ")
-
-
-;; Negated unsigned conditional jump instructions (faked for 1750).
-
-(define_insn ""
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-;; Tablejump
-;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
-(define_insn "tablejump"
- [(set (pc)
- (match_operand:QI 0 "register_operand" "b"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
- "jc 15,0,r%0 ; tablejump label_ref=%1")
-
-
-;; Unconditional jump
-(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
- ""
- "jc 15,%0")
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-(define_insn "call_value"
- [(set (match_operand 0 "register_operand" "=r")
- (call (match_operand:QI 1 "memory_operand" "m")
- (match_operand:QI 2 "general_operand" "g")))]
- ;; Operand 2 not really used for 1750.
- ""
- "sjs r15,%1 ; return value in R0")
-
-;; Call subroutine with no return value.
-
-;; Operand 1 not really used in MIL-STD-1750.
-(define_insn ""
- [(call (match_operand:QI 0 "memory_operand" "mp")
- (match_operand:QI 1 "general_operand" ""))]
- ""
- "sjs r15,%0 ; no return value")
-
-;;;;;;;;;;;; 1750: NOT READY YET.
-(define_insn "call"
- [(call (match_operand:QI 0 "" "")
- (match_operand:QI 1 "" ""))]
- ""
- "ANYCALL %0")
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
- ""
- "jci 15,%0")
-
-(define_insn "nop"
- [(const_int 0)]
- ""
- "nop")
-
-
-;; Subtract One and Jump (if non-zero)
-(define_peephole
- [(set (match_operand:QI 0 "register_operand" "=r")
- (plus:QI (match_operand:QI 1 "register_operand" "%0")
- (match_operand:QI 2 "immediate_operand" "J")))
- (set (cc0) (match_dup 0))
- (set (pc)
- (if_then_else (ne (cc0) (const_int 0))
- (label_ref (match_operand 3 "" ""))
- (pc)))
- ]
- "INTVAL(operands[2]) == -1"
- "soj r%0,%3")
-
-;; Combine a Load Register with subsequent increment/decrement into a LIM
-(define_peephole
- [(set (match_operand:QI 0 "register_operand" "=r")
- (match_operand:QI 1 "register_operand" "b"))
- (set (match_dup 0)
- (plus:QI (match_dup 0)
- (match_operand:QI 2 "immediate_operand" "i")))]
- "REGNO(operands[1]) > 0"
- "lim r%0,%2,r%1 ; LR,inc/dec peephole")
-
-;; Eliminate the redundant load in a store/load sequence
-(define_peephole
- [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r")
- (match_operand:QI 1 "immediate_operand" "i")))
- (match_operand:QI 2 "register_operand" "r"))
- (set (match_operand:QI 3 "register_operand" "=r")
- (mem:QI (plus:QI (match_dup 0)
- (match_dup 1))))
- ]
- "REGNO(operands[2]) == REGNO(operands[3])"
- "st r%2,%1,r%0 ; eliminated previous redundant load")
-
-;;;End.
+++ /dev/null
-;; GCC assembler includefile for AS1750
-;;
-;; Macros defined:
-;; EFLR.M #d,#s Load the three regs starting at R#s to R#d following.
-;; RET.M #fs Return from function (uses the framesize #fs)
-
-
-UC SET 15
-
-; Return from function ; parameter: framesize
- MACRO RET.M
- IF `1` > 0
- IF `1` <= 16
- AISP R14,`1`
- ELSE
- AIM R14,`1`
- ENDIF
- ENDIF
- LR R15,R14
- URS R15
- ENDMACRO
-
-; Useful instructions missing from the 1750A standard:
-
-; Extended Float Load from Registers
- MACRO EFLR.M ; args : #1=dest-regno, #2=source-regno
-ONE SET `1` + 2
-TWO SET `2` + 2
- IF `1` >= `2` || `1`+2 < `2`
- LR R`ONE`,R`TWO`
- DLR R`1`,R`2`
- ELSE
- DLR R`1`,R`2`
- LR R`ONE`,R`TWO`
- DLR R`1`,R`1` ; Just to update condition codes
- ENDIF
- ENDMACRO
-
-; The following leave the condition codes haywire. But that is
-; accounted for (see notice_update_cc in config/1750a.c.)
-
-; Double ANd Register with Register
- MACRO DANR.M
-ONE SET `1` + 1
-TWO SET `2` + 1
- ANDR R`1`,R`2`
- ANDR R`ONE`,R`TWO`
- ENDMACRO
-
-; Double OR Register with Register
- MACRO DORR.M
-ONE SET `1` + 1
-TWO SET `2` + 1
- ORR R`1`,R`2`
- ORR R`ONE`,R`TWO`
- ENDMACRO
-
-; Double eXoR Register with Register
- MACRO DXRR.M
-ONE SET `1` + 1
-TWO SET `2` + 1
- XORR R`1`,R`2`
- XORR R`ONE`,R`TWO`
- ENDMACRO
-
-; Double Nand Register with register
- MACRO DNR.M
-ONE SET `1` + 1
-TWO SET `2` + 1
- NR R`1`,R`2`
- NR R`ONE`,R`TWO`
- ENDMACRO
-
-; Unsigned Compare Immediate
-
- MACRO UCIM.M
-LAST SET `1` + 3
- PSHM R`1`,R`LAST`
-LO SET `1` + 1
- LR R`LO`,R`1`
- XORR R`1`,R`1`
-HI SET `1` + 2
- XORR R`HI`,R`HI`
- LIM R`LAST`,`2`
- DCR R`1`,R`HI`
- POPM R`1`,R`LAST`
- ENDMACRO
-
-
-; Unsigned Compare Register with register
-
- MACRO UCR.M
- PSHM R10,R13 ; R12 and R13 are assumed not to be input parameters
- LR R13,R`2`
- LR R11,R`1`
- XORR R12,R12
- XORR R10,R10
- DCR R10,R12
- POPM R10,R13
- ENDMACRO
-
-
-; Unsigned Compare register with memory
-
- MACRO UC.M
- PSHM R10,R13
- L R13,`2`
- LR R11,R`1`
- XORR R12,R12
- XORR R10,R10
- DCR R10,R12
- POPM R10,R13
- ENDMACRO
-
-
-; Double Unsigned Compare Register with register
-
- MACRO DUCR.M
- PSHM R13,R14 ; R13 and R14 are assumed not to be input parameters
-LOW1 SET `1` + 1
-LOW2 SET `2` + 1
- PSHM R`1`,R`LOW1`
- PSHM R`2`,R`LOW2`
- LR R13,R`LOW1`
- LR R14,R`LOW2`
- DSRL R`1`,1
- DSRL R`2`,1
- DCR R`1`,R`2`
- BNE +6
- ANDM R13,1
- ANDM R14,1
- CR R13,R14
- POPM R`2`,R`LOW2`
- POPM R`1`,R`LOW1`
- POPM R13,R14
- ENDMACRO
-
-
-; Double Unsigned Compare register with memory
-
- MACRO DUC.M
- PSHM R13,R14 ; R13 and R14 are assumed not to be input parameters
-LOW1 SET `1` + 1
- PSHM R`1`,R`LOW1`
- DL R13,`2`
- DSRL R`1`,1
- DSRL R13,1
- DCR R`1`,R13
- BNE +10 ; done, go pop the saved regs
- DL R13,`2` ; interested in the *low* word (R14)
- L R13,1,R15
- ANDM R13,1
- ANDM R14,1
- CR R13,R14
- POPM R`1`,R`LOW1`
- POPM R13,R14
- ENDMACRO
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU.
- Copyright (C) 2000 Free Software Foundation, Inc.
- Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifdef RTX_CODE
-/* This function is used to get the address of an object. */
-extern struct rtx_def *a29k_get_reloaded_address PARAMS ((rtx));
-extern int gpc_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int long_const_operand PARAMS ((rtx, enum machine_mode));
-extern int cint_8_operand PARAMS ((rtx, enum machine_mode));
-extern int cint_16_operand PARAMS ((rtx, enum machine_mode));
-extern int const_0_operand PARAMS ((rtx, enum machine_mode));
-extern int const_8_operand PARAMS ((rtx, enum machine_mode));
-extern int const_16_operand PARAMS ((rtx, enum machine_mode));
-extern int const_24_operand PARAMS ((rtx, enum machine_mode));
-extern int float_const_operand PARAMS ((rtx, enum machine_mode));
-extern int gpc_reg_or_float_constant_operand PARAMS ((rtx, enum machine_mode));
-extern int gpc_reg_or_integer_constant_operand PARAMS ((rtx, enum machine_mode));
-extern int spec_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int accum_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int srcb_operand PARAMS ((rtx, enum machine_mode));
-extern int cmplsrcb_operand PARAMS ((rtx, enum machine_mode));
-extern int gpc_reg_or_immediate_operand PARAMS ((rtx, enum machine_mode));
-extern int and_operand PARAMS ((rtx, enum machine_mode));
-extern int add_operand PARAMS ((rtx, enum machine_mode));
-extern int call_operand PARAMS ((rtx, enum machine_mode));
-extern int in_operand PARAMS ((rtx, enum machine_mode));
-extern int out_operand PARAMS ((rtx, enum machine_mode));
-extern int reload_memory_operand PARAMS ((rtx, enum machine_mode));
-extern void a29k_set_memflags PARAMS ((rtx, rtx));
-extern int fp_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern int branch_operator PARAMS ((rtx, enum machine_mode));
-extern int load_multiple_operation PARAMS ((rtx, enum machine_mode));
-extern int store_multiple_operation PARAMS ((rtx, enum machine_mode));
-extern int masks_bits_for_special PARAMS ((rtx, rtx));
-extern int epilogue_operand PARAMS ((rtx, enum machine_mode));
-extern enum reg_class secondary_reload_class PARAMS ((enum reg_class,
- enum machine_mode, rtx));
-extern int incoming_reg PARAMS ((int, int));
-extern void a29k_clobbers_to PARAMS ((rtx, rtx));
-extern int needs_regstack_p PARAMS ((void));
-extern int uses_local_reg_p PARAMS ((rtx));
-extern int null_epilogue PARAMS ((void));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern void a29k_compute_reg_names PARAMS ((void));
-#endif /* RTX_CODE */
-
-extern void literal_section PARAMS ((void));
+++ /dev/null
-/* Subroutines used for code generation on AMD Am29000.
- Copyright (C) 1987, 1988, 1990, 1991, 1992, 1993, 1994, 1995, 1997, 1998,
- 1999, 2000 Free Software
- Foundation, Inc.
- Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "tree.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "function.h"
-#include "expr.h"
-#include "obstack.h"
-#include "reload.h"
-#include "tm_p.h"
-#include "target.h"
-#include "target-def.h"
-
-static int shift_constant_operand PARAMS ((rtx, enum machine_mode, int));
-static void a29k_set_memflags_1 PARAMS ((rtx, int, int, int, int));
-static void compute_regstack_size PARAMS ((void));
-static void check_epilogue_internal_label PARAMS ((FILE *));
-static void output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void a29k_asm_named_section PARAMS ((const char *, unsigned int));
-static int a29k_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static void a29k_encode_section_info PARAMS ((tree, int));
-
-#define min(A,B) ((A) < (B) ? (A) : (B))
-
-/* This gives the size in words of the register stack for the current
- procedure. */
-
-static int a29k_regstack_size;
-
-/* True if the current procedure has a call instruction. */
-
-static int a29k_makes_calls;
-
-/* This points to the last insn of the insn prologue. It is set when
- an insn without a filled delay slot is found near the start of the
- function. */
-
-static char *a29k_last_prologue_insn;
-
-/* This points to the first insn that will be in the epilogue. It is null if
- no epilogue is required. */
-
-static char *a29k_first_epilogue_insn;
-
-/* This is nonzero if a a29k_first_epilogue_insn was put in a delay slot. It
- indicates that an intermediate label needs to be written. */
-
-static int a29k_first_epilogue_insn_used;
-
-/* Location to hold the name of the current function. We need this prolog to
- contain the tag words prior to the declaration. So the name must be stored
- away. */
-
-const char *a29k_function_name;
-
-/* Mapping of registers to debug register numbers. The only change is
- for the frame pointer and the register numbers used for the incoming
- arguments. */
-
-int a29k_debug_reg_map[FIRST_PSEUDO_REGISTER];
-
-/* Save information from a "cmpxx" operation until the branch or scc is
- emitted. */
-
-rtx a29k_compare_op0, a29k_compare_op1;
-int a29k_compare_fp_p;
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
-#undef TARGET_ASM_ALIGNED_SI_OP
-#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
-
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE output_function_epilogue
-#undef TARGET_SCHED_ADJUST_COST
-#define TARGET_SCHED_ADJUST_COST a29k_adjust_cost
-#undef TARGET_ENCODE_SECTION_INFO
-#define TARGET_ENCODE_SECTION_INFO a29k_encode_section_info
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* Returns 1 if OP is a 8-bit constant. */
-
-int
-cint_8_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffffff00) == 0;
-}
-
-/* Returns 1 if OP is a 16-bit constant. */
-
-int
-cint_16_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0;
-}
-
-/* Returns 1 if OP is a constant that cannot be moved in a single insn. */
-
-int
-long_const_operand (op, mode)
- register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- if (! CONSTANT_P (op))
- return 0;
-
- if (TARGET_29050 && GET_CODE (op) == CONST_INT
- && (INTVAL (op) & 0xffff) == 0)
- return 0;
-
- return (GET_CODE (op) != CONST_INT
- || ((INTVAL (op) & 0xffff0000) != 0
- && (INTVAL (op) & 0xffff0000) != 0xffff0000
- && INTVAL (op) != 0x80000000));
-}
-\f
-/* The following four functions detect constants of 0, 8, 16, and 24 used as
- a position in ZERO_EXTRACT operations. They can either be the appropriate
- constant integer or a shift (which will be produced by combine). */
-
-static int
-shift_constant_operand (op, mode, val)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
- int val;
-{
- return ((GET_CODE (op) == CONST_INT && INTVAL (op) == val)
- || (GET_CODE (op) == ASHIFT
- && GET_CODE (XEXP (op, 0)) == CONST_INT
- && INTVAL (XEXP (op, 0)) == val / 8
- && GET_CODE (XEXP (op, 1)) == CONST_INT
- && INTVAL (XEXP (op, 1)) == 3));
-}
-
-int
-const_0_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return shift_constant_operand (op, mode, 0);
-}
-
-int
-const_8_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return shift_constant_operand (op, mode, 8);
-}
-
-int
-const_16_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return shift_constant_operand (op, mode, 16);
-}
-
-int
-const_24_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return shift_constant_operand (op, mode, 24);
-}
-
-/* Returns 1 if OP is a floating-point constant of the proper mode. */
-
-int
-float_const_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == mode;
-}
-
-/* Returns 1 if OP is a floating-point constant of the proper mode or a
- general-purpose register. */
-
-int
-gpc_reg_or_float_constant_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return float_const_operand (op, mode) || gpc_reg_operand (op, mode);
-}
-
-/* Returns 1 if OP is an integer constant of the proper mode or a
- general-purpose register. */
-
-int
-gpc_reg_or_integer_constant_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return ((GET_MODE (op) == VOIDmode
- && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE))
- || gpc_reg_operand (op, mode));
-}
-\f
-/* Returns 1 if OP is a special machine register. */
-
-int
-spec_reg_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) != REG || GET_MODE (op) != mode)
- return 0;
-
- switch (GET_MODE_CLASS (mode))
- {
- case MODE_PARTIAL_INT:
- return REGNO (op) >= R_BP && REGNO (op) <= R_CR;
- case MODE_INT:
- return REGNO (op) >= R_Q && REGNO (op) <= R_EXO;
- default:
- return 0;
- }
-}
-
-/* Returns 1 if OP is an accumulator register. */
-
-int
-accum_reg_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return (GET_CODE (op) == REG
- && REGNO (op) >= R_ACU (0) && REGNO (op) <= R_ACU (3));
-}
-
-/* Returns 1 if OP is a normal data register. */
-
-int
-gpc_reg_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- int regno;
-
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- if (GET_CODE (op) == REG)
- regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
- {
- if (REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
- regno = subreg_regno (op);
- else
- regno = REGNO (SUBREG_REG (op));
- }
- else
- return 0;
-
- return (regno >= FIRST_PSEUDO_REGISTER || regno < R_BP
- || (regno >= R_KR (0) && regno <= R_KR (31)));
-}
-
-/* Returns 1 if OP is either an 8-bit constant integer or a general register.
- If a register, it must be in the proper mode unless MODE is VOIDmode. */
-
-int
-srcb_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) == CONST_INT
- && (mode == QImode
- || (INTVAL (op) & 0xffffff00) == 0))
- return 1;
-
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- return gpc_reg_operand (op, mode);
-}
-
-int
-cmplsrcb_operand (op, mode)
- register rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) == CONST_INT
- && (mode == QImode
- || (INTVAL (op) & 0xffffff00) == 0xffffff00))
- return 1;
-
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- return gpc_reg_operand (op, mode);
-}
-
-/* Return 1 if OP is either an immediate or a general register. This is used
- for the input operand of mtsr/mtrsim. */
-
-int
-gpc_reg_or_immediate_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return gpc_reg_operand (op, mode) || immediate_operand (op, mode);
-}
-
-/* Return 1 if OP can be used as the second operand of and AND insn. This
- includes srcb_operand and a constant whose complement fits in 8 bits. */
-
-int
-and_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (srcb_operand (op, mode)
- || (GET_CODE (op) == CONST_INT
- && ((unsigned) ((~ INTVAL (op)) & GET_MODE_MASK (mode)) < 256)));
-}
-
-/* Return 1 if OP can be used as the second operand of an ADD insn.
- This is the same as above, except we use negative, rather than
- complement. */
-
-int
-add_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (srcb_operand (op, mode)
- || (GET_CODE (op) == CONST_INT
- && ((unsigned) ((- INTVAL (op)) & GET_MODE_MASK (mode)) < 256)));
-}
-
-/* Return 1 if OP is a valid address in a CALL_INSN. These are a SYMBOL_REF
- to the current function, all SYMBOL_REFs if TARGET_SMALL_MEMORY, or
- a sufficiently-small constant. */
-
-int
-call_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- switch (GET_CODE (op))
- {
- case SYMBOL_REF:
- return (TARGET_SMALL_MEMORY
- || (! TARGET_LARGE_MEMORY
- && ((GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FLAG (op))
- || ! strcmp (XSTR (op, 0), current_function_name))));
-
- case CONST_INT:
- return (unsigned HOST_WIDE_INT) INTVAL (op) < 0x40000;
-
- default:
- return 0;
- }
-}
-\f
-/* Return 1 if OP can be used as the input operand for a move insn. */
-
-int
-in_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- if (! general_operand (op, mode))
- return 0;
-
- while (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- switch (GET_CODE (op))
- {
- case REG:
- return 1;
-
- case MEM:
- return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE);
-
- case CONST_INT:
- if (GET_MODE_CLASS (mode) != MODE_INT
- && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
- return 0;
-
- return 1;
-
- case CONST:
- case SYMBOL_REF:
- case LABEL_REF:
- return (GET_MODE (op) == mode
- || mode == SImode || mode == HImode || mode == QImode);
-
- case CONST_DOUBLE:
- return ((GET_MODE_CLASS (mode) == MODE_FLOAT
- && mode == GET_MODE (op))
- || (GET_MODE (op) == VOIDmode
- && GET_MODE_CLASS (mode) == MODE_INT));
-
- default:
- return 0;
- }
-}
-
-/* Return 1 if OP can be used as the output operand for a move insn. */
-
-int
-out_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- rtx orig_op = op;
-
- if (! general_operand (op, mode))
- return 0;
-
- while (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- if (GET_CODE (op) == REG)
- return (gpc_reg_operand (orig_op, mode)
- || spec_reg_operand (orig_op, mode)
- || (GET_MODE_CLASS (mode) == MODE_FLOAT
- && accum_reg_operand (orig_op, mode)));
-
- else if (GET_CODE (op) == MEM)
- return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE);
- else
- return 0;
-}
-
-/* Return 1 if OP is an item in memory, given that we are in reload. */
-
-int
-reload_memory_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- int regno = true_regnum (op);
-
- return (! CONSTANT_P (op)
- && (regno == -1
- || (GET_CODE (op) == REG
- && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
-}
-
-/* Given an object for which reload_memory_operand is true, return the address
- of the operand, taking into account anything that reload may do. */
-
-rtx
-a29k_get_reloaded_address (op)
- rtx op;
-{
- if (GET_CODE (op) == SUBREG)
- {
- if (SUBREG_BYTE (op) != 0)
- abort ();
-
- op = SUBREG_REG (op);
- }
-
- if (GET_CODE (op) == REG)
- op = reg_equiv_mem[REGNO (op)];
-
- return find_replacement (&XEXP (op, 0));
-}
-\f
-/* Subfunction of the following function. Update the flags of any MEM
- found in part of X. */
-
-static void
-a29k_set_memflags_1 (x, in_struct_p, scalar_p, volatile_p, unchanging_p)
- rtx x;
- int in_struct_p, scalar_p, volatile_p, unchanging_p;
-{
- int i;
-
- switch (GET_CODE (x))
- {
- case SEQUENCE:
- case PARALLEL:
- for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
- a29k_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, scalar_p,
- volatile_p, unchanging_p);
- break;
-
- case INSN:
- a29k_set_memflags_1 (PATTERN (x), in_struct_p, scalar_p, volatile_p,
- unchanging_p);
- break;
-
- case SET:
- a29k_set_memflags_1 (SET_DEST (x), in_struct_p, scalar_p, volatile_p,
- unchanging_p);
- a29k_set_memflags_1 (SET_SRC (x), in_struct_p, scalar_p, volatile_p,
- unchanging_p);
- break;
-
- case MEM:
- MEM_IN_STRUCT_P (x) = in_struct_p;
- MEM_SCALAR_P (x) = scalar_p;
- MEM_VOLATILE_P (x) = volatile_p;
- RTX_UNCHANGING_P (x) = unchanging_p;
- break;
-
- default:
- break;
- }
-}
-
-/* Given INSN, which is either an INSN or a SEQUENCE generated to
- perform a memory operation, look for any MEMs in either a SET_DEST or
- a SET_SRC and copy the in-struct, unchanging, and volatile flags from
- REF into each of the MEMs found. If REF is not a MEM, don't do
- anything. */
-
-void
-a29k_set_memflags (insn, ref)
- rtx insn;
- rtx ref;
-{
- /* Note that it is always safe to get these flags, though they won't
- be what we think if REF is not a MEM. */
- int in_struct_p = MEM_IN_STRUCT_P (ref);
- int scalar_p = MEM_SCALAR_P (ref);
- int volatile_p = MEM_VOLATILE_P (ref);
- int unchanging_p = RTX_UNCHANGING_P (ref);
-
- if (GET_CODE (ref) != MEM
- || (! in_struct_p && ! volatile_p && ! unchanging_p))
- return;
-
- a29k_set_memflags_1 (insn, in_struct_p, scalar_p, volatile_p, unchanging_p);
-}
-\f
-/* Return 1 if OP is a comparison operator that we have in floating-point. */
-
-int
-fp_comparison_operator (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return ((mode == VOIDmode || mode == GET_MODE (op))
- && (GET_CODE (op) == EQ || GET_CODE (op) == GT ||
- GET_CODE (op) == GE));
-}
-
-/* Return 1 if OP is a valid branch comparison. */
-
-int
-branch_operator (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return ((mode == VOIDmode || mode == GET_MODE (op))
- && (GET_CODE (op) == GE || GET_CODE (op) == LT));
-}
-\f
-/* Return 1 if OP is a load multiple operation. It is known to be a
- PARALLEL and the first three sections will be tested. */
-
-int
-load_multiple_operation (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- int count = XVECLEN (op, 0) - 2;
- int dest_regno;
- rtx src_addr;
- int i;
-
- /* Perform a quick check so we don't blow up below. */
- if (count <= 1
- || GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
- return 0;
-
- dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
- src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
-
- for (i = 1; i < count; i++)
- {
- rtx elt = XVECEXP (op, 0, i + 2);
-
- if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
- || GET_MODE (SET_DEST (elt)) != SImode
- || REGNO (SET_DEST (elt)) != dest_regno + i
- || GET_CODE (SET_SRC (elt)) != MEM
- || GET_MODE (SET_SRC (elt)) != SImode
- || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
- || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
- || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
- || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
- return 0;
- }
-
- return 1;
-}
-
-/* Similar, but tests for store multiple. */
-
-int
-store_multiple_operation (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- int num_special = TARGET_NO_STOREM_BUG ? 2 : 1;
- int count = XVECLEN (op, 0) - num_special;
- int src_regno;
- rtx dest_addr;
- int i;
-
- /* Perform a quick check so we don't blow up below. */
- if (count <= 1
- || GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
- return 0;
-
- src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
- dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
-
- for (i = 1; i < count; i++)
- {
- rtx elt = XVECEXP (op, 0, i + num_special);
-
- if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
- || GET_MODE (SET_SRC (elt)) != SImode
- || REGNO (SET_SRC (elt)) != src_regno + i
- || GET_CODE (SET_DEST (elt)) != MEM
- || GET_MODE (SET_DEST (elt)) != SImode
- || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
- || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
- || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
- || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
- return 0;
- }
-
- return 1;
-}
-\f
-/* Given a special register REG and MASK, a value being masked against a
- quantity to which the special register is set, return 1 if the masking
- operation is built-in to the setting of that special register. */
-
-int
-masks_bits_for_special (reg, mask)
- rtx reg;
- rtx mask;
-{
- int needed_mask_value;
-
- if (GET_CODE (reg) != REG || GET_CODE (mask) != CONST_INT)
- abort ();
-
- switch (REGNO (reg))
- {
- case R_BP:
- case R_INT:
- needed_mask_value = 3;
- break;
-
- case R_FC:
- needed_mask_value = 31;
- break;
-
- case R_CR:
- case R_LRU:
- needed_mask_value = 255;
- break;
-
- case R_FPE:
- needed_mask_value = 511;
- break;
-
- case R_MMU:
- needed_mask_value = 0x3ff;
- break;
-
- case R_OPS:
- case R_CPS:
- case R_RBP:
- case R_FPS:
- needed_mask_value = 0xffff;
- break;
-
- case R_VAB:
- needed_mask_value = 0xffff0000;
- break;
-
- case R_Q:
- case R_CFG:
- case R_CHA:
- case R_CHD:
- case R_CHC:
- case R_TMC:
- case R_TMR:
- case R_PC0:
- case R_PC1:
- case R_PC2:
- return 0;
-
- default:
- abort ();
- }
-
- return (INTVAL (mask) & ~ needed_mask_value) == 0;
-}
-\f
-/* Return nonzero if this label is that of the return point, but there is
- a non-null epilogue. */
-
-int
-epilogue_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return next_active_insn (op) == 0 && a29k_first_epilogue_insn != 0;
-}
-\f
-/* Return the register class of a scratch register needed to copy IN into
- or out of a register in CLASS in MODE. If it can be done directly,
- NO_REGS is returned. */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
- enum reg_class class;
- enum machine_mode mode;
- rtx in;
-{
- int regno = -1;
- enum rtx_code code = GET_CODE (in);
-
- if (! CONSTANT_P (in))
- {
- regno = true_regnum (in);
-
- /* A pseudo is the same as memory. */
- if (regno == -1 || regno >= FIRST_PSEUDO_REGISTER)
- code = MEM;
- }
-
- /* If we are transferring between memory and a multi-word mode, we need
- CR. */
-
- if (code == MEM && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
- return CR_REGS;
-
- /* If between memory and a mode smaller than a word without DW being
- enabled, we need BP. */
-
- if (code == MEM && ! TARGET_DW_ENABLE
- && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
- return BP_REGS;
-
- /* Otherwise, we can place anything into GENERAL_REGS and can put
- GENERAL_REGS into anything. */
- if (class == GENERAL_REGS
- || (regno != -1
- && (regno < R_BP
- || (regno >= R_KR (0) && regno <= R_KR (31)))))
- return NO_REGS;
-
- /* We can place 16-bit constants into a special register. */
- if (code == CONST_INT
- && (GET_MODE_BITSIZE (mode) <= 16 || (unsigned) INTVAL (in) <= 65535)
- && (class == BP_REGS || class == Q_REGS || class == SPECIAL_REGS))
- return NO_REGS;
-
- /* Otherwise, we need GENERAL_REGS. */
- return GENERAL_REGS;
-}
-\f
-/* START is the zero-based incoming argument register index used (0 is 160,
- i.e., the first incoming argument register) and COUNT is the number used.
-
- Mark the corresponding incoming registers as neither fixed nor call used.
- For each register used for incoming arguments, we have one less local
- register that can be used. So also mark some high-numbered registers as
- fixed.
-
- Return the first register number to use for the argument. */
-
-int
-incoming_reg (start, count)
- int start;
- int count;
-{
- int i;
-
- /* We only use 16 argument registers, so truncate at the end of the
- area. */
- if (start + count > 16)
- count = 16 - start;
-
- if (! TARGET_NO_REUSE_ARGS)
- /* Mark all the used registers as not fixed and saved over calls. */
- for (i = R_AR (start); i < R_AR (start + count); i++)
- {
- fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0;
- CLEAR_HARD_REG_BIT (fixed_reg_set, i);
- CLEAR_HARD_REG_BIT (call_used_reg_set, i);
- CLEAR_HARD_REG_BIT (call_fixed_reg_set, i);
- }
-
- /* Shorten the maximum size of the frame.
- Remember that R_AR(-1,-2) are place holders for the caller's lr0,lr1.
- Make sure to keep the frame rounded to an even boundary. Rounding up
- to an 8 byte boundary will use a slot. Otherwise a frame with 121 local
- regs and 5 arguments will overrun the stack (121+1 + 5 + 2 > 128). */
- /* ??? An alternative would be to never allocate one reg. */
- for (i = (R_AR (0) - 2 - start - count) & ~1; i < R_AR (0) - 2 - start; i++)
- {
- fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
- SET_HARD_REG_BIT (fixed_reg_set, i);
- SET_HARD_REG_BIT (call_used_reg_set, i);
- SET_HARD_REG_BIT (call_fixed_reg_set, i);
- }
-
- return R_AR (start);
-}
-\f
-/* Add CLOBBERs to CALL_INSN_FUNCTION_USAGE chain of INSN indicating
- that LR2 up to, but not including, OP are clobbered. If OP is
- zero, indicate all parameter registers are clobbered. */
-
-void
-a29k_clobbers_to (insn, op)
- rtx insn;
- rtx op;
-{
- int i;
- int high_regno;
-
- if (op == 0)
- high_regno = R_LR (18);
- else if (GET_CODE (op) != REG || REGNO (op) < R_LR (0)
- || REGNO (op) > R_LR (18))
- abort ();
- else
- high_regno = REGNO (op);
-
- for (i = R_LR (2); i < high_regno; i++)
- CALL_INSN_FUNCTION_USAGE (insn)
- = gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_CLOBBER (VOIDmode,
- gen_rtx (REG, SImode, i)),
- CALL_INSN_FUNCTION_USAGE (insn));
-}
-\f
-/* These routines are used in finding insns to fill delay slots in the
- epilogue. */
-
-/* Return 1 if the current function will adjust the register stack. */
-
-int
-needs_regstack_p ()
-{
- int i;
- rtx insn;
-
- if (frame_pointer_needed)
- return 1;
-
- /* If any local register is used, we need to adjust the regstack. */
- for (i = R_LR (127); i >= R_LR (0); i --)
- if (regs_ever_live[i])
- return 1;
-
- /* We need a register stack if we make any calls. */
- for (insn = get_insns (); insn; insn = next_insn (insn))
- if (GET_CODE (insn) == CALL_INSN
- || (GET_CODE (insn) == INSN
- && GET_CODE (PATTERN (insn)) == SEQUENCE
- && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN))
- return 1;
-
- /* Otherwise, we don't. */
- return 0;
-}
-
-/* Return 1 if X uses a local register. */
-
-int
-uses_local_reg_p (x)
- rtx x;
-{
- const char *fmt;
- int i, j;
-
- switch (GET_CODE (x))
- {
- case REG:
- return REGNO (x) >= R_LR (0) && REGNO (x) <= R_FP;
-
- case CONST_INT:
- case CONST:
- case PC:
- case CC0:
- case LABEL_REF:
- case SYMBOL_REF:
- return 0;
-
- default:
- break;
- }
-
- fmt = GET_RTX_FORMAT (GET_CODE (x));
- for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
- {
- if (fmt[i] == 'e')
- {
- if (uses_local_reg_p (XEXP (x, i)))
- return 1;
- }
- else if (fmt[i] == 'E')
- {
- for (j = XVECLEN (x, i) - 1; j >= 0; j--)
- if (uses_local_reg_p (XVECEXP (x, i, j)))
- return 1;
- }
- }
-
- return 0;
-}
-
-/* Returns 1 if this function is known to have a null epilogue. */
-
-int
-null_epilogue ()
-{
- return (reload_completed && ! needs_regstack_p ()
- && get_frame_size () == 0
- && current_function_pretend_args_size == 0);
-}
-\f
-/* Write out the assembler form of an operand. Recognize the following
- special options:
-
- %N means write the low-order 8 bits of the negative of the constant
- %Q means write a QImode operand (truncate constants to 8 bits)
- %M means write the low-order 16 bits of the constant
- %m means write the low-order 16 bits shifted left 16 bits
- %C means write the low-order 8 bits of the complement of the constant
- %b means write `f' is this is a reversed condition, `t' otherwise
- %B means write `t' is this is a reversed condition, `f' otherwise
- %J means write the 29k opcode part for a comparison operation
- %e means write the label with an extra `X' is this is the epilogue
- otherwise the normal label name
- %E means write nothing if this insn has a delay slot,
- a nop unless this is the epilogue label, in which case
- write the first epilogue insn
- %F means write just the normal operand if the insn has a delay slot;
- otherwise, this is a recursive call so output the
- symbol + 4 and write the first prologue insn in the
- delay slot.
- %L means write the register number plus one ("low order" register)
- or the low-order part of a multi-word constant
- %O means write the register number plus two
- %P means write the register number plus three ("low order" of TImode)
- %S means write the number of words in the mode of the operand,
- minus one (for CR)
- %V means write the number of elements in a PARALLEL minus 1
- %# means write nothing if we have a delay slot, "\n\tnop" otherwise
- %* means write the register name for TPC. */
-
-void
-print_operand (file, x, code)
- FILE *file;
- rtx x;
- char code;
-{
- char buf[100];
-
- /* These macros test for integers and extract the low-order bits. */
-#define INT_P(X) \
-((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
- && GET_MODE (X) == VOIDmode)
-
-#define INT_LOWPART(X) \
- (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
-
- switch (code)
- {
- case 'Q':
- if (GET_CODE (x) == REG)
- break;
- else if (! INT_P (x))
- output_operand_lossage ("invalid %%Q value");
- fprintf (file, "%d", INT_LOWPART (x) & 0xff);
- return;
-
- case 'C':
- if (! INT_P (x))
- output_operand_lossage ("invalid %%C value");
- fprintf (file, "%d", (~ INT_LOWPART (x)) & 0xff);
- return;
-
- case 'N':
- if (! INT_P (x))
- output_operand_lossage ("invalid %%N value");
- fprintf (file, "%d", (- INT_LOWPART (x)) & 0xff);
- return;
-
- case 'M':
- if (! INT_P (x))
- output_operand_lossage ("invalid %%M value");
- fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
- return;
-
- case 'm':
- if (! INT_P (x))
- output_operand_lossage ("invalid %%m value");
- fprintf (file, "%d", (INT_LOWPART (x) & 0xffff) << 16);
- return;
-
- case 'b':
- if (GET_CODE (x) == GE)
- fprintf (file, "f");
- else
- fprintf (file, "t");
- return;
-
- case 'B':
- if (GET_CODE (x) == GE)
- fprintf (file, "t");
- else
- fprintf (file, "f");
- return;
-
- case 'J':
- /* It so happens that the RTX names for the conditions are the same as
- the 29k's insns except for "ne", which requires "neq". */
- fprintf (file, GET_RTX_NAME (GET_CODE (x)));
- if (GET_CODE (x) == NE)
- fprintf (file, "q");
- return;
-
- case 'e':
- if (optimize && flag_delayed_branch
- && a29k_last_prologue_insn == 0 && epilogue_operand (x, VOIDmode)
- && dbr_sequence_length () == 0)
- {
- /* We need to output the label number of the last label in the
- function, which is not necessarily X since there might be
- a USE insn in between. First go forward to the last insn, then
- back up to a label. */
- while (NEXT_INSN (x) != 0)
- x = NEXT_INSN (x);
-
- while (GET_CODE (x) != CODE_LABEL)
- x = PREV_INSN (x);
-
- ASM_GENERATE_INTERNAL_LABEL (buf, "LX", CODE_LABEL_NUMBER (x));
- assemble_name (file, buf);
- }
- else
- output_asm_label (x);
- return;
-
- case 'E':
- if (dbr_sequence_length ())
- ;
- else if (a29k_last_prologue_insn)
- {
- fprintf (file, "\n\t%s", a29k_last_prologue_insn);
- free (a29k_last_prologue_insn);
- a29k_last_prologue_insn = 0;
- }
- else if (optimize && flag_delayed_branch
- && epilogue_operand (x, VOIDmode))
- {
- fprintf (file, "\n\t%s", a29k_first_epilogue_insn);
- a29k_first_epilogue_insn_used = 1;
- }
- else
- fprintf (file, "\n\tnop");
- return;
-
- case 'F':
- output_addr_const (file, x);
- if (dbr_sequence_length () == 0)
- {
- /* If this doesn't have its delay slot filled, see if we need to
- put the last insn of the prolog in it. If not, see if this is
- a recursive call. If so, we can put the first insn of its
- prolog in the delay slot. Otherwise, write a nop. */
- if (a29k_last_prologue_insn)
- {
- fprintf (file, "\n\t%s", a29k_last_prologue_insn);
- free (a29k_last_prologue_insn);
- a29k_last_prologue_insn = 0;
- }
- else if (GET_CODE (x) == SYMBOL_REF
- && ! strcmp (XSTR (x, 0), current_function_name))
- fprintf (file, "+4\n\t%s,%d",
- a29k_regstack_size >= 64 ? "const gr121" : "sub gr1,gr1",
- a29k_regstack_size * 4);
- else
- fprintf (file, "\n\tnop");
- }
- return;
-
- case 'L':
- if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
- {
- REAL_VALUE_TYPE r;
- char s[30];
-
- REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- REAL_VALUE_TO_DECIMAL (r, "%.20e", s);
-
- fprintf (file, "$double1(%s)", s);
- }
- else if (GET_CODE (x) == REG)
- fprintf (file, "%s", reg_names[REGNO (x) + 1]);
- else
- output_operand_lossage ("invalid %%L value");
- return;
-
- case 'O':
- if (GET_CODE (x) != REG)
- output_operand_lossage ("invalid %%O value");
- fprintf (file, "%s", reg_names[REGNO (x) + 2]);
- return;
-
- case 'P':
- if (GET_CODE (x) != REG)
- output_operand_lossage ("invalid %%P value");
- fprintf (file, "%s", reg_names[REGNO (x) + 3]);
- return;
-
- case 'S':
- fprintf (file, "%d", (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD)-1);
- return;
-
- case 'V':
- if (GET_CODE (x) != PARALLEL)
- output_operand_lossage ("invalid %%V value");
- fprintf (file, "%d", XVECLEN (x, 0) - 2);
- return;
-
- case '#':
- if (dbr_sequence_length () == 0)
- {
- if (a29k_last_prologue_insn)
- {
- fprintf (file, "\n\t%s", a29k_last_prologue_insn);
- free (a29k_last_prologue_insn);
- a29k_last_prologue_insn = 0;
- }
- else
- fprintf (file, "\n\tnop");
- }
- return;
-
- case '*':
- fprintf (file, "%s", reg_names [R_TPC]);
- return;
- }
-
- if (GET_CODE (x) == REG)
- fprintf (file, "%s", reg_names [REGNO (x)]);
-
- else if (GET_CODE (x) == MEM)
- output_address (XEXP (x, 0));
-
- else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == SUBREG
- && GET_CODE (SUBREG_REG (XEXP (x, 0))) == CONST_DOUBLE)
- {
- REAL_VALUE_TYPE r;
- char s[30];
-
- if (GET_MODE (SUBREG_REG (XEXP (x, 0))) == SFmode)
- fprintf (file, "$float");
- else
- fprintf (file, "$double%d",
- (SUBREG_BYTE (XEXP (x, 0)) / GET_MODE_SIZE (GET_MODE (x))));
-
- REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- REAL_VALUE_TO_DECIMAL (r, "%.20e", s);
- fprintf (file, "(%s)", s);
- }
-
- else if (GET_CODE (x) == CONST_DOUBLE
- && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
- {
- REAL_VALUE_TYPE r;
- char s[30];
-
- REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- REAL_VALUE_TO_DECIMAL (r, "%.20e", s);
- fprintf (file, "$%s(%s)",
- GET_MODE (x) == SFmode ? "float" : "double0", s);
- }
-
- else
- output_addr_const (file, x);
-}
-\f
-/* This page contains routines to output function prolog and epilog code. */
-
-/* Compute the size of the register stack, and determine if there are any
- call instructions. */
-
-static void
-compute_regstack_size ()
-{
- int i;
- rtx insn;
-
- /* See if we make any calls. We need to set lr1 if so. */
- a29k_makes_calls = 0;
- for (insn = get_insns (); insn; insn = next_insn (insn))
- if (GET_CODE (insn) == CALL_INSN
- || (GET_CODE (insn) == INSN
- && GET_CODE (PATTERN (insn)) == SEQUENCE
- && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN))
- {
- a29k_makes_calls = 1;
- break;
- }
-
- /* Find the highest local register used. */
- for (i = R_LR (127); i >= R_LR (0); i--)
- if (regs_ever_live[i])
- break;
-
- a29k_regstack_size = i - (R_LR (0) - 1);
-
- /* If calling routines, ensure we count lr0 & lr1. */
- if (a29k_makes_calls && a29k_regstack_size < 2)
- a29k_regstack_size = 2;
-
- /* Count frame pointer and align to 8 byte boundary (even number of
- registers). */
- a29k_regstack_size += frame_pointer_needed;
- if (a29k_regstack_size & 1) a29k_regstack_size++;
-}
-
-/* Sets register names for incoming arguments and frame pointer.
- This can't be computed until after register allocation. */
-
-void
-a29k_compute_reg_names ()
-{
- int i;
-
- compute_regstack_size ();
-
- /* Set the names and numbers of the frame pointer and incoming argument
- registers. */
-
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- a29k_debug_reg_map[i] = i;
-
- reg_names[FRAME_POINTER_REGNUM] = reg_names[R_LR (a29k_regstack_size - 1)];
- a29k_debug_reg_map[FRAME_POINTER_REGNUM] = R_LR (a29k_regstack_size - 1);
-
- for (i = 0; i < 16; i++)
- {
- reg_names[R_AR (i)] = reg_names[R_LR (a29k_regstack_size + i + 2)];
- a29k_debug_reg_map[R_AR (i)] = R_LR (a29k_regstack_size + i + 2);
- }
-
- /* If using kernel register map, swap numbers for kernel and user
- registers. */
- if (TARGET_KERNEL_REGISTERS)
- for (i = 0; i < 32; i++)
- {
- int tem = a29k_debug_reg_map[i];
- a29k_debug_reg_map[i] = a29k_debug_reg_map[R_KR (i)];
- a29k_debug_reg_map[R_KR (i)] = tem;
- }
-}
-
-/* Output function prolog code to file FILE. Memory stack size is SIZE. */
-
-static void
-output_function_prologue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- int i;
- int arg_count = 0;
- rtx insn;
- unsigned int tag_word;
-
- /* See how many incoming arguments we have in registers. */
- for (i = R_AR (0); i < R_AR (16); i++)
- if (! fixed_regs[i])
- arg_count++;
-
- /* The argument count includes the caller's lr0 and lr1. */
- arg_count += 2;
-
- /* Compute memory stack size. Add in number of bytes that the we should
- push and pretend the caller did and the size of outgoing arguments.
- Then round to a doubleword boundary. */
- size += (current_function_pretend_args_size
- + current_function_outgoing_args_size);
- size = (size + 7) & ~7;
-
- /* Write header words. See if one or two word form. */
- tag_word = (frame_pointer_needed ? 0x400000 : 0) + (arg_count << 16);
-
- if (size / 8 > 0xff)
- fprintf (file, "\t.word %d, 0x%0x\n", (size / 8) << 2,
- 0x800000 + tag_word);
- else
- fprintf (file, "\t.word 0x%0x\n", tag_word + ((size / 8) << 3));
-
- /* Define the function name. */
- assemble_name (file, a29k_function_name);
- fprintf (file, ":\n");
-
- /* Push the register stack by the proper amount. There are two possible
- ways to do this. */
- if (a29k_regstack_size >= 256/4)
- fprintf (file, "\tconst %s,%d\n\tsub gr1,gr1,%s\n",
- reg_names[R_TAV], a29k_regstack_size * 4, reg_names[R_TAV]);
- else if (a29k_regstack_size)
- fprintf (file, "\tsub gr1,gr1,%d\n", a29k_regstack_size * 4);
-
- /* Test that the registers are available. */
- if (a29k_regstack_size)
- fprintf (file, "\tasgeu V_%sSPILL,gr1,%s\n",
- TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RAB]);
-
- /* Set up frame pointer, if one is needed. */
- if (frame_pointer_needed)
- fprintf (file, "\tsll %s,%s,0\n", reg_names[FRAME_POINTER_REGNUM],
- reg_names[R_MSP]);
-
- /* Make room for any frame space. There are three ways to do this. */
- if (size >= 256)
- {
- fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size);
- if (size >= 65536)
- fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size);
- if (TARGET_STACK_CHECK)
- fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]);
- fprintf (file, "\tsub %s,%s,%s\n",
- reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]);
- }
- else if (size)
- {
- if (TARGET_STACK_CHECK)
- fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]);
- fprintf (file, "\tsub %s,%s,%d\n",
- reg_names[R_MSP], reg_names[R_MSP], size);
- }
-
- /* If this routine will make calls, set lr1. If we see an insn that
- can use a delay slot before a call or jump, save this insn for that
- slot (this condition is equivalent to seeing if we have an insn that
- needs delay slots before an insn that has a filled delay slot). */
- a29k_last_prologue_insn = 0;
- if (a29k_makes_calls)
- {
- i = (a29k_regstack_size + arg_count) * 4;
- if (i >= 256)
- fprintf (file, "\tconst %s,%d\n\tadd lr1,gr1,%s\n",
- reg_names[R_TAV], i, reg_names[R_TAV]);
- else
- {
- if (optimize && flag_delayed_branch)
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
- {
- if (GET_CODE (insn) == CODE_LABEL
- || (GET_CODE (insn) == INSN
- && GET_CODE (PATTERN (insn)) == SEQUENCE))
- break;
-
- if (GET_CODE (insn) == NOTE
- || (GET_CODE (insn) == INSN
- && (GET_CODE (PATTERN (insn)) == USE
- || GET_CODE (PATTERN (insn)) == CLOBBER)))
- continue;
-
- if (num_delay_slots (insn) > 0)
- {
- a29k_last_prologue_insn = (char *) xmalloc (100);
- sprintf (a29k_last_prologue_insn, "add lr1,gr1,%d", i);
- break;
- }
- }
-
- if (a29k_last_prologue_insn == 0)
- fprintf (file, "\tadd lr1,gr1,%d\n", i);
- }
- }
-
- /* Compute the first insn of the epilogue. */
- a29k_first_epilogue_insn_used = 0;
-
- if (size == 0 && a29k_regstack_size == 0 && ! frame_pointer_needed)
- a29k_first_epilogue_insn = 0;
- else
- a29k_first_epilogue_insn = (char *) xmalloc (100);
-
- if (frame_pointer_needed)
- sprintf (a29k_first_epilogue_insn, "sll %s,%s,0",
- reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]);
- else if (a29k_regstack_size)
- {
- if (a29k_regstack_size >= 256 / 4)
- sprintf (a29k_first_epilogue_insn, "const %s,%d",
- reg_names[R_TAV], a29k_regstack_size * 4);
- else
- sprintf (a29k_first_epilogue_insn, "add gr1,gr1,%d",
- a29k_regstack_size * 4);
- }
- else if (size)
- {
- if (size >= 256)
- sprintf (a29k_first_epilogue_insn, "const %s,%d",
- reg_names[R_TAV], size);
- else
- sprintf (a29k_first_epilogue_insn, "add %s,%s,%d",
- reg_names[R_MSP], reg_names[R_MSP], size);
- }
-}
-\f
-/* Call this after writing what might be the first instruction of the
- epilogue. If that first insn was used in a delay slot, an intermediate
- label is written. */
-
-static void
-check_epilogue_internal_label (file)
- FILE *file;
-{
- rtx insn;
-
- if (! a29k_first_epilogue_insn_used)
- return;
-
- for (insn = get_last_insn ();
- GET_CODE (insn) != CODE_LABEL;
- insn = PREV_INSN (insn))
- ;
-
- ASM_OUTPUT_INTERNAL_LABEL (file, "LX", CODE_LABEL_NUMBER (insn));
- a29k_first_epilogue_insn_used = 0;
-}
-
-/* Output the epilog of the last procedure to file FILE. SIZE is the memory
- stack size. The register stack size is in the variable
- A29K_REGSTACK_SIZE. */
-
-static void
-output_function_epilogue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- rtx insn;
- int locals_unavailable = 0; /* True until after first insn
- after gr1 update. */
-
- /* If we hit a BARRIER before a real insn or CODE_LABEL, we don't
- need to do anything because we are never jumped to. */
- insn = get_last_insn ();
- if (GET_CODE (insn) == NOTE)
- insn = prev_nonnote_insn (insn);
-
- if (insn && GET_CODE (insn) == BARRIER)
- return;
-
- /* If a frame pointer was needed we must restore the memory stack pointer
- before adjusting the register stack. */
- if (frame_pointer_needed)
- {
- fprintf (file, "\tsll %s,%s,0\n",
- reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]);
- check_epilogue_internal_label (file);
- }
-
- /* Restore the register stack. There are two ways to do this. */
- if (a29k_regstack_size)
- {
- if (a29k_regstack_size >= 256/4)
- {
- fprintf (file, "\tconst %s,%d\n",
- reg_names[R_TAV], a29k_regstack_size * 4);
- check_epilogue_internal_label (file);
- fprintf (file, "\tadd gr1,gr1,%s\n", reg_names[R_TAV]);
- }
- else
- {
- fprintf (file, "\tadd gr1,gr1,%d\n", a29k_regstack_size * 4);
- check_epilogue_internal_label (file);
- }
- locals_unavailable = 1;
- }
-
- /* Restore the memory stack pointer if there is no frame pointer.
- Adjust the size to include any pretend arguments and pushed
- arguments and round to doubleword boundary. */
- size += (current_function_pretend_args_size
- + current_function_outgoing_args_size);
- size = (size + 7) & ~7;
-
- if (size && ! frame_pointer_needed)
- {
- if (size >= 256)
- {
- fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size);
- check_epilogue_internal_label (file);
- locals_unavailable = 0;
- if (size >= 65536)
- fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size);
- fprintf (file, "\tadd %s,%s,%s\n",
- reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]);
- }
- else
- {
- fprintf (file, "\tadd %s,%s,%d\n",
- reg_names[R_MSP], reg_names[R_MSP], size);
- check_epilogue_internal_label (file);
- locals_unavailable = 0;
- }
- }
-
- if (locals_unavailable)
- {
- /* If we have an insn for this delay slot, write it. */
- if (current_function_epilogue_delay_list)
- final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
- file, 1, -2, 1);
- else
- fprintf (file, "\tnop\n");
- }
-
- fprintf (file, "\tjmpi lr0\n");
- if (a29k_regstack_size)
- fprintf (file, "\tasleu V_%sFILL,lr1,%s\n",
- TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RFB]);
- else if (current_function_epilogue_delay_list)
- final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
- file, 1, -2, 1);
- else
- fprintf (file, "\tnop\n");
-
- if (a29k_first_epilogue_insn)
- free (a29k_first_epilogue_insn);
- a29k_first_epilogue_insn = 0;
-}
-
-static void
-a29k_asm_named_section (name, flags)
- const char *name;
- unsigned int flags ATTRIBUTE_UNUSED;
-{
- /* ??? Is it really correct to mark all sections as "bss"? */
- fprintf (asm_out_file, "\t.sect %s, bss\n\t.use %s\n", name, name);
-}
-
-/* Return a new value for COST based on the relationship between INSN
- that is dependent on DEP_INSN through the dependence LINK. The
- default is to make no adjustment to COST.
-
- On the a29k, ignore the cost of anti- and output-dependencies. */
-static int
-a29k_adjust_cost (insn, link, dep_insn, cost)
- rtx insn ATTRIBUTE_UNUSED;
- rtx link;
- rtx dep_insn ATTRIBUTE_UNUSED;
- int cost;
-{
- if (REG_NOTE_KIND (link) != 0)
- return 0; /* Anti or output dependence. */
-
- return cost;
-}
-
-/* If we are referencing a function that is static or is known to be
- in this file, make the SYMBOL_REF special. We can use this to
- indicate that we can branch to this function without emitting a
- no-op after the call. */
-
-static void
-a29k_encode_section_info (decl, first)
- tree decl;
- int first ATTRIBUTE_UNUSED;
-{
- if (TREE_CODE (decl) == FUNCTION_DECL
- && (TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)))
- SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU.
- Copyright (C) 1988, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 2000, 2001, 2002 Free Software Foundation, Inc.
- Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-D_AM29K -D_AM29000 -D_EPI -Acpu=a29k -Amachine=a29k"
-
-/* Print subsidiary information on the compiler version in use. */
-#define TARGET_VERSION
-
-/* Pass -w to assembler. */
-#define ASM_SPEC "-w"
-
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-/* This means that the DW bit will be enabled, to allow direct loads
- of bytes. */
-
-#define TARGET_DW_ENABLE (target_flags & 1)
-
-/* This means that the external hardware does supports byte writes. */
-
-#define TARGET_BYTE_WRITES (target_flags & 2)
-
-/* This means that a "small memory model" has been selected where all
- function addresses are known to be within 256K. This allows CALL to be
- used. */
-
-#define TARGET_SMALL_MEMORY (target_flags & 4)
-
-/* This means that we must always used on indirect call, even when
- calling a function in the same file, since the file might be > 256KB. */
-
-#define TARGET_LARGE_MEMORY (target_flags & 8)
-
-/* This means that we are compiling for a 29050. */
-
-#define TARGET_29050 (target_flags & 16)
-
-/* This means that we are compiling for the kernel which means that we use
- gr64-gr95 instead of gr96-126. */
-
-#define TARGET_KERNEL_REGISTERS (target_flags & 32)
-
-/* This means that a call to "__msp_check" should be inserted after each stack
- adjustment to check for stack overflow. */
-
-#define TARGET_STACK_CHECK (target_flags & 64)
-
-/* This handles 29k processors which cannot handle the separation
- of a mtsrim insns and a storem insn (most 29000 chips to date, but
- not the 29050. */
-
-#define TARGET_NO_STOREM_BUG (target_flags & 128)
-
-/* This forces the compiler not to use incoming argument registers except
- for copying out arguments. It helps detect problems when a function is
- called with fewer arguments than it is declared with. */
-
-#define TARGET_NO_REUSE_ARGS (target_flags & 256)
-
-/* This means that neither builtin nor emulated float operations are
- available, and that GCC should generate libcalls instead. */
-
-#define TARGET_SOFT_FLOAT (target_flags & 512)
-
-/* This means that we should not emit the multm or mutmu instructions
- that some embedded systems' trap handlers don't support. */
-
-#define TARGET_MULTM ((target_flags & 1024) == 0)
-
-#define TARGET_SWITCHES \
- { {"dw", 1, N_("Generate code assuming DW bit is set")}, \
- {"ndw", -1, N_("Generate code assuming DW bit is not set")}, \
- {"bw", 2, N_("Generate code using byte writes")}, \
- {"nbw", - (1|2), N_("Do not generate byte writes")}, \
- {"small", 4, N_("Use small memory model")}, \
- {"normal", - (4|8), N_("Use normal memory model")}, \
- {"large", 8, N_("Use large memory model")}, \
- {"29050", 16+128, N_("Generate 29050 code")}, \
- {"29000", -16, N_("Generate 29000 code")}, \
- {"kernel-registers", 32, N_("Use kernel global registers")}, \
- {"user-registers", -32, N_("Use user global registers")}, \
- {"stack-check", 64, N_("Emit stack checking code")}, \
- {"no-stack-check", - 74, N_("Do not emit stack checking code")}, \
- {"storem-bug", -128, N_("Work around storem hardware bug")}, \
- {"no-storem-bug", 128, N_("Do not work around storem hardware bug")}, \
- {"reuse-arg-regs", -256, N_("Store locals in argument registers")}, \
- {"no-reuse-arg-regs", 256, N_("Do not store locals in arg registers")}, \
- {"soft-float", 512, N_("Use software floating point")}, \
- {"no-multm", 1024, N_("Do not generate multm instructions")}, \
- {"", TARGET_DEFAULT, NULL}}
-
-#define TARGET_DEFAULT 3
-
-/* Show we can debug even without a frame pointer. */
-#define CAN_DEBUG_WITHOUT_FP
-\f
-/* target machine storage layout */
-
-/* Define the types for size_t, ptrdiff_t, and wchar_t. These are the
- same as those used by EPI. The type for wchar_t does not make much
- sense, but is what is used. */
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_TYPE "char"
-#define WCHAR_TYPE_SIZE BITS_PER_UNIT
-
-/* Define this macro if it is advisable to hold scalars in registers
- in a wider mode than that declared by the program. In such cases,
- the value is constrained to be within the bounds of the declared
- type, but kept valid in the wider mode. The signedness of the
- extension may differ from that of the type. */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
- if (GET_MODE_CLASS (MODE) == MODE_INT \
- && GET_MODE_SIZE (MODE) < 4) \
- (MODE) = SImode;
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields.
- This is arbitrary on the 29k since it has no actual bit-field insns.
- It is better to define this as TRUE because BYTES_BIG_ENDIAN is TRUE
- and we want to be able to convert BP position to bit position with
- just a shift. */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.
- This is true on 29k. */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is lowest
- numbered.
-
- For 29k we can decide arbitrarily since there are no machine instructions
- for them. Might as well be consistent with bytes. */
-#define WORDS_BIG_ENDIAN 1
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 4
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#define STACK_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this. */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct. */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this. */
-#define BIGGEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster. */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- (TREE_CODE (EXP) == STRING_CST \
- && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons. */
-#define DATA_ALIGNMENT(TYPE, ALIGN) \
- (TREE_CODE (TYPE) == ARRAY_TYPE \
- && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
- && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Set this non-zero if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 0
-
-/* Set this non-zero if unaligned move instructions are extremely slow.
-
- On the 29k, they trap. */
-#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
-\f
-/* Standard register usage. */
-
-/* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers.
-
- 29k has 256 registers, of which 62 are not defined. gr0 and gr1 are
- not produced in generated RTL so we can start at gr96, and call it
- register zero.
-
- So 0-31 are gr96-gr127, lr0-lr127 are 32-159. To represent the input
- arguments, whose register numbers we won't know until we are done,
- use register 160-175. They cannot be modified. Similarly, 176 is used
- for the frame pointer. It is assigned the last local register number
- once the number of registers used is known.
-
- We use 177, 178, 179, and 180 for the special registers BP, FC, CR, and Q,
- respectively. Registers 181 through 199 are used for the other special
- registers that may be used by the programmer, but are never used by the
- compiler.
-
- Registers 200-203 are the four floating-point accumulator register in
- the 29050.
-
- Registers 204-235 are the 32 global registers for kernel mode when
- -mkernel-registers is not specified, and the 32 global user registers
- when it is.
-
- When -mkernel-registers is specified, we still use the same register
- map but change the names so 0-31 print as gr64-gr95. */
-
-#define FIRST_PSEUDO_REGISTER 236
-
-/* Because of the large number of registers on the 29k, we define macros
- to refer to each group of registers and then define the number for some
- registers used in the calling sequence. */
-
-#define R_GR(N) ((N) - 96) /* gr96 is register number 0 */
-#define R_LR(N) ((N) + 32) /* lr0 is register number 32 */
-#define R_FP 176 /* frame pointer is register 176 */
-#define R_AR(N) ((N) + 160) /* first incoming arg reg is 160 */
-#define R_KR(N) ((N) + 204) /* kernel registers (gr64 to gr95) */
-
-/* Define the numbers of the special registers. */
-#define R_BP 177
-#define R_FC 178
-#define R_CR 179
-#define R_Q 180
-
-/* These special registers are not used by the compiler, but may be referenced
- by the programmer via asm declarations. */
-
-#define R_VAB 181
-#define R_OPS 182
-#define R_CPS 183
-#define R_CFG 184
-#define R_CHA 185
-#define R_CHD 186
-#define R_CHC 187
-#define R_RBP 188
-#define R_TMC 189
-#define R_TMR 190
-#define R_PC0 191
-#define R_PC1 192
-#define R_PC2 193
-#define R_MMU 194
-#define R_LRU 195
-#define R_FPE 196
-#define R_INT 197
-#define R_FPS 198
-#define R_EXO 199
-
-/* Define the number for floating-point accumulator N. */
-#define R_ACU(N) ((N) + 200)
-
-/* Now define the registers used in the calling sequence. */
-#define R_TAV R_GR (121)
-#define R_TPC R_GR (122)
-#define R_LRP R_GR (123)
-#define R_SLP R_GR (124)
-#define R_MSP R_GR (125)
-#define R_RAB R_GR (126)
-#define R_RFB R_GR (127)
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator. */
-
-#define FIXED_REGISTERS \
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
- 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 0, 0, 0, 0, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like. */
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* List the order in which to allocate registers. Each register must be
- listed once, even those in FIXED_REGISTERS.
-
- We allocate in the following order:
- gr116-gr120 (not used for anything but temps)
- gr96-gr111 (function return values, reverse order)
- argument registers (160-175)
- lr0-lr127 (locals, saved)
- acc3-0 (acc0 special)
- everything else */
-
-#define REG_ALLOC_ORDER \
- {R_GR (116), R_GR (117), R_GR (118), R_GR (119), R_GR (120), \
- R_GR (111), R_GR (110), R_GR (109), R_GR (108), R_GR (107), \
- R_GR (106), R_GR (105), R_GR (104), R_GR (103), R_GR (102), \
- R_GR (101), R_GR (100), R_GR (99), R_GR (98), R_GR (97), R_GR (96), \
- R_AR (0), R_AR (1), R_AR (2), R_AR (3), R_AR (4), R_AR (5), \
- R_AR (6), R_AR (7), R_AR (8), R_AR (9), R_AR (10), R_AR (11), \
- R_AR (12), R_AR (13), R_AR (14), R_AR (15), \
- R_LR (0), R_LR (1), R_LR (2), R_LR (3), R_LR (4), R_LR (5), \
- R_LR (6), R_LR (7), R_LR (8), R_LR (9), R_LR (10), R_LR (11), \
- R_LR (12), R_LR (13), R_LR (14), R_LR (15), R_LR (16), R_LR (17), \
- R_LR (18), R_LR (19), R_LR (20), R_LR (21), R_LR (22), R_LR (23), \
- R_LR (24), R_LR (25), R_LR (26), R_LR (27), R_LR (28), R_LR (29), \
- R_LR (30), R_LR (31), R_LR (32), R_LR (33), R_LR (34), R_LR (35), \
- R_LR (36), R_LR (37), R_LR (38), R_LR (39), R_LR (40), R_LR (41), \
- R_LR (42), R_LR (43), R_LR (44), R_LR (45), R_LR (46), R_LR (47), \
- R_LR (48), R_LR (49), R_LR (50), R_LR (51), R_LR (52), R_LR (53), \
- R_LR (54), R_LR (55), R_LR (56), R_LR (57), R_LR (58), R_LR (59), \
- R_LR (60), R_LR (61), R_LR (62), R_LR (63), R_LR (64), R_LR (65), \
- R_LR (66), R_LR (67), R_LR (68), R_LR (69), R_LR (70), R_LR (71), \
- R_LR (72), R_LR (73), R_LR (74), R_LR (75), R_LR (76), R_LR (77), \
- R_LR (78), R_LR (79), R_LR (80), R_LR (81), R_LR (82), R_LR (83), \
- R_LR (84), R_LR (85), R_LR (86), R_LR (87), R_LR (88), R_LR (89), \
- R_LR (90), R_LR (91), R_LR (92), R_LR (93), R_LR (94), R_LR (95), \
- R_LR (96), R_LR (97), R_LR (98), R_LR (99), R_LR (100), R_LR (101), \
- R_LR (102), R_LR (103), R_LR (104), R_LR (105), R_LR (106), \
- R_LR (107), R_LR (108), R_LR (109), R_LR (110), R_LR (111), \
- R_LR (112), R_LR (113), R_LR (114), R_LR (115), R_LR (116), \
- R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121), \
- R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126), \
- R_LR (127), \
- R_ACU (3), R_ACU (2), R_ACU (1), R_ACU (0), \
- R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121), \
- R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126), \
- R_GR (127), \
- R_FP, R_BP, R_FC, R_CR, R_Q, \
- R_VAB, R_OPS, R_CPS, R_CFG, R_CHA, R_CHD, R_CHC, R_RBP, R_TMC, \
- R_TMR, R_PC0, R_PC1, R_PC2, R_MMU, R_LRU, R_FPE, R_INT, R_FPS, \
- R_EXO, \
- R_KR (0), R_KR (1), R_KR (2), R_KR (3), R_KR (4), R_KR (5), \
- R_KR (6), R_KR (7), R_KR (8), R_KR (9), R_KR (10), R_KR (11), \
- R_KR (12), R_KR (13), R_KR (14), R_KR (15), R_KR (16), R_KR (17), \
- R_KR (18), R_KR (19), R_KR (20), R_KR (21), R_KR (22), R_KR (23), \
- R_KR (24), R_KR (25), R_KR (26), R_KR (27), R_KR (28), R_KR (29), \
- R_KR (30), R_KR (31) }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers. */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)? 1 \
- : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- On 29k, the cpu registers can hold any mode. But a double-precision
- floating-point value should start at an even register. The special
- registers cannot hold floating-point values, BP, CR, and FC cannot
- hold integer or floating-point values, and the accumulators cannot
- hold integer values.
-
- DImode and larger values should start at an even register just like
- DFmode values, even though the instruction set doesn't require it, in order
- to prevent reload from aborting due to a modes_equiv_for_class_p failure.
-
- (I'd like to use the "?:" syntax to make this more readable, but Sun's
- compiler doesn't seem to accept it.) */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-(((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3) \
- && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
- || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)) \
- || ((REGNO) >= R_BP && (REGNO) <= R_CR \
- && GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT) \
- || ((REGNO) >= R_Q && (REGNO) < R_ACU (0) \
- && GET_MODE_CLASS (MODE) != MODE_FLOAT \
- && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \
- || (((REGNO) < R_BP || (REGNO) >= R_KR (0)) \
- && ((((REGNO) & 1) == 0) \
- || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD)))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output.
-
- On the 29k, normally we'd just have problems with DFmode because of the
- even alignment. However, we also have to be a bit concerned about
- the special register's restriction to non-floating and the floating-point
- accumulator's restriction to only floating. This probably won't
- cause any great inefficiencies in practice. */
-
-#define MODES_TIEABLE_P(MODE1, MODE2) \
- ((MODE1) == (MODE2) \
- || (GET_MODE_CLASS (MODE1) == MODE_INT \
- && GET_MODE_CLASS (MODE2) == MODE_INT))
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-/* 29k pc isn't overloaded on a register that the compiler knows about. */
-/* #define PC_REGNUM */
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM R_GR (125)
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM R_FP
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM R_FP
-
-/* Register in which static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM R_SLP
-
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM R_LRP
-\f
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union.
-
- The 29k has nine registers classes: LR0_REGS, GENERAL_REGS, SPECIAL_REGS,
- BP_REGS, FC_REGS, CR_REGS, Q_REGS, ACCUM_REGS, and ACCUM0_REGS.
- LR0_REGS, BP_REGS, FC_REGS, CR_REGS, and Q_REGS contain just the single
- register. The latter two classes are used to represent the floating-point
- accumulator registers in the 29050. We also define the union class
- FLOAT_REGS to represent any register that can be used to hold a
- floating-point value. The union of SPECIAL_REGS and ACCUM_REGS isn't
- useful as the former cannot contain floating-point and the latter can only
- contain floating-point. */
-
-enum reg_class { NO_REGS, LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS, CR_REGS,
- Q_REGS, SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS,
- ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file. */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "LR0_REGS", "GENERAL_REGS", "BP_REGS", "FC_REGS", "CR_REGS", \
- "Q_REGS", "SPECIAL_REGS", "ACCUM0_REGS", "ACCUM_REGS", "FLOAT_REGS", \
- "ALL_REGS" }
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. */
-
-#define REG_CLASS_CONTENTS \
- { {0, 0, 0, 0, 0, 0, 0, 0}, \
- {0, 1, 0, 0, 0, 0, 0, 0}, \
- {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfff}, \
- {0, 0, 0, 0, 0, 0x20000, 0, 0}, \
- {0, 0, 0, 0, 0, 0x40000, 0, 0}, \
- {0, 0, 0, 0, 0, 0x80000, 0, 0}, \
- {0, 0, 0, 0, 0, 0x100000, 0, 0}, \
- {0, 0, 0, 0, 0, 0xfffe0000, 0xff, 0}, \
- {0, 0, 0, 0, 0, 0, 0x100, 0}, \
- {0, 0, 0, 0, 0, 0, 0xf00, 0}, \
- {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, 0xfff}, \
- {~0, ~0, ~0, ~0, ~0, ~0, ~0, 0xfff} }
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) == R_BP ? BP_REGS \
- : (REGNO) == R_FC ? FC_REGS \
- : (REGNO) == R_CR ? CR_REGS \
- : (REGNO) == R_Q ? Q_REGS \
- : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS \
- : (REGNO) == R_ACU (0) ? ACCUM0_REGS \
- : (REGNO) >= R_KR (0) ? GENERAL_REGS \
- : (REGNO) > R_ACU (0) ? ACCUM_REGS \
- : (REGNO) == R_LR (0) ? LR0_REGS \
- : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'r' ? GENERAL_REGS \
- : (C) == 'l' ? LR0_REGS \
- : (C) == 'b' ? BP_REGS \
- : (C) == 'f' ? FC_REGS \
- : (C) == 'c' ? CR_REGS \
- : (C) == 'q' ? Q_REGS \
- : (C) == 'h' ? SPECIAL_REGS \
- : (C) == 'a' ? ACCUM_REGS \
- : (C) == 'A' ? ACCUM0_REGS \
- : (C) == 'f' ? FLOAT_REGS \
- : NO_REGS)
-
-/* Define this macro to change register usage conditional on target flags.
-
- On the 29k, we use this to change the register names for kernel mapping. */
-
-#define CONDITIONAL_REGISTER_USAGE \
- { \
- const char *p; \
- int i; \
- \
- if (TARGET_KERNEL_REGISTERS) \
- for (i = 0; i < 32; i++) \
- { \
- p = reg_names[i]; \
- reg_names[i] = reg_names[R_KR (i)]; \
- reg_names[R_KR (i)] = p; \
- } \
- }
-
-/* The letters I, J, K, L, M, N, O, and P in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- For 29k:
- `I' is used for the range of constants most insns can contain.
- `J' is for the few 16-bit insns.
- `K' is a constant whose high-order 24 bits are all one
- `L' is a HImode constant whose high-order 8 bits are all one
- `M' is a 32-bit constant whose high-order 16 bits are all one (for CONSTN)
- `N' is a 32-bit constant whose negative is 8 bits
- `O' is the 32-bit constant 0x80000000, any constant with low-order
- 16 bits zero for 29050.
- `P' is a HImode constant whose negative is 8 bits */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? (unsigned) (VALUE) < 0x100 \
- : (C) == 'J' ? (unsigned) (VALUE) < 0x10000 \
- : (C) == 'K' ? ((VALUE) & 0xffffff00) == 0xffffff00 \
- : (C) == 'L' ? ((VALUE) & 0xff00) == 0xff00 \
- : (C) == 'M' ? ((VALUE) & 0xffff0000) == 0xffff0000 \
- : (C) == 'N' ? ((VALUE) < 0 && (VALUE) > -256) \
- : (C) == 'O' ? ((VALUE) == 0x80000000 \
- || (TARGET_29050 && ((VALUE) & 0xffff) == 0)) \
- : (C) == 'P' ? (((VALUE) | 0xffff0000) < 0 \
- && ((VALUE) | 0xffff0000) > -256) \
- : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself.
- All floating-point constants are valid on 29k. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
-
-/* Return the register class of a scratch register needed to copy IN into
- or out of a register in CLASS in MODE. If it can be done directly,
- NO_REGS is returned. */
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
- secondary_reload_class (CLASS, MODE, IN)
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS.
-
- On 29k, this is the size of MODE in words except that the floating-point
- accumulators only require one word for anything they can hold. */
-
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- (((CLASS) == ACCUM_REGS || (CLASS) == ACCUM0_REGS) ? 1 \
- : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Define the cost of moving between registers of various classes. Everything
- involving a general register is cheap, but moving between the other types
- (even within a class) is two insns. */
-
-#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
- ((CLASS1) == GENERAL_REGS || (CLASS2) == GENERAL_REGS ? 2 : 4)
-
-/* A C expressions returning the cost of moving data of MODE from a register to
- or from memory.
-
- It takes extra insns on the 29k to form addresses, so we want to make
- this higher. In addition, we need to keep it more expensive than the
- most expensive register-register copy. */
-
-#define MEMORY_MOVE_COST(MODE,CLASS,IN) 6
-\f
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- that is, each additional local variable allocated
- goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated. */
-
-#define STARTING_FRAME_OFFSET (- current_function_pretend_args_size)
-
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by.
- On 29k, don't define this because there are no push insns. */
-/* #define PUSH_ROUNDING(BYTES) */
-
-/* Define this if the maximum size of all the outgoing args is to be
- accumulated and pushed during the prologue. The amount can be
- found in the variable current_function_outgoing_args_size. */
-#define ACCUMULATE_OUTGOING_ARGS 1
-
-/* Offset of first parameter from the argument pointer register value. */
-
-#define FIRST_PARM_OFFSET(FNDECL) (- current_function_pretend_args_size)
-
-/* Define this if stack space is still allocated for a parameter passed
- in a register. */
-/* #define REG_PARM_STACK_SPACE */
-
-/* Value is the number of bytes of arguments automatically
- popped when returning from a subroutine call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
- SIZE is the number of bytes of arguments passed on the stack. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0.
-
- On 29k the value is found in gr96. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), R_GR (96))
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, R_GR (96))
-
-/* 1 if N is a possible register number for a function value
- as seen by the caller.
- On 29k, gr96-gr111 are used. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == R_GR (96))
-
-/* 1 if N is a possible register number for function argument passing.
- On 29k, these are lr2-lr17. */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) <= R_LR (17) && (N) >= R_LR (2))
-\f
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go.
-
- On 29k, this is a single integer, which is a number of words
- of arguments scanned so far.
- Thus 16 or more means all following args should go on the stack. */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0. */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
-
-/* Same, but called for incoming args.
-
- On the 29k, we use this to set all argument registers to fixed and
- set the last 16 local regs, less two, (lr110-lr125) to available. Some
- will later be changed to call-saved by FUNCTION_INCOMING_ARG.
- lr126,lr127 are always fixed, they are place holders for the caller's
- lr0,lr1. */
-
-#define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
-{ int i; \
- for (i = R_AR (0) - 2; i < R_AR (16); i++) \
- { \
- fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; \
- SET_HARD_REG_BIT (fixed_reg_set, i); \
- SET_HARD_REG_BIT (call_used_reg_set, i); \
- SET_HARD_REG_BIT (call_fixed_reg_set, i); \
- } \
- for (i = R_LR (110); i < R_LR (126); i++) \
- { \
- fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0; \
- CLEAR_HARD_REG_BIT (fixed_reg_set, i); \
- CLEAR_HARD_REG_BIT (call_used_reg_set, i); \
- CLEAR_HARD_REG_BIT (call_fixed_reg_set, i); \
- } \
- (CUM) = 0; \
- }
-
-/* Define intermediate macro to compute the size (in registers) of an argument
- for the 29k. */
-
-#define A29K_ARG_SIZE(MODE, TYPE, NAMED) \
-(! (NAMED) ? 0 \
- : (MODE) != BLKmode \
- ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
- : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.) */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- if (MUST_PASS_IN_STACK (MODE, TYPE)) \
- (CUM) = 16; \
- else \
- (CUM) += A29K_ARG_SIZE (MODE, TYPE, NAMED)
-
-/* Determine where to put an argument to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis).
-
- On 29k the first 16 words of args are normally in registers
- and the rest are pushed. */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \
- ? gen_rtx_REG ((MODE), R_LR (2) + (CUM)) : 0)
-
-/* Define where a function finds its arguments.
- This is different from FUNCTION_ARG because of register windows.
-
- On the 29k, we hack this to call a function that sets the used registers
- as non-fixed and not used by calls. */
-
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
-((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \
- ? gen_rtx_REG (MODE, \
- incoming_reg (CUM, A29K_ARG_SIZE (MODE, TYPE, NAMED))) \
- : 0)
-
-/* This indicates that an argument is to be passed with an invisible reference
- (i.e., a pointer to the object is passed).
-
- On the 29k, we do this if it must be passed on the stack. */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
- (MUST_PASS_IN_STACK (MODE, TYPE))
-
-/* Specify the padding direction of arguments.
-
- On the 29k, we must pad upwards in order to be able to pass args in
- registers. */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE) upward
-
-/* For an arg passed partly in registers and partly in memory,
- this is the number of registers used.
- For args passed entirely in registers or entirely in memory, zero. */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-((CUM) < 16 && 16 < (CUM) + A29K_ARG_SIZE (MODE, TYPE, NAMED) && (NAMED) \
- ? 16 - (CUM) : 0)
-
-/* Perform any needed actions needed for a function that is receiving a
- variable number of arguments.
-
- CUM is as above.
-
- MODE and TYPE are the mode and type of the current parameter.
-
- PRETEND_SIZE is a variable that should be set to the amount of stack
- that must be pushed by the prolog to pretend that our caller pushed
- it.
-
- Normally, this macro will push all remaining incoming registers on the
- stack and set PRETEND_SIZE to the length of the registers pushed. */
-
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
-{ if ((CUM) < 16) \
- { \
- int first_reg_offset = (CUM); \
- \
- if (MUST_PASS_IN_STACK (MODE, TYPE)) \
- first_reg_offset += A29K_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1); \
- \
- if (first_reg_offset > 16) \
- first_reg_offset = 16; \
- \
- if (! (NO_RTL) && first_reg_offset != 16) \
- move_block_from_reg \
- (R_AR (0) + first_reg_offset, \
- gen_rtx_MEM (BLKmode, virtual_incoming_args_rtx), \
- 16 - first_reg_offset, (16 - first_reg_offset) * UNITS_PER_WORD); \
- PRETEND_SIZE = (16 - first_reg_offset) * UNITS_PER_WORD; \
- } \
-}
-
-/* Define the information needed to generate branch and scc insns. This is
- stored from the compare operation. Note that we can't use "rtx" here
- since it hasn't been defined! */
-
-extern struct rtx_def *a29k_compare_op0, *a29k_compare_op1;
-extern int a29k_compare_fp_p;
-
-/* This macro produces the initial definition of a function name.
-
- For the 29k, we need the prolog to contain one or two words prior to
- the declaration of the function name. So just store away the name and
- write it as part of the prolog. This also computes the register names,
- which can't be done until after register allocation, but must be done
- before final_start_function is called. */
-
-extern const char *a29k_function_name;
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
- a29k_function_name = NAME; \
- a29k_compute_reg_names ();
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Define the number of delay slots needed for the function epilogue.
-
- On the 29k, we need a slot except when we have a register stack adjustment,
- have a memory stack adjustment, and have no frame pointer. */
-
-#define DELAY_SLOTS_FOR_EPILOGUE \
- (! (needs_regstack_p () \
- && (get_frame_size () + current_function_pretend_args_size \
- + current_function_outgoing_args_size) != 0 \
- && ! frame_pointer_needed))
-
-/* Define whether INSN can be placed in delay slot N for the epilogue.
-
- On the 29k, we must be able to place it in a delay slot, it must
- not use sp if the frame pointer cannot be eliminated, and it cannot
- use local regs if we need to push the register stack.
- If this is a SET with a memory as source, it might load from
- a stack slot, unless the address is constant. */
-
-#define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
- (get_attr_in_delay_slot (INSN) == IN_DELAY_SLOT_YES \
- && ! (frame_pointer_needed \
- && reg_mentioned_p (stack_pointer_rtx, PATTERN (INSN))) \
- && ! (needs_regstack_p () && uses_local_reg_p (PATTERN (INSN))) \
- && (GET_CODE (PATTERN (INSN)) != SET \
- || GET_CODE (SET_SRC (PATTERN (INSN))) != MEM \
- || ! rtx_varies_p (XEXP (SET_SRC (PATTERN (INSN)), 0), 0)))
-\f
-/* Output assembler code for a block containing the constant parts
- of a trampoline, leaving space for the variable parts.
-
- The trampoline should set the static chain pointer to value placed
- into the trampoline and should branch to the specified routine. We
- use gr121 (tav) as a temporary. */
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
-{ \
- fprintf (FILE, "\tconst %s,0\n", reg_names[R_TAV]); \
- fprintf (FILE, "\tconsth %s,0\n", reg_names[R_TAV]); \
- fprintf (FILE, "\tconst %s,0\n", reg_names[R_SLP]); \
- fprintf (FILE, "\tjmpi %s\n", reg_names[R_TAV]); \
- fprintf (FILE, "\tconsth %s,0\n", reg_names[R_SLP]); \
-}
-
-/* Length in units of the trampoline for entering a nested function. */
-
-#define TRAMPOLINE_SIZE 20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function.
-
- We do this on the 29k by writing the bytes of the addresses into the
- trampoline one byte at a time. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- INITIALIZE_TRAMPOLINE_VALUE (TRAMP, FNADDR, 0, 4); \
- INITIALIZE_TRAMPOLINE_VALUE (TRAMP, CXT, 8, 16); \
-}
-
-/* Define a sub-macro to initialize one value into the trampoline.
- We specify the offsets of the CONST and CONSTH instructions, respectively
- and copy the value a byte at a time into these instructions. */
-
-#define INITIALIZE_TRAMPOLINE_VALUE(TRAMP, VALUE, CONST, CONSTH) \
-{ \
- rtx _addr, _temp; \
- rtx _val = force_reg (SImode, VALUE); \
- \
- _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 3)); \
- emit_move_insn (gen_rtx_MEM (QImode, _addr), \
- gen_lowpart (QImode, _val)); \
- \
- _temp = expand_shift (RSHIFT_EXPR, SImode, _val, \
- build_int_2 (8, 0), 0, 1); \
- _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 1)); \
- emit_move_insn (gen_rtx_MEM (QImode, _addr), \
- gen_lowpart (QImode, _temp)); \
- \
- _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \
- build_int_2 (8, 0), _temp, 1); \
- _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 3)); \
- emit_move_insn (gen_rtx_MEM (QImode, _addr), \
- gen_lowpart (QImode, _temp)); \
- \
- _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \
- build_int_2 (8, 0), _temp, 1); \
- _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 1)); \
- emit_move_insn (gen_rtx_MEM (QImode, _addr), \
- gen_lowpart (QImode, _temp)); \
-}
-\f
-/* Addressing modes, and classification of registers for them. */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) 0
-#define REGNO_OK_FOR_BASE_P(REGNO) 1
-
-/* Given the value returned from get_frame_size, compute the actual size
- of the frame we will allocate. We include the pretend and outgoing
- arg sizes and round to a doubleword. */
-
-#define ACTUAL_FRAME_SIZE(SIZE) \
- (((SIZE) + current_function_pretend_args_size \
- + current_function_outgoing_args_size + 7) & ~7)
-
-/* Define the initial offset between the frame and stack pointer. */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
- (DEPTH) = ACTUAL_FRAME_SIZE (get_frame_size ())
-\f
-/* Maximum number of registers that can appear in a valid memory address. */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) \
-(GET_CODE (X) == CONST_INT && (unsigned) INTVAL (X) < 0x100)
-
-/* Include all constant integers and constant doubles */
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) 0
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) 1
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- On the 29k, a legitimate address is a register and so is a
- constant of less than 256. */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
- goto ADDR; \
- if (GET_CODE (X) == CONST_INT \
- && (unsigned) INTVAL (X) < 0x100) \
- goto ADDR; \
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output.
-
- For the 29k, we need not do anything. However, if we don't,
- `memory_address' will try lots of things to get a valid address, most of
- which will result in dead code and extra pseudos. So we make the address
- valid here.
-
- This is easy: The only valid addresses are an offset from a register
- and we know the address isn't valid. So just call either `force_operand'
- or `force_reg' unless this is a (plus (reg ...) (const_int 0)). */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
-{ if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx) \
- X = XEXP (x, 0); \
- if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS) \
- X = force_operand (X, 0); \
- else \
- X = force_reg (Pmode, X); \
- goto WIN; \
-}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for.
- On the 29k this is never true. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* Compute the cost of an address. For the 29k, all valid addresses are
- the same cost. */
-
-#define ADDRESS_COST(X) 0
-
-/* Define this if some processing needs to be done immediately before
- emitting code for an insn. */
-
-/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
-\f
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this as 1 if `char' should by default be signed; else as 0. */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
- also convert validly to an unsigned one.
-
- We actually lie a bit here as overflow conditions are different. But
- they aren't being checked anyway. */
-
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move to of from memory
- in one reasonably fast instruction.
-
- For the 29k, we will define movti, so put this at 4 words. */
-#define MOVE_MAX 16
-
-/* Largest number of bytes of an object that can be placed in a register.
- On the 29k we have plenty of registers, so use TImode. */
-#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
-
-/* Nonzero if access to memory by bytes is no faster than for words.
- Also non-zero if doing byte operations (specifically shifts) in registers
- is undesirable.
-
- On the 29k, large masks are expensive, so we want to use bytes to
- manipulate fields. */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if operations between registers always perform the operation
- on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
- will either zero-extend or sign-extend. The value of this macro should
- be the code that says which one of the two operations is implicitly
- done, NIL if none. */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Define if the object format being used is COFF or a superset. */
-#define OBJECT_FORMAT_COFF
-
-/* This uses COFF, so it wants SDB format. */
-#define SDB_DEBUGGING_INFO
-
-/* Define this to be the delimiter between SDB sub-sections. The default
- is ";". */
-#define SDB_DELIM "\n"
-
-/* Do not break .stabs pseudos into continuations. */
-#define DBX_CONTIN_LENGTH 0
-
-/* Don't try to use the `x' type-cross-reference character in DBX data.
- Also has the consequence of putting each struct, union or enum
- into a separate .stabs, containing only cross-refs to the others. */
-#define DBX_NO_XREFS
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
- and some other value for true. This is the value stored for true, which
- is just the sign bit. */
-
-#define STORE_FLAG_VALUE (-2147483647 - 1)
-
-/* Specify the machine mode that pointers have.
- After generation of rtl, the compiler makes no further distinction
- between pointers and any other objects of this machine mode. */
-#define Pmode SImode
-
-/* Mode of a function address in a call instruction (for indexing purposes).
-
- Doesn't matter on 29k. */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
- shouldn't be put through pseudo regs where they can be cse'd.
- Desirable on machines where ordinary constants are expensive
- but a CALL with constant address is cheap. */
-#define NO_FUNCTION_CSE
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
- few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch.
-
- We only care about the cost if it is valid in an insn. The only
- constants that cause an insn to generate more than one machine
- instruction are those involving floating-point or address. So
- only these need be expensive. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST_INT: \
- return 0; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 6; \
- case CONST_DOUBLE: \
- return GET_MODE (RTX) == SFmode ? 6 : 8;
-
-/* Provide the costs of a rtl expression. This is in the body of a
- switch on CODE.
-
- All MEMs cost the same if they are valid. This is used to ensure
- that (mem (symbol_ref ...)) is placed into a CALL when valid.
-
- The multiply cost depends on whether this is a 29050 or not. */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE) \
- case MULT: \
- return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40); \
- case DIV: \
- case UDIV: \
- case MOD: \
- case UMOD: \
- return COSTS_N_INSNS (50); \
- case MEM: \
- return COSTS_N_INSNS (2);
-\f
-/* Control the assembler format that we output. */
-
-/* Output at beginning of assembler file. */
-
-#define ASM_FILE_START(FILE) \
-{ const char *p, *after_dir = main_input_filename; \
- if (TARGET_29050) \
- fprintf (FILE, "\t.cputype 29050\n"); \
- for (p = main_input_filename; *p; p++) \
- if (*p == '/') \
- after_dir = p + 1; \
- fprintf (FILE, "\t.file "); \
- output_quoted_string (FILE, after_dir); \
- fprintf (FILE, "\n"); \
- fprintf (FILE, "\t.sect .lit,lit\n"); }
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#define ASM_APP_OFF ""
-
-/* The next few macros don't have tabs on most machines, but
- at least one 29K assembler wants them. */
-
-/* Output before instructions. */
-
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-/* Output before read-only data. */
-
-#define READONLY_DATA_SECTION_ASM_OP "\t.use .lit"
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
-
-#define REGISTER_NAMES \
-{"gr96", "gr97", "gr98", "gr99", "gr100", "gr101", "gr102", "gr103", "gr104", \
- "gr105", "gr106", "gr107", "gr108", "gr109", "gr110", "gr111", "gr112", \
- "gr113", "gr114", "gr115", "gr116", "gr117", "gr118", "gr119", "gr120", \
- "gr121", "gr122", "gr123", "gr124", "gr125", "gr126", "gr127", \
- "lr0", "lr1", "lr2", "lr3", "lr4", "lr5", "lr6", "lr7", "lr8", "lr9", \
- "lr10", "lr11", "lr12", "lr13", "lr14", "lr15", "lr16", "lr17", "lr18", \
- "lr19", "lr20", "lr21", "lr22", "lr23", "lr24", "lr25", "lr26", "lr27", \
- "lr28", "lr29", "lr30", "lr31", "lr32", "lr33", "lr34", "lr35", "lr36", \
- "lr37", "lr38", "lr39", "lr40", "lr41", "lr42", "lr43", "lr44", "lr45", \
- "lr46", "lr47", "lr48", "lr49", "lr50", "lr51", "lr52", "lr53", "lr54", \
- "lr55", "lr56", "lr57", "lr58", "lr59", "lr60", "lr61", "lr62", "lr63", \
- "lr64", "lr65", "lr66", "lr67", "lr68", "lr69", "lr70", "lr71", "lr72", \
- "lr73", "lr74", "lr75", "lr76", "lr77", "lr78", "lr79", "lr80", "lr81", \
- "lr82", "lr83", "lr84", "lr85", "lr86", "lr87", "lr88", "lr89", "lr90", \
- "lr91", "lr92", "lr93", "lr94", "lr95", "lr96", "lr97", "lr98", "lr99", \
- "lr100", "lr101", "lr102", "lr103", "lr104", "lr105", "lr106", "lr107", \
- "lr108", "lr109", "lr110", "lr111", "lr112", "lr113", "lr114", "lr115", \
- "lr116", "lr117", "lr118", "lr119", "lr120", "lr121", "lr122", "lr123", \
- "lr124", "lr125", "lr126", "lr127", \
- "AI0", "AI1", "AI2", "AI3", "AI4", "AI5", "AI6", "AI7", "AI8", "AI9", \
- "AI10", "AI11", "AI12", "AI13", "AI14", "AI15", "FP", \
- "bp", "fc", "cr", "q", \
- "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", \
- "pc0", "pc1", "pc2", "mmu", "lru", "fpe", "int", "fps", "exo", \
- "0", "1", "2", "3", \
- "gr64", "gr65", "gr66", "gr67", "gr68", "gr69", "gr70", "gr71", \
- "gr72", "gr73", "gr74", "gr75", "gr76", "gr77", "gr78", "gr79", \
- "gr80", "gr81", "gr82", "gr83", "gr84", "gr85", "gr86", "gr87", \
- "gr88", "gr89", "gr90", "gr91", "gr92", "gr93", "gr94", "gr95" }
-
-/* How to renumber registers for dbx and gdb. */
-
-extern int a29k_debug_reg_map[FIRST_PSEUDO_REGISTER];
-#define DBX_REGISTER_NUMBER(REGNO) a29k_debug_reg_map[REGNO]
-
-/* Switch into a generic section. */
-#define TARGET_ASM_NAMED_SECTION a29k_asm_named_section
-
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
- do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a label for a jump table. Arguments are the same as
- for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
- passed. */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
-{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* This is how to store into the string LABEL
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tsub %s,%s,4\n\tstore 0,0,%s,%s\n", \
- reg_names[R_MSP], reg_names[R_MSP], reg_names[REGNO], \
- reg_names[R_MSP]);
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tload 0,0,%s,%s\n\tadd %s,%s,4\n", \
- reg_names[REGNO], reg_names[R_MSP], reg_names[R_MSP], \
- reg_names[R_MSP]);
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- fprintf (FILE, "\t.word L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
- Don't define this if it is not supported. */
-
-/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG) != 0) \
- fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\t.block %d\n", (SIZE))
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
-( fputs ("\t.lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
- CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
- For `%' followed by punctuation, CODE is the punctuation and X is null. */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
-
-/* Determine which codes are valid without a following integer. These must
- not be alphabetic.
-
- We support `#' which is null if a delay slot exists, otherwise
- "\n\tnop" and `*' which prints the register name for TPC (gr122). */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#' || (CODE) == '*')
-\f
-/* Print a memory address as an operand to reference that memory location. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-{ register rtx addr = ADDR; \
- if (!REG_P (addr) \
- && ! (GET_CODE (addr) == CONST_INT \
- && INTVAL (addr) >= 0 && INTVAL (addr) < 256)) \
- abort (); \
- output_operand (addr, 0); \
-}
-/* Define the codes that are matched by predicates in a29k.c. */
-
-#define PREDICATE_CODES \
- {"cint_8_operand", {CONST_INT}}, \
- {"cint_16_operand", {CONST_INT}}, \
- {"long_const_operand", {CONST_INT, CONST, CONST_DOUBLE, \
- LABEL_REF, SYMBOL_REF}}, \
- {"const_0_operand", {CONST_INT, ASHIFT}}, \
- {"const_8_operand", {CONST_INT, ASHIFT}}, \
- {"const_16_operand", {CONST_INT, ASHIFT}}, \
- {"const_24_operand", {CONST_INT, ASHIFT}}, \
- {"float_const_operand", {CONST_DOUBLE}}, \
- {"gpc_reg_operand", {SUBREG, REG}}, \
- {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
- {"gpc_reg_or_integer_constant_operand", {SUBREG, REG, \
- CONST_INT, CONST_DOUBLE}}, \
- {"gpc_reg_or_immediate_operand", {SUBREG, REG, CONST_INT, \
- CONST_DOUBLE, CONST, \
- SYMBOL_REF, LABEL_REF}}, \
- {"spec_reg_operand", {REG}}, \
- {"accum_reg_operand", {REG}}, \
- {"srcb_operand", {SUBREG, REG, CONST_INT}}, \
- {"cmplsrcb_operand", {SUBREG, REG, CONST_INT}}, \
- {"reg_or_immediate_operand", {SUBREG, REG, CONST_INT, CONST, \
- CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}}, \
- {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
- {"and_operand", {SUBREG, REG, CONST_INT}}, \
- {"add_operand", {SUBREG, REG, CONST_INT}}, \
- {"call_operand", {SYMBOL_REF, CONST_INT}}, \
- {"in_operand", {SUBREG, MEM, REG, CONST_INT, CONST, SYMBOL_REF, \
- LABEL_REF, CONST_DOUBLE}}, \
- {"out_operand", {SUBREG, REG, MEM}}, \
- {"reload_memory_operand", {SUBREG, REG, MEM}}, \
- {"fp_comparison_operator", {EQ, GT, GE}}, \
- {"branch_operator", {GE, LT}}, \
- {"load_multiple_operation", {PARALLEL}}, \
- {"store_multiple_operation", {PARALLEL}}, \
- {"epilogue_operand", {CODE_LABEL}},
+++ /dev/null
-;;- Machine description for AMD Am29000 for GNU C compiler
-;; Copyright (C) 1991, 1992, 1994, 1998, 1999, 2001
-;; Free Software Foundation, Inc.
-;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; The insns in this file are presented in the same order as the AMD 29000
-;; User's Manual (i.e., alphabetical by machine op-code).
-;;
-;; DEFINE_EXPAND's are located near the first occurrence of the major insn
-;; that they generate.
-\f
-;; The only attribute we have is the type. We only care about calls, branches,
-;; loads, stores, floating-point operations, and multi-word insns.
-;; Everything else is miscellaneous.
-
-(define_attr "type"
- "call,branch,load,store,fadd,fmul,fam,fdiv,fsqrt,dmul,dam,ddiv,dsqrt,multi,misc"
- (const_string "misc"))
-
-;; ASM insns cannot go into a delay slot, so call them "multi".
-(define_asm_attributes [(set_attr "type" "multi")])
-
-(define_attr "in_delay_slot" "yes,no"
- (if_then_else (eq_attr "type" "call,branch,multi") (const_string "no")
- (const_string "yes")))
-
-;; Branch and call insns require a single delay slot. Annulling is not
-;; supported.
-(define_delay (eq_attr "type" "call,branch")
- [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
-
-;; Define the function unit usages. We first define memory as a unit.
-(define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 5
- [(eq_attr "type" "load")])
-(define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 6
- [(eq_attr "type" "store")])
-(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
-
-;; Now define the function units for the floating-point support. Most
-;; units are pipelined and can accept an input every cycle.
-;;
-;; Note that we have an inaccuracy here. If a fmac insn is issued, followed
-;; 2 cycles later by a fadd, there will be a conflict for the floating
-;; adder that we can't represent. Also, all insns will conflict for the
-;; floating-point rounder. It isn't clear how to represent this.
-
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0)
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 4)
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 0)
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 4)
-
-(define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0)
-
-(define_function_unit "divider" 1 0 (eq_attr "type" "fdiv") 11 10)
-(define_function_unit "divider" 1 0 (eq_attr "type" "fsqrt") 28 27)
-(define_function_unit "divider" 1 0 (eq_attr "type" "ddiv") 18 17)
-(define_function_unit "divider" 1 0 (eq_attr "type" "dsqrt") 57 56)
-\f
-;; ADD
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "add_operand" "rI,N")))]
- ""
- "@
- add %0,%1,%2
- sub %0,%1,%n2")
-
-(define_insn "adddi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
- ""
- "add %L0,%L1,%L2\;addc %0,%1,%2"
- [(set_attr "type" "multi")])
-
-;; AND/ANDN
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "and_operand" "rI,K")))]
- ""
- "@
- and %0,%1,%2
- andn %0,%1,%C2")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
- ""
- "@
- andn %0,%2,%1
- nor %0,%1,%C2")
-\f
-;; CALLI
-;;
-;; Each call pattern is duplicated so that we can add CLOBBERs to the
-;; resulting insn.
-;;
-;; We indicate that LR0 is clobbered in the CALL_INSN itself. Otherwise,
-;; reorg will think it is just clobbered by the called function.
-
-(define_expand "call"
- [(use (match_operand:SI 0 "" ""))
- (use (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))]
- ""
- "
-{ rtx insn = emit_call_insn (gen_call_internal (operands[0], operands[1]));
- a29k_clobbers_to (insn, operands[2]);
-
- DONE;
-}")
-
-(define_expand "call_internal"
- [(parallel [(call (match_operand:SI 0 "" "")
- (match_operand 1 "" ""))
- (clobber (scratch:SI))])]
- ""
- "
-{
- if (GET_CODE (operands[0]) != MEM)
- abort ();
-
- /* We tell here whether this is a recursive call, since this insn may
- later be inlined into another function. */
- if (! TARGET_SMALL_MEMORY
- && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
- operands[0] = gen_rtx_MEM (SImode,
- force_reg (Pmode, XEXP (operands[0], 0)));
-}")
-
-(define_expand "call_value"
- [(use (match_operand:SI 0 "gpc_reg_operand" ""))
- (use (match_operand:SI 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))]
- ""
- "
-{ rtx insn = emit_call_insn (gen_call_value_internal (operands[0], operands[1],
- operands[2]));
-
- a29k_clobbers_to (insn, operands[3]);
- DONE;
-}")
-
-(define_expand "call_value_internal"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (call (match_operand:SI 1 "" "")
- (match_operand 2 "" "")))
- (clobber (scratch:SI))])]
- ""
- "
-{
- if (GET_CODE (operands[1]) != MEM)
- abort ();
-
- /* We tell here whether this is a recursive call, since this insn may
- later be inlined into another function. */
- if (! TARGET_SMALL_MEMORY
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
- operands[1] = gen_rtx_MEM (SImode,
- force_reg (Pmode, XEXP (operands[1], 0)));
-}")
-
-(define_insn ""
- [(call (match_operand:SI 0 "memory_operand" "m")
- (match_operand 1 "" ""))
- (clobber (match_scratch:SI 2 "=&l"))]
- "GET_CODE (XEXP (operands[0], 0)) != CONST_INT"
- "calli lr0,%0%#"
- [(set_attr "type" "call")])
-
-(define_insn ""
- [(call (mem:SI (match_operand:SI 0 "call_operand" "i"))
- (match_operand:SI 1 "general_operand" "g"))
- (clobber (match_scratch:SI 2 "=&l"))]
- ""
- "call lr0,%F0"
- [(set_attr "type" "call")])
-
-(define_insn ""
- [(set (match_operand 0 "gpc_reg_operand" "=r")
- (call (match_operand:SI 1 "memory_operand" "m")
- (match_operand 2 "" "")))
- (clobber (match_scratch:SI 3 "=&l"))]
- "GET_CODE (XEXP (operands[1], 0)) != CONST_INT"
- "calli lr0,%1%#"
- [(set_attr "type" "call")])
-
-(define_insn ""
- [(set (match_operand 0 "gpc_reg_operand" "=r")
- (call (mem:SI (match_operand:SI 1 "call_operand" "i"))
- (match_operand:SI 2 "general_operand" "g")))
- (clobber (match_scratch:SI 3 "=&l"))]
- ""
- "call lr0,%F1"
- [(set_attr "type" "call")])
-
-(define_expand "probe"
- [(call (mem:SI (symbol_ref:SI "_msp_check"))
- (const_int 1))]
- "TARGET_STACK_CHECK"
- "")
-
-;; This is used for internal routine calls via TPC. Currently used only
-;; in probe, above.
-(define_insn ""
- [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s"))
- (const_int 1))]
- ""
- "call %*,%0"
- [(set_attr "type" "call")])
-\f
-;; CONST, CONSTH, CONSTN
-;;
-;; Many of these are generated from move insns.
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (and:SI (match_operand:SI 1 "immediate_operand" "i")
- (const_int 65535)))]
- ""
- "const %0,%1")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 16)
- (match_operand:SI 1 "const_0_operand" ""))
- (ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i")
- (const_int 16)))]
- ""
- "consth %0,%2")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 16)
- (match_operand:SI 1 "const_0_operand" ""))
- (match_operand:SI 2 "cint_16_operand" "J"))]
- ""
- "consth %0,%m2")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
- (match_operand:SI 2 "const_int_operand" "n")))]
- "(INTVAL (operands[2]) & 0xffff) == 0"
- "consth %0,%2")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
- (and:SI (match_operand:SI 2 "immediate_operand" "i")
- (const_int -65536))))]
- ""
- "consth %0,%2")
-\f
-;; CONVERT
-(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (fix:SI (match_operand:SF 1 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,0,3,0,1")
-
-(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (fix:SI (match_operand:DF 1 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,0,3,0,2")
-
-(define_insn "fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,1,3,0,1")
-
-(define_insn "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,1,3,0,2")
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,0,4,1,2")
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,0,4,2,1")
-
-(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,0,4,1,0")
-
-(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,0,4,2,0")
-
-(define_insn "floatunssisf2"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,1,4,1,0")
-
-(define_insn "floatunssidf2"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "convert %0,%1,1,4,2,0")
-\f
-;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (match_operator:SI 3 "comparison_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "srcb_operand" "rI")]))]
- ""
- "cp%J3 %0,%1,%2")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (match_operator:SI 3 "fp_comparison_operator"
- [(match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r")]))]
- "! TARGET_SOFT_FLOAT"
- "f%J3 %0,%1,%2"
- [(set_attr "type" "fadd")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (match_operator:SI 3 "fp_comparison_operator"
- [(match_operand:DF 1 "register_operand" "r")
- (match_operand:DF 2 "register_operand" "r")]))]
- "! TARGET_SOFT_FLOAT"
- "d%J3 %0,%1,%2"
- [(set_attr "type" "fadd")])
-\f
-;; DADD
-(define_expand "adddf3"
- [(set (match_operand:DF 0 "register_operand" "")
- (plus:DF (match_operand:DF 1 "register_operand" "")
- (match_operand:DF 2 "register_operand" "")))]
- "! TARGET_SOFT_FLOAT"
- "")
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (plus:DF (match_operand:DF 1 "register_operand" "%r")
- (match_operand:DF 2 "register_operand" "r")))]
- "! TARGET_29050 "
- "dadd %0,%1,%2"
- [(set_attr "type" "fadd")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r,a")
- (plus:DF (match_operand:DF 1 "register_operand" "%r,r")
- (match_operand:DF 2 "register_operand" "r,0")))]
- "TARGET_29050"
- "@
- dadd %0,%1,%2
- dmac 8,%0,%1,%1"
- [(set_attr "type" "fadd,dam")])
-
-;; DDIV
-(define_insn "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (div:DF (match_operand:DF 1 "register_operand" "=r")
- (match_operand:DF 2 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "ddiv %0,%1,%2"
- [(set_attr "type" "ddiv")])
-\f
-;; DIVIDE
-;;
-;; We must set Q to the sign extension of the dividend first. For MOD, we
-;; must get the remainder from Q.
-;;
-;; For divmod: operand 1 is divided by operand 2; quotient goes to operand
-;; 0 and remainder to operand 3.
-(define_expand "divmodsi4"
- [(set (match_dup 4)
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (const_int 31)))
- (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (div:SI (match_dup 1)
- (match_operand:SI 2 "gpc_reg_operand" "")))
- (set (match_operand:SI 3 "gpc_reg_operand" "")
- (mod:SI (match_dup 1)
- (match_dup 2)))
- (use (match_dup 4))])]
- ""
- "
-{
- operands[4] = gen_reg_rtx (SImode);
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (set (match_operand:SI 3 "register_operand" "=q")
- (mod:SI (match_dup 1)
- (match_dup 2)))
- (use (match_operand:SI 4 "register_operand" "3"))]
- ""
- "divide %0,%1,%2")
-\f
-;; DIVIDU
-;;
-;; Similar to DIVIDE.
-(define_expand "udivmodsi4"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "gpc_reg_operand" "")))
- (set (match_operand:SI 3 "gpc_reg_operand" "")
- (umod:SI (match_dup 1)
- (match_dup 2)))
- (use (const_int 0))])]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (set (match_operand:SI 3 "register_operand" "=q")
- (umod:SI (match_dup 1)
- (match_dup 2)))
- (use (match_operand:SI 4 "const_int_operand" "3"))]
- ""
- "dividu %0,%1,%2")
-\f
-;; DMAC/DMSM
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=a,*r")
- (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A")
- (match_operand:DF 2 "register_operand" "r,r"))
- (match_operand:DF 3 "register_operand" "0,*r")))]
- "TARGET_29050"
- "@
- dmac 0,%0,%1,%2
- dmsm %0,%2,%3"
- [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=a")
- (plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "r"))
- (match_operand:DF 3 "register_operand" "0")))]
- "TARGET_29050"
- "dmac 1,%0,%2,%1"
- [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=a")
- (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r")
- (match_operand:DF 2 "register_operand" "r"))
- (match_operand:DF 3 "register_operand" "0")))]
- "TARGET_29050"
- "dmac 2,%0,%1,%2"
- [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=a")
- (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r")
- (neg:DF (match_operand:DF 2 "register_operand" "r")))
- (match_operand:DF 3 "register_operand" "0")))]
- "TARGET_29050"
- "dmac 3,%0,%1,%2"
- [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=a")
- (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "r")))]
- "TARGET_29050"
- "dmac 5,%0,%2,%1"
- [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=a")
- (minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "0")))]
- "TARGET_29050"
- "dmac 11,%0,%1,%1"
- [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=a")
- (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r")
- (match_operand:DF 2 "register_operand" "0"))))]
- "TARGET_29050"
- "dmac 11,%0,%1,%1"
- [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r,r,a")
- (neg:DF (match_operand:DF 1 "register_operand" "0,r,r")))
- (clobber (match_scratch:SI 2 "=&r,&r,X"))]
- "TARGET_29050"
- "@
- cpeq %2,gr1,gr1\;xor %0,%1,%2
- cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0
- dmac 13,%0,%1,%1"
- [(set_attr "type" "multi,multi,dam")])
-
-;; DMUL
-(define_expand "muldf3"
- [(set (match_operand:DF 0 "register_operand" "")
- (mult:DF (match_operand:DF 1 "register_operand" "")
- (match_operand:DF 2 "register_operand" "")))]
- "! TARGET_SOFT_FLOAT"
- "")
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (match_operand:DF 1 "register_operand" "%r")
- (match_operand:DF 2 "register_operand" "r")))]
- "! TARGET_29050"
- "dmul %0,%1,%2"
- [(set_attr "type" "dmul")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r,a")
- (mult:DF (match_operand:DF 1 "register_operand" "%r,r")
- (match_operand:DF 2 "register_operand" "r,r")))]
- "TARGET_29050"
- "@
- dmul %0,%1,%2
- dmac 4,%0,%1,%2"
- [(set_attr "type" "dmul,dam")])
-
-;; DSUB
-(define_expand "subdf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (match_operand:DF 1 "register_operand" "r")
- (match_operand:DF 2 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "")
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (match_operand:DF 1 "register_operand" "r")
- (match_operand:DF 2 "register_operand" "r")))]
- "! TARGET_29050"
- "dsub %0,%1,%2"
- [(set_attr "type" "fadd")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r,a,a")
- (minus:DF (match_operand:DF 1 "register_operand" "r,0,r")
- (match_operand:DF 2 "register_operand" "r,r,0")))]
- "TARGET_29050"
- "@
- dsub %0,%1,%2
- dmac 9,%0,%2,%2
- dmac 10,%0,%1,%1"
- [(set_attr "type" "fadd,dam,dam")])
-\f
-;; EXBYTE
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
- (const_int -256))
- (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 8)
- (ashift:PSI
- (match_operand:PSI 3 "register_operand" "b")
- (const_int 3)))))]
- ""
- "exbyte %0,%2,%1")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 8)
- (ashift:PSI
- (match_operand:PSI 2 "register_operand" "b")
- (const_int 3))))]
- ""
- "exbyte %0,%1,0")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 8)
- (match_operand:PSI 1 "const_24_operand" ""))
- (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 8)
- (ashift:PSI
- (match_operand:PSI 3 "register_operand" "b")
- (const_int 3))))]
- ""
- "exbyte %0,%2,%0")
-
-(define_expand "extzv"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "general_operand" "")
- (match_operand:SI 3 "general_operand" "")))]
- ""
- "
-{
- int size, pos;
-
- if (GET_CODE (operands[2]) != CONST_INT
- || GET_CODE (operands[3]) != CONST_INT)
- FAIL;
-
- size = INTVAL (operands[2]);
- pos = INTVAL (operands[3]);
-
- /* Can't do this unless a byte extraction. If extracting the high
- or low byte, don't do this because a shift or AND is shorter.
- Don't do 16-bit extracts, since the only two are the high and low
- ends, and it is faster to do them with CONSTH and SRL. */
-
- if (size != 8 || (pos != 8 && pos != 16))
- FAIL;
-
- operands[3] = gen_rtx_ASHIFT (PSImode,
- force_reg (PSImode, GEN_INT (pos / 8)),
- GEN_INT (3));
-
-}")
-
-;; EXHW
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
- (const_int -65536))
- (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)
- (ashift:PSI
- (match_operand:PSI 3 "register_operand" "b")
- (const_int 3)))))]
- ""
- "exhw %0,%2,%1")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 16)
- (ashift:PSI
- (match_operand:PSI 2 "register_operand" "b")
- (const_int 3))))]
- ""
- "exhw %0,%1,0")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 16)
- (match_operand:PSI 1 "const_16_operand" ""))
- (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
- (const_int 16)
- (ashift:PSI
- (match_operand:PSI 3 "register_operand" "b")
- (const_int 3))))]
- ""
- "exhw %0,%2,%0")
-
-;; EXHWS
-;;
-;; This is probably unused. The high-order 16-bits are obtained with an SRA
-;; insn. The low-order 16 bits are a sign-extend, which is a pair of
-;; shifts. Setting BP followed by the insn is equivalent, so we don't
-;; bother going to any trouble to generate this insn.
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 16)
- (ashift:PSI
- (match_operand:PSI 2 "register_operand" "b")
- (const_int 3))))]
- ""
- "exhws %0,%1")
-\f
-;; EXTRACT
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:PSI 2 "register_operand" "f")))]
- ""
- "extract %0,%1,%1")
-
-(define_expand "rotlsi3"
- [(set (match_dup 3)
- (match_operand:SI 2 "gpc_reg_or_immediate_operand" ""))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_dup 3)))]
- ""
- "
-{ operands[2] = gen_lowpart (PSImode, operands[2]);
- operands[3] = gen_reg_rtx (PSImode);
-}")
-
-;; It would be nice to be able to have a define_split corresponding to the
-;; above, but there is no way to tell combine we need a PSImode temporary.
-;; If we put a (clobber (scratch:PSI)) there, combine would merge the above
-;; two insns. This is bad because it then thinks only one insn is needed.
-\f
-;; FADD
-(define_expand "addsf3"
- [(set (match_operand:SF 0 "register_operand" "")
- (plus:SF (match_operand:SF 1 "register_operand" "")
- (match_operand:SF 2 "register_operand" "")))]
- "! TARGET_SOFT_FLOAT"
- "")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r")
- (plus:SF (match_operand:SF 1 "register_operand" "%r")
- (match_operand:SF 2 "register_operand" "r")))]
- "! TARGET_29050"
- "fadd %0,%1,%2"
- [(set_attr "type" "fadd")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r,a")
- (plus:SF (match_operand:SF 1 "register_operand" "%r,r")
- (match_operand:SF 2 "register_operand" "r,0")))]
- "TARGET_29050"
- "@
- fadd %0,%1,%2
- fmac 8,%0,%1,%1"
- [(set_attr "type" "fadd,fam")])
-
-;; FDIV
-(define_insn "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (div:SF (match_operand:SF 1 "register_operand" "=r")
- (match_operand:SF 2 "register_operand" "r")))]
- "! TARGET_SOFT_FLOAT"
- "fdiv %0,%1,%2"
- [(set_attr "type" "fdiv")])
-
-;; FDMUL
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r"))
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
- "! TARGET_SOFT_FLOAT"
- "fdmul %0,%1,%2")
-
-;; FMAC/FMSM
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=a,*r")
- (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A")
- (match_operand:SF 2 "register_operand" "r,r"))
- (match_operand:SF 3 "register_operand" "0,*r")))]
- "TARGET_29050"
- "@
- fmac 0,%0,%1,%2
- fmsm %0,%2,%3"
- [(set_attr "type" "fam")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=a")
- (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:SF 2 "register_operand" "r"))
- (match_operand:SF 3 "register_operand" "0")))]
- "TARGET_29050"
- "fmac 1,%0,%2,%1"
- [(set_attr "type" "fam")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=a")
- (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r")
- (match_operand:SF 2 "register_operand" "r"))
- (match_operand:SF 3 "register_operand" "0")))]
- "TARGET_29050"
- "fmac 2,%0,%1,%2"
- [(set_attr "type" "fam")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=a")
- (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:SF 2 "register_operand" "r"))
- (match_operand:SF 3 "register_operand" "0")))]
- "TARGET_29050"
- "fmac 3,%0,%2,%1"
- [(set_attr "type" "fam")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=a")
- (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:SF 2 "register_operand" "r")))]
- "TARGET_29050"
- "fmac 5,%0,%2,%1"
- [(set_attr "type" "fam")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=a")
- (minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r"))
- (match_operand:SF 2 "register_operand" "0")))]
- "TARGET_29050"
- "fmac 11,%0,%1,%1"
- [(set_attr "type" "fam")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=a")
- (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r")
- (match_operand:SF 2 "register_operand" "0"))))]
- "TARGET_29050"
- "fmac 11,%0,%1,%1"
- [(set_attr "type" "fam")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r,a")
- (neg:SF (match_operand:SF 1 "register_operand" "r,r")))
- (clobber (match_scratch:SI 2 "=&r,X"))]
- "TARGET_29050"
- "@
- cpeq %2,gr1,gr1\;xor %0,%1,%2
- fmac 13,%0,%1,%1"
- [(set_attr "type" "multi,fam")])
-
-;; FMUL
-(define_expand "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "")
- (mult:SF (match_operand:SF 1 "register_operand" "")
- (match_operand:SF 2 "register_operand" "")))]
- "! TARGET_SOFT_FLOAT"
- "")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r")
- (mult:SF (match_operand:SF 1 "register_operand" "%r")
- (match_operand:SF 2 "register_operand" "r")))]
- "! TARGET_29050"
- "fmul %0,%1,%2"
- [(set_attr "type" "fmul")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r,a")
- (mult:SF (match_operand:SF 1 "register_operand" "%r,r")
- (match_operand:SF 2 "register_operand" "r,r")))]
- "TARGET_29050"
- "@
- fmul %0,%1,%2
- fmac 4,%0,%1,%2"
- [(set_attr "type" "fmul,fam")])
-
-;; FSUB
-(define_expand "subsf3"
- [(set (match_operand:SF 0 "register_operand" "")
- (minus:SF (match_operand:SF 1 "register_operand" "")
- (match_operand:SF 2 "register_operand" "")))]
- "! TARGET_SOFT_FLOAT"
- "")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r")
- (minus:SF (match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r")))]
- "! TARGET_29050"
- "fsub %0,%1,%2"
- [(set_attr "type" "fadd")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r,a,a")
- (minus:SF (match_operand:SF 1 "register_operand" "r,0,r")
- (match_operand:SF 2 "register_operand" "r,r,0")))]
- "TARGET_29050"
- "@
- fsub %0,%1,%2
- fmac 9,%0,%2,%2
- fmac 10,%0,%1,%1"
- [(set_attr "type" "fadd,fam,fam")])
-\f
-;; INBYTE
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 8)
- (ashift:PSI
- (match_operand:PSI 2 "register_operand" "b")
- (const_int 3)))
- (match_operand:SI 1 "srcb_operand" "rI"))]
- ""
- "inbyte %0,%0,%1")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI
- (not:SI
- (ashift:SI (const_int 255)
- (ashift:PSI
- (match_operand:PSI 3 "register_operand" "b")
- (const_int 3))))
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (ashift:SI (zero_extend:SI
- (match_operand:QI 2 "srcb_operand" "rI"))
- (ashift:PSI (match_dup 3) (const_int 3)))))]
- ""
- "inbyte %0,%1,%2")
-
-;; INHW
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 16)
- (ashift:PSI
- (match_operand:PSI 2 "register_operand" "b")
- (const_int 3)))
- (match_operand:SI 1 "srcb_operand" "rI"))]
- ""
- "inhw %0,%0,%1")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (and:SI
- (not:SI
- (ashift:SI (const_int 65535)
- (ashift:PSI
- (match_operand:PSI 3 "register_operand" "b")
- (const_int 3))))
- (match_operand:SI 1 "gpc_reg_operand" "r"))
- (ashift:SI (zero_extend:SI
- (match_operand:HI 2 "srcb_operand" "rI"))
- (ashift:PSI (match_dup 3) (const_int 3)))))]
- ""
- "inhw %0,%1,%2")
-
-(define_expand "insv"
- [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "")
- (match_operand:SI 1 "general_operand" "")
- (match_operand:SI 2 "general_operand" ""))
- (match_operand:SI 3 "srcb_operand" ""))]
- ""
- "
-{
- int size, pos;
-
- if (GET_CODE (operands[1]) != CONST_INT
- || GET_CODE (operands[2]) != CONST_INT)
- FAIL;
-
- size = INTVAL (operands[1]);
- pos = INTVAL (operands[2]);
- if ((size != 8 && size != 16) || pos % size != 0)
- FAIL;
-
- operands[2] = gen_rtx_ASHIFT (PSImode,
- force_reg (PSImode, GEN_INT (pos / 8)),
- GEN_INT (3));
-}")
-\f
-;; LOAD (also used by move insn).
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int -4))))
- (set (match_operand:PSI 2 "register_operand" "=b")
- (truncate:PSI (match_dup 1)))]
- "! TARGET_DW_ENABLE"
- "load 0,16,%0,%1"
- [(set_attr "type" "load")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_DW_ENABLE"
- "load 0,1,%0,%1"
- [(set_attr "type" "load")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_DW_ENABLE"
- "load 0,1,%0,%1"
- [(set_attr "type" "load")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
- "TARGET_DW_ENABLE"
- "load 0,2,%0,%1"
- [(set_attr "type" "load")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))
- (clobber (match_scratch:PSI 2 "=&b"))]
- "TARGET_DW_ENABLE"
- "load 0,17,%0,%1"
- [(set_attr "type" "load")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
- (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))
- (clobber (match_scratch:PSI 2 "=&b"))]
- "TARGET_DW_ENABLE"
- "load 0,17,%0,%1"
- [(set_attr "type" "load")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
- (clobber (match_scratch:PSI 2 "=&b"))]
- "TARGET_DW_ENABLE"
- "load 0,18,%0,%1"
- [(set_attr "type" "load")])
-\f
-;; LOADM
-(define_expand "load_multiple"
- [(set (match_dup 4)
- (match_operand:PSI 2 "const_int_operand" ""))
- (match_par_dup 3 [(set (match_operand:SI 0 "" "")
- (match_operand:SI 1 "" ""))])]
- ""
- "
-{
- int regno;
- int count;
- rtx from;
- int i;
-
- /* Support only loading a constant number of hard registers from memory. */
- if (GET_CODE (operands[2]) != CONST_INT
- || operands[2] == const1_rtx
- || GET_CODE (operands[1]) != MEM
- || GET_CODE (operands[0]) != REG
- || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
- FAIL;
-
- count = INTVAL (operands[2]);
- regno = REGNO (operands[0]);
-
- /* CR gets set to the number of registers minus one. */
- operands[2] = GEN_INT(count - 1);
-
- operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 2));
- from = memory_address (SImode, XEXP (operands[1], 0));
- XVECEXP (operands[3], 0, 0) = gen_rtx_SET (VOIDmode,
- gen_rtx_REG (SImode, regno),
- gen_rtx_MEM (SImode, from));
- operands[4] = gen_reg_rtx (PSImode);
-
- XVECEXP (operands[3], 0, 1) = gen_rtx_USE (VOIDmode, operands[4]);
- XVECEXP (operands[3], 0, 2) = gen_rtx_CLOBBER (VOIDmode, operands[4]);
-
- for (i = 1; i < count; i++)
- XVECEXP (operands[3], 0, i + 2)
- = gen_rtx_SET (VOIDmode, gen_rtx (REG, SImode, regno + i),
- gen_rtx_MEM (SImode, plus_constant (from, i * 4)));
-}")
-
-;; Indicate that CR is used and is then clobbered.
-(define_insn ""
- [(set (match_operand 0 "gpc_reg_operand" "=r")
- (match_operand 1 "memory_operand" "m"))
- (use (match_operand:PSI 2 "register_operand" "+c"))
- (clobber (match_dup 2))]
- "GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
- "loadm 0,0,%0,%1"
- [(set_attr "type" "load")])
-
-(define_insn ""
- [(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
- (match_operand:SI 2 "memory_operand" "m"))
- (use (match_operand:PSI 3 "register_operand" "+c"))
- (clobber (match_dup 3))])]
- ""
- "loadm 0,0,%1,%2"
- [(set_attr "type" "load")])
-\f
-;; MTSR (used also by move insn)
-(define_insn ""
- [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h")
- (and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")
- (match_operand:SI 2 "const_int_operand" "n,n")))]
- "masks_bits_for_special (operands[0], operands[2])"
- "@
- mtsr %0,%1
- mtsrim %0,%1")
-
-(define_insn ""
- [(set (match_operand:PSI 0 "register_operand" "=h,h")
- (truncate:PSI
- (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))]
- ""
- "@
- mtsr %0,%1
- mtsrim %0,%1")
-\f
-;; MULTIPLY, MULTM, MULTMU
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))
- (clobber (match_scratch:SI 3 "=&q"))]
- ""
- "multiply %0,%1,%2")
-
-(define_insn "mulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (clobber (match_scratch:SI 3 "=&q"))]
- "TARGET_MULTM"
- "multiply %L0,%1,%2\;multm %0,%1,%2"
- [(set_attr "type" "multi")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
- (clobber (reg:SI 180))]
- "reload_completed"
- [(parallel [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:SI 180))])
- (parallel [(set (match_dup 4)
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (sign_extend:DI (match_dup 1))
- (sign_extend:DI (match_dup 2)))
- (const_int 32))))
- (clobber (reg:SI 180))])]
- "
-{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
- operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
-
-(define_insn "umulsidi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
- (clobber (match_scratch:SI 3 "=&q"))]
- "TARGET_MULTM"
- "multiplu %L0,%1,%2\;multmu %0,%1,%2"
- [(set_attr "type" "multi")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
- (clobber (reg:SI 180))]
- "reload_completed"
- [(parallel [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:SI 180))])
- (parallel [(set (match_dup 4)
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI (match_dup 1))
- (zero_extend:DI (match_dup 2)))
- (const_int 32))))
- (clobber (reg:SI 180))])]
- "
-{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
- operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
-
-(define_insn "smulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=&q"))]
- "TARGET_MULTM"
- "multm %0,%1,%2")
-
-(define_insn "umulsi3_highpart"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=&q"))]
- "TARGET_MULTM"
- "multmu %0,%1,%2")
-
-;; NAND
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- ""
- "nand %0,%1,%2")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (match_operand:SI 2 "const_int_operand" "K")))]
- ; Match TARGET_29050 in "orn" pattern for slightly better reload.
- "! TARGET_29050 && ((unsigned) ~ INTVAL (operands[2])) < 256"
- "nand %0,%1,%C2")
-
-;; NOR
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- ""
- "nor %0,%1,%2")
-
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
- ""
- "nor %0,%1,0")
-\f
-;; OR/ORN
-(define_expand "iorsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "srcb_operand" "")))]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
- (match_operand:SI 2 "srcb_operand" "rI")))]
- "! TARGET_29050"
- "or %0,%1,%2")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "and_operand" "rI,K")))]
- "TARGET_29050"
- "@
- or %0,%1,%2
- orn %0,%1,%C2")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
- (match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
- "TARGET_29050"
- "@
- orn %0,%2,%1
- nand %0,%1,%C2")
-
-\f
-;; SLL (also used by move insn)
-(define_insn "nop"
- [(const_int 0)]
- ""
- "aseq 0x40,gr1,gr1")
-
-(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "srcb_operand" "rn")))]
- ""
- "sll %0,%1,%Q2")
-
-;; SQRT
-(define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
- "TARGET_29050"
- "sqrt %0,%1,1"
- [(set_attr "type" "fsqrt")])
-
-(define_insn "sqrtdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_29050"
- "sqrt %0,%1,2"
- [(set_attr "type" "dsqrt")])
-
-;; SRA
-(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "srcb_operand" "rn")))]
- ""
- "sra %0,%1,%Q2")
-
-;; SRL
-(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:QI 2 "srcb_operand" "rn")))]
- ""
- "srl %0,%1,%Q2")
-\f
-;; STORE
-;;
-;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word
-;; stores on systems with DW not set.
-(define_insn ""
- [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
- (const_int -4)))
- (match_operand:SI 1 "gpc_reg_operand" "r"))]
- "! TARGET_DW_ENABLE"
- "store 0,1,%1,%0"
- [(set_attr "type" "store")])
-
-(define_insn ""
- [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
- (const_int -3)))
- (match_operand:SI 1 "gpc_reg_operand" "r"))]
- "! TARGET_DW_ENABLE"
- "store 0,2,%1,%0"
- [(set_attr "type" "store")])
-
-;; STOREM
-(define_expand "store_multiple"
- [(use (match_operand 0 "" ""))
- (use (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))]
- ""
- "
-{ rtx pat;
-
- if (TARGET_NO_STOREM_BUG)
- pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]);
- else
- pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]);
-
- if (pat)
- emit_insn (pat);
- else
- FAIL;
-
- DONE;
-}")
-
-(define_expand "store_multiple_no_bug"
- [(set (match_dup 4)
- (match_operand:PSI 2 "const_int_operand" ""))
- (match_par_dup 3 [(set (match_operand:SI 0 "" "")
- (match_operand:SI 1 "" ""))])]
- ""
- "
-{
- int regno;
- int count;
- rtx from;
- int i;
-
- /* Support only storing a constant number of hard registers to memory. */
- if (GET_CODE (operands[2]) != CONST_INT
- || operands[2] == const1_rtx
- || GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG
- || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
- FAIL;
-
- count = INTVAL (operands[2]);
- regno = REGNO (operands[1]);
-
- /* CR gets set to the number of registers minus one. */
- operands[2] = GEN_INT(count - 1);
-
- operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 2));
- from = memory_address (SImode, XEXP (operands[0], 0));
- XVECEXP (operands[3], 0, 0) = gen_rtx_SET (VOIDmode,
- gen_rtx_MEM (SImode, from),
- gen_rtx_REG (SImode, regno));
- operands[4] = gen_reg_rtx (PSImode);
- XVECEXP (operands[3], 0, 1) = gen_rtx_USE (VOIDmode, operands[4]);
- XVECEXP (operands[3], 0, 2) = gen_rtx_CLOBBER (VOIDmode, operands[4]);
-
- for (i = 1; i < count; i++)
- XVECEXP (operands[3], 0, i + 2)
- = gen_rtx_SET (VOIDmode,
- gen_rtx_MEM (SImode, plus_constant (from, i * 4)),
- gen_rtx_REG (SImode, regno + i));
-}")
-
-(define_expand "store_multiple_bug"
- [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
- (match_operand:SI 1 "" ""))
- (use (match_operand:SI 2 "" ""))])]
- ""
- "
-{
- int regno;
- int count;
- rtx from;
- int i;
-
- /* Support only storing a constant number of hard registers to memory. */
- if (GET_CODE (operands[2]) != CONST_INT
- || operands[2] == const1_rtx
- || GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG
- || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
- FAIL;
-
- count = INTVAL (operands[2]);
- regno = REGNO (operands[1]);
-
- operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
- from = memory_address (SImode, XEXP (operands[0], 0));
- XVECEXP (operands[3], 0, 0) = gen_rtx_SET (VOIDmode,
- gen_rtx_MEM (SImode, from),
- gen_rtx_REG (SImode, regno));
- XVECEXP (operands[3], 0, 1)
- = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (PSImode));
-
- for (i = 1; i < count; i++)
- XVECEXP (operands[3], 0, i + 1)
- = gen_rtx_SET (VOIDmode,
- gen_rtx_MEM (SImode, plus_constant (from, i * 4)),
- gen_rtx_REG (SImode, regno + i));
-}")
-
-(define_insn ""
- [(set (match_operand 0 "memory_operand" "=m")
- (match_operand 1 "gpc_reg_operand" "r"))
- (clobber (match_scratch:PSI 2 "=&c"))]
- "!TARGET_NO_STOREM_BUG
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
- "mtsrim cr,%S1\;storem 0,0,%1,%0"
- [(set_attr "type" "multi")])
-
-(define_insn ""
- [(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:PSI 3 "=&c"))])]
- "!TARGET_NO_STOREM_BUG"
- "mtsrim cr,%V0\;storem 0,0,%2,%1"
- [(set_attr "type" "multi")])
-
-(define_insn ""
- [(set (match_operand 0 "memory_operand" "=m")
- (match_operand 1 "gpc_reg_operand" "r"))
- (use (match_operand:PSI 2 "register_operand" "+c"))
- (clobber (match_dup 2))]
- "TARGET_NO_STOREM_BUG
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
- "storem 0,0,%1,%0"
- [(set_attr "type" "store")])
-
-(define_insn ""
- [(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
- (match_operand:SI 2 "gpc_reg_operand" "r"))
- (use (match_operand:PSI 3 "register_operand" "+c"))
- (clobber (match_dup 3))])]
- "TARGET_NO_STOREM_BUG"
- "storem 0,0,%2,%1"
- [(set_attr "type" "store")])
-\f
-;; SUB
-;;
-;; Either operand can be a register or an 8-bit constant, but both cannot be
-;; constants (can't usually occur anyway).
-(define_expand "subsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (minus:SI (match_operand:SI 1 "srcb_operand" "")
- (match_operand:SI 2 "srcb_operand" "")))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == CONST_INT
- && GET_CODE (operands[1]) == CONST_INT)
- operands[1] = force_reg (SImode, operands[1]);
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (minus:SI (match_operand:SI 1 "srcb_operand" "r,I")
- (match_operand:SI 2 "srcb_operand" "rI,r")))]
- "register_operand (operands[1], SImode)
- || register_operand (operands[2], SImode)"
- "@
- sub %0,%1,%2
- subr %0,%2,%1")
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "gpc_reg_operand" "r")))]
- ""
- "sub %L0,%L1,%L2\;subc %0,%1,%2"
- [(set_attr "type" "multi")])
-
-;; SUBR (also used above in SUB)
-(define_insn "negdi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
- ""
- "subr %L0,%L1,0\;subrc %0,%1,0"
- [(set_attr "type" "multi")])
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
- ""
- "subr %0,%1,0")
-\f
-;; XNOR
-(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
- (match_operand:SI 2 "gpc_reg_operand" "r"))))]
- ""
- "xnor %0,%1,%2")
-
-;; XOR
-
-(define_insn "xorsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
- (match_operand:SI 2 "and_operand" "rI,K")))]
- ""
- "@
- xor %0,%1,%2
- xnor %0,%1,%C2")
-
-;; Can use XOR to negate floating-point values, but we are better off not doing
-;; it that way on the 29050 so it can combine with the fmac insns.
-(define_expand "negsf2"
- [(parallel [(set (match_operand:SF 0 "register_operand" "")
- (neg:SF (match_operand:SF 1 "register_operand" "")))
- (clobber (match_scratch:SI 2 ""))])]
- "! TARGET_SOFT_FLOAT"
- "
-{
- rtx result;
- rtx target;
-
- if (! TARGET_29050)
- {
- target = operand_subword_force (operands[0], 0, SFmode);
- result = expand_binop (SImode, xor_optab,
- operand_subword_force (operands[1], 0, SFmode),
- GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
- if (result == 0)
- abort ();
-
- if (result != target)
- emit_move_insn (result, target);
-
- /* Make a place for REG_EQUAL. */
- emit_move_insn (operands[0], operands[0]);
- DONE;
- }
-}")
-
-(define_expand "negdf2"
- [(parallel [(set (match_operand:DF 0 "register_operand" "")
- (neg:DF (match_operand:DF 1 "register_operand" "")))
- (clobber (match_scratch:SI 2 ""))])]
- "! TARGET_SOFT_FLOAT"
- "
-{
- rtx result;
- rtx target;
- rtx insns;
-
- if (! TARGET_29050)
- {
- start_sequence ();
- target = operand_subword (operands[0], 0, 1, DFmode);
- result = expand_binop (SImode, xor_optab,
- operand_subword_force (operands[1], 0, DFmode),
- GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
- if (result == 0)
- abort ();
-
- if (result != target)
- emit_move_insn (result, target);
-
- emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
- operand_subword_force (operands[1], 1, DFmode));
-
- insns = get_insns ();
- end_sequence ();
-
- emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
- DONE;
- }
-}")
-\f
-;; Sign extend and truncation operations.
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
- (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
- ""
- "and %0,%1,255")
-
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
- ""
- "and %0,%1,255")
-
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))]
- ""
- "consth %0,0")
-
-(define_expand "extendqihi2"
- [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (set (match_operand:HI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))]
- ""
- "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqisi2"
- [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
- (const_int 24)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 24)))]
- ""
- "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendhisi2"
- [(set (match_dup 2)
- (ashift:SI (match_operand:HI 1 "gpc_reg_operand" "")
- (const_int 16)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 2)
- (const_int 16)))]
- ""
- "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_reg_rtx (SImode); }")
-\f
-;; Define the methods used to move data around.
-;;
-;; movsi:
-;;
-;; If storing into memory, force source into register.
-(define_expand "movsi"
- [(set (match_operand:SI 0 "general_operand" "")
- (match_operand:SI 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode))
- operands[1] = copy_to_mode_reg (SImode, operands[1]);
- else if (spec_reg_operand (operands[0], SImode)
- && ! (register_operand (operands[1], SImode)
- || cint_16_operand (operands[1], SImode)))
- operands[1] = force_reg (SImode, operands[1]);
-}")
-
-(define_expand "movpsi"
- [(set (match_operand:PSI 0 "general_operand" "")
- (match_operand:PSI 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM
- && ! gpc_reg_operand (operands[1], PSImode))
- operands[1] = copy_to_mode_reg (PSImode, operands[1]);
- else if (spec_reg_operand (operands[0], PSImode)
- && ! (register_operand (operands[1], PSImode)
- || cint_16_operand (operands[1], PSImode)))
- operands[1] = force_reg (PSImode, operands[1]);
-}")
-
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_operand:SI 1 "long_const_operand" ""))]
- ""
- [(set (match_dup 0)
- (and:SI (match_dup 1)
- (const_int 65535)))
- (set (match_dup 0)
- (ior:SI (zero_extend:SI (match_dup 2))
- (and:SI (match_dup 1)
- (const_int -65536))))]
- " operands[2] = gen_lowpart (HImode, operands[0]); ")
-\f
-;; Subroutines to load/store halfwords. Operands 0 and 1 are the output and
-;; input, respectively, except that the address is passed for a MEM instead
-;; of the MEM itself and the short item is passed in QImode.
-;;
-;; Operand 2 is a scratch general register and operand 3 is a scratch register
-;; used for BP. When called before reload, pseudos are passed for both
-;; operands. During reload, R_TAV is used for the general register, and
-;; a reload register of class BR_REGS (R_VP) for BP.
-;;
-;; We have two versions of the store operations, for when halfword writes are
-;; supported and when they are not.
-(define_expand "loadhi"
- [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
- (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (const_int -4))))
- (set (match_operand:PSI 3 "register_operand" "")
- (truncate:PSI (match_dup 1)))])
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extract:SI (match_dup 2)
- (const_int 16)
- (ashift:PSI (match_dup 3) (const_int 3))))]
- ""
- "")
-
-(define_expand "storehinhww"
- [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
- (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
- (const_int -4))))
- (set (match_operand:PSI 3 "register_operand" "")
- (truncate:PSI (match_dup 0)))])
- (set (zero_extract:SI (match_dup 2)
- (const_int 16)
- (ashift:PSI (match_dup 3) (const_int 3)))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (set (mem:SI (match_dup 0))
- (match_dup 2))]
- ""
- "")
-
-(define_expand "storehihww"
- [(set (match_operand:PSI 3 "register_operand" "")
- (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
- (set (match_operand:SI 2 "gpc_reg_operand" "")
- (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535)
- (ashift:PSI (match_dup 3)
- (const_int 3))))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (ashift:SI (zero_extend:SI (match_dup 4))
- (ashift:PSI (match_dup 3) (const_int 3)))))
- (set (mem:SI (and:SI (match_dup 0)
- (const_int -3)))
- (match_dup 2))]
- ""
- "
-{ operands[4] = gen_lowpart (HImode, operands[1]); }")
-
-(define_expand "movhi"
- [(set (match_operand:HI 0 "general_operand" "")
- (match_operand:HI 1 "general_operand" ""))]
- ""
- "
-{ if (GET_CODE (operands[0]) == MEM)
- {
- if (! gpc_reg_operand (operands[1], HImode))
- operands[1] = copy_to_mode_reg (HImode, operands[1]);
- if (! TARGET_DW_ENABLE)
- {
- rtx general = gen_reg_rtx (SImode);
- rtx bp = gen_reg_rtx (PSImode);
- rtx (*fcn) PARAMS ((rtx, rtx, rtx, rtx))
- = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
- rtx seq = (*fcn) (XEXP (operands[0], 0),
- gen_lowpart (SImode, operands[1]),
- general, bp);
-
- a29k_set_memflags (seq, operands[0]);
- emit_insn (seq);
- DONE;
- }
- }
- else if (GET_CODE (operands[1]) == MEM)
- {
- if (! TARGET_DW_ENABLE)
- {
- rtx general = gen_reg_rtx (SImode);
- rtx bp = gen_reg_rtx (PSImode);
- rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]),
- XEXP (operands[1], 0), general, bp);
-
- a29k_set_memflags (seq, operands[1]);
- emit_insn (seq);
- DONE;
- }
- }
-}")
-
-(define_expand "reload_inhi"
- [(parallel [(match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "reload_memory_operand" "m")
- (match_operand:PSI 2 "register_operand" "=b")])]
- "! TARGET_DW_ENABLE"
- "
-{ rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]),
- a29k_get_reloaded_address (operands[1]),
- gen_rtx_REG (SImode, R_TAV),
- operands[2]);
-
- a29k_set_memflags (seq, operands[1]);
- emit_insn (seq);
- DONE;
-}")
-
-(define_expand "reload_outhi"
- [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
- (match_operand:SI 1 "register_operand" "m")
- (match_operand:PSI 2 "register_operand" "=b")])]
- "! TARGET_DW_ENABLE"
- "
-{ rtx (*fcn) PARAMS ((rtx, rtx, rtx, rtx)) =
- TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
- rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
- gen_lowpart (SImode, operands[1]),
- gen_rtx_REG (SImode, R_TAV), operands[2]);
-
- a29k_set_memflags (seq, operands[0]);
- emit_insn (seq);
- DONE;
-}")
-\f
-;; Subroutines to load/store bytes. Operands 0 and 1 are the output and
-;; input, respectively, except that the address is passed for a MEM instead
-;; of the MEM itself and the short item is passed in QImode.
-;;
-;; Operand 2 is a scratch general register and operand 3 is a scratch register
-;; used for BP. When called before reload, pseudos are passed for both
-;; operands. During reload, R_TAV is used for the general register, and
-;; a reload register of class BR_REGS (R_VP) for BP.
-;;
-;; We have two versions of the store operations, for when byte writes are
-;; supported and when they are not.
-(define_expand "loadqi"
- [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
- (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (const_int -4))))
- (set (match_operand:PSI 3 "register_operand" "")
- (truncate:PSI (match_dup 1)))])
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extract:SI (match_dup 2)
- (const_int 8)
- (ashift:PSI (match_dup 3) (const_int 3))))]
- ""
- "")
-
-(define_expand "storeqinhww"
- [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
- (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
- (const_int -4))))
- (set (match_operand:PSI 3 "register_operand" "")
- (truncate:PSI (match_dup 0)))])
- (set (zero_extract:SI (match_dup 2)
- (const_int 8)
- (ashift:PSI (match_dup 3)
- (const_int 3)))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (set (mem:SI (match_dup 0))
- (match_dup 2))]
- ""
- "")
-
-(define_expand "storeqihww"
- [(set (match_operand:PSI 3 "register_operand" "")
- (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
- (set (match_operand:SI 2 "gpc_reg_operand" "")
- (ior:SI (and:SI (not:SI (ashift:SI (const_int 255)
- (ashift:PSI (match_dup 3)
- (const_int 3))))
- (match_operand:SI 1 "gpc_reg_operand" ""))
- (ashift:SI (zero_extend:SI (match_dup 4))
- (ashift:PSI (match_dup 3)
- (const_int 3)))))
- (set (mem:SI (and:SI (match_dup 0)
- (const_int -4)))
- (match_dup 2))]
- ""
- "
-{ operands[4] = gen_lowpart (QImode, operands[1]); }")
-\f
-(define_expand "movqi"
- [(set (match_operand:QI 0 "general_operand" "")
- (match_operand:QI 1 "general_operand" ""))]
- ""
- "
-{ if (GET_CODE (operands[0]) == MEM)
- {
- if (! gpc_reg_operand (operands[1], QImode))
- operands[1] = copy_to_mode_reg (QImode, operands[1]);
- if (! TARGET_DW_ENABLE)
- {
- rtx general = gen_reg_rtx (SImode);
- rtx bp = gen_reg_rtx (PSImode);
- rtx (*fcn) PARAMS ((rtx, rtx, rtx, rtx))
- = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
- rtx seq = (*fcn) (XEXP (operands[0], 0),
- gen_lowpart (SImode, operands[1]),
- general, bp);
-
- a29k_set_memflags (seq, operands[0]);
- emit_insn (seq);
- DONE;
- }
- }
- else if (GET_CODE (operands[1]) == MEM)
- {
- if (! TARGET_DW_ENABLE)
- {
- rtx general = gen_reg_rtx (SImode);
- rtx bp = gen_reg_rtx (PSImode);
- rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
- XEXP (operands[1], 0), general, bp);
-
- a29k_set_memflags (seq, operands[1]);
- emit_insn (seq);
- DONE;
- }
- }
-}")
-
-(define_expand "reload_inqi"
- [(parallel [(match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "reload_memory_operand" "m")
- (match_operand:PSI 2 "register_operand" "=b")])]
- "! TARGET_DW_ENABLE"
- "
-{ rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
- a29k_get_reloaded_address (operands[1]),
- gen_rtx_REG (SImode, R_TAV),
- operands[2]);
-
- a29k_set_memflags (seq, operands[1]);
- emit_insn (seq);
- DONE;
-}")
-
-(define_expand "reload_outqi"
- [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
- (match_operand:SI 1 "register_operand" "m")
- (match_operand:PSI 2 "register_operand" "=b")])]
- "! TARGET_DW_ENABLE"
- "
-{ rtx (*fcn) PARAMS ((rtx, rtx, rtx, rtx)) =
- TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
- rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
- gen_lowpart (SImode, operands[1]),
- gen_rtx_REG (SImode, R_TAV), operands[2]);
-
- a29k_set_memflags (seq, operands[0]);
- emit_insn (seq);
- DONE;
-}")
-\f
-;; Now the actual insns used to move data around. We include here the
-;; DEFINE_SPLITs that may be needed. In some cases these will be
-;; split again. For floating-point, if we can look inside the constant,
-;; always split it. This can eliminate unnecessary insns.
-(define_insn ""
- [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m")
- (match_operand:SF 1 "in_operand" "r,E,F,m,r"))]
- "(gpc_reg_operand (operands[0], SFmode)
- || gpc_reg_operand (operands[1], SFmode))
- && ! TARGET_29050"
- "@
- sll %0,%1,0
- #
- const %0,%1\;consth %0,%1
- load 0,0,%0,%1
- store 0,0,%1,%0"
- [(set_attr "type" "misc,multi,multi,load,store")])
-
-(define_insn ""
- [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r")
- (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))]
- "(gpc_reg_operand (operands[0], SFmode)
- || gpc_reg_operand (operands[1], SFmode))
- && TARGET_29050"
- "@
- sll %0,%1,0
- #
- const %0,%1\;consth %0,%1
- load 0,0,%0,%1
- store 0,0,%1,%0
- mtacc %1,1,%0
- mfacc %0,1,%1"
- [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")])
-
-;; Turn this into SImode. It will then be split up that way.
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "float_const_operand" ""))]
- ""
- [(set (match_dup 0)
- (match_dup 1))]
- "
-{ operands[0] = operand_subword (operands[0], 0, 0, SFmode);
- operands[1] = operand_subword (operands[1], 0, 0, SFmode);
-
- if (operands[0] == 0 || operands[1] == 0)
- FAIL;
-}")
-
-(define_insn ""
- [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m")
- (match_operand:DF 1 "in_operand" "rE,F,m,r"))
- (clobber (match_scratch:PSI 2 "=X,X,&c,&c"))]
- "(gpc_reg_operand (operands[0], DFmode)
- || gpc_reg_operand (operands[1], DFmode))
- && ! TARGET_29050"
- "@
- #
- const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
- mtsrim cr,1\;loadm 0,0,%0,%1
- mtsrim cr,1\;storem 0,0,%1,%0"
- [(set_attr "type" "multi")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m,?*a,?r")
- (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a"))
- (clobber (match_scratch:PSI 2 "=X,X,&c,&c,X,X"))]
- "(gpc_reg_operand (operands[0], DFmode)
- || gpc_reg_operand (operands[1], DFmode))
- && TARGET_29050"
- "@
- #
- const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
- mtsrim cr,1\;loadm 0,0,%0,%1
- mtsrim cr,1\;storem 0,0,%1,%0
- mtacc %1,2,%0
- mfacc %0,2,%1"
- [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")])
-
-;; Split register-register copies and constant loads into two SImode loads,
-;; one for each word. In the constant case, they will get further split.
-;; Don't so this until register allocation, though, since it will
-;; interfere with register allocation. Normally copy the lowest-addressed
-;; word first; the exception is if we are copying register to register and
-;; the lowest register of the first operand is the highest register of the
-;; second operand.
-(define_split
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operand:DF 1 "gpc_reg_or_float_constant_operand" ""))
- (clobber (match_scratch:PSI 2 ""))]
- "reload_completed"
- [(set (match_dup 3) (match_dup 4))
- (set (match_dup 5) (match_dup 6))]
- "
-{ if (GET_CODE (operands[1]) == REG
- && REGNO (operands[0]) == REGNO (operands[1]) + 1)
- {
- operands[3] = operand_subword (operands[0], 1, 1, DFmode);
- operands[4] = operand_subword (operands[1], 1, 1, DFmode);
- operands[5] = operand_subword (operands[0], 0, 1, DFmode);
- operands[6] = operand_subword (operands[1], 0, 1, DFmode);
- }
- else
- {
- operands[3] = operand_subword (operands[0], 0, 1, DFmode);
- operands[4] = operand_subword (operands[1], 0, 1, DFmode);
- operands[5] = operand_subword (operands[0], 1, 1, DFmode);
- operands[6] = operand_subword (operands[1], 1, 1, DFmode);
- }
-
- if (operands[3] == 0 || operands[4] == 0
- || operands[5] == 0 || operands[6] == 0)
- FAIL;
-}")
-
-;; Split memory loads and stores into the MTSR and LOADM/STOREM.
-(define_split
- [(set (match_operand:DF 0 "out_operand" "")
- (match_operand:DF 1 "in_operand" ""))
- (clobber (reg:PSI 179))]
- "TARGET_NO_STOREM_BUG
- && (memory_operand (operands[0], DFmode)
- || memory_operand (operands[1], DFmode))"
- [(set (reg:PSI 179) (const_int 1))
- (parallel [(set (match_dup 0) (match_dup 1))
- (use (reg:PSI 179))
- (clobber (reg:PSI 179))])]
- "")
-
-;; DI move is similar to DF move.
-(define_insn ""
- [(set (match_operand:DI 0 "out_operand" "=?r,r,m")
- (match_operand:DI 1 "in_operand" "rn,m,r"))
- (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
- "(gpc_reg_operand (operands[0], DImode)
- || gpc_reg_operand (operands[1], DImode))"
- "@
- #
- mtsrim cr,1\;loadm 0,0,%0,%1
- mtsrim cr,1\;storem 0,0,%1,%0"
- [(set_attr "type" "multi")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "gpc_reg_or_integer_constant_operand" ""))
- (clobber (match_scratch:PSI 2 ""))]
- "reload_completed"
- [(set (match_dup 3) (match_dup 4))
- (set (match_dup 5) (match_dup 6))]
- "
-{ if (GET_CODE (operands[1]) == REG
- && REGNO (operands[0]) == REGNO (operands[1]) + 1)
- {
- operands[3] = operand_subword (operands[0], 1, 1, DImode);
- operands[4] = operand_subword (operands[1], 1, 1, DImode);
- operands[5] = operand_subword (operands[0], 0, 1, DImode);
- operands[6] = operand_subword (operands[1], 0, 1, DImode);
- }
- else
- {
- operands[3] = operand_subword (operands[0], 0, 1, DImode);
- operands[4] = operand_subword (operands[1], 0, 1, DImode);
- operands[5] = operand_subword (operands[0], 1, 1, DImode);
- operands[6] = operand_subword (operands[1], 1, 1, DImode);
- }
-}")
-
-(define_split
- [(set (match_operand:DI 0 "out_operand" "")
- (match_operand:DI 1 "in_operand" ""))
- (clobber (reg:PSI 179))]
- "TARGET_NO_STOREM_BUG
- && (memory_operand (operands[0], DImode)
- || memory_operand (operands[1], DImode))"
- [(set (reg:PSI 179) (const_int 1))
- (parallel [(set (match_dup 0) (match_dup 1))
- (use (reg:PSI 179))
- (clobber (reg:PSI 179))])]
- "")
-
-;; TImode moves are very similar to DImode moves, except that we can't
-;; have constants.
-(define_insn ""
- [(set (match_operand:TI 0 "out_operand" "=?r,r,m")
- (match_operand:TI 1 "in_operand" "r,m,r"))
- (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
- "(gpc_reg_operand (operands[0], TImode)
- || gpc_reg_operand (operands[1], TImode))"
- "@
- #
- mtsrim cr,3\;loadm 0,0,%0,%1
- mtsrim cr,3\;storem 0,0,%1,%0"
- [(set_attr "type" "multi,multi,multi")])
-
-(define_split
- [(set (match_operand:TI 0 "gpc_reg_operand" "")
- (match_operand:TI 1 "gpc_reg_operand" ""))
- (clobber (match_scratch:PSI 2 ""))]
- "reload_completed"
- [(set (match_dup 3) (match_dup 4))
- (set (match_dup 5) (match_dup 6))
- (set (match_dup 7) (match_dup 8))
- (set (match_dup 9) (match_dup 10))]
- "
-{
- if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
- && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
- {
- operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 3);
- operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 3);
- operands[5] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
- operands[6] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
- operands[7] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- operands[8] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- operands[9] = gen_rtx_REG (SImode, REGNO (operands[0]));
- operands[10] = gen_rtx_REG (SImode, REGNO (operands[1]));
- }
- else
- {
- operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]));
- operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]));
- operands[5] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- operands[6] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- operands[7] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
- operands[8] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
- operands[9] = gen_rtx_REG (SImode, REGNO (operands[0]) + 3);
- operands[10] = gen_rtx_REG (SImode, REGNO (operands[1]) + 3);
- }
-}")
-
-(define_split
- [(set (match_operand:TI 0 "out_operand" "")
- (match_operand:TI 1 "in_operand" ""))
- (clobber (reg:PSI 179))]
- "TARGET_NO_STOREM_BUG
- && (memory_operand (operands[0], TImode)
- || memory_operand (operands[1], TImode))"
- [(set (reg:PSI 179) (const_int 3))
- (parallel [(set (match_dup 0) (match_dup 1))
- (use (reg:PSI 179))
- (clobber (reg:PSI 179))])]
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
- (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
- "(gpc_reg_operand (operands[0], SImode)
- || gpc_reg_operand (operands[1], SImode)
- || (spec_reg_operand (operands[0], SImode)
- && cint_16_operand (operands[1], SImode)))
- && ! TARGET_29050"
- "@
- sll %0,%1,0
- const %0,%1
- constn %0,%M1
- cpeq %0,gr1,gr1
- #
- load 0,0,%0,%1
- mfsr %0,%1
- store 0,0,%1,%0
- mtsr %0,%1
- mtsrim %0,%1"
- [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
- (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
- "(gpc_reg_operand (operands[0], SImode)
- || gpc_reg_operand (operands[1], SImode)
- || (spec_reg_operand (operands[0], SImode)
- && cint_16_operand (operands[1], SImode)))
- && TARGET_29050"
- "@
- sll %0,%1,0
- const %0,%1
- constn %0,%M1
- consthz %0,%1
- #
- load 0,0,%0,%1
- mfsr %0,%1
- store 0,0,%1,%0
- mtsr %0,%1
- mtsrim %0,%1"
- [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
-
-(define_insn ""
- [(set (match_operand:PSI 0 "out_operand" "=*r,*r,*r,*r,m,h,h")
- (match_operand:PSI 1 "in_operand" "r,i,m,h,r,r,J"))]
- "(gpc_reg_operand (operands[0], PSImode)
- || gpc_reg_operand (operands[1], PSImode)
- || (spec_reg_operand (operands[0], PSImode)
- && cint_16_operand (operands[1], PSImode)))"
- "@
- sll %0,%1,0
- const %0,%1
- load 0,0,%0,%1
- mfsr %0,%1
- store 0,0,%1,%0
- mtsr %0,%1
- mtsrim %0,%1"
- [(set_attr "type" "misc,multi,load,misc,store,misc,misc")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h")
- (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))]
- "gpc_reg_operand (operands[0], HImode)
- || gpc_reg_operand (operands[1], HImode)
- || (spec_reg_operand (operands[0], HImode)
- && cint_16_operand (operands[1], HImode))"
- "@
- sll %0,%1,0
- const %0,%1
- load 0,2,%0,%1
- store 0,2,%1,%0
- mfsr %0,%1
- mtsr %0,%1
- mtsrim %0,%1"
- [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
-
-(define_insn ""
- [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h")
- (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))]
- "gpc_reg_operand (operands[0], QImode)
- || gpc_reg_operand (operands[1], QImode)
- || (spec_reg_operand (operands[0], HImode)
- && cint_16_operand (operands[1], HImode))"
- "@
- sll %0,%1,0
- const %0,%1
- load 0,1,%0,%1
- store 0,1,%1,%0
- mfsr %0,%1
- mtsr %0,%1
- mtsrim %0,%1"
- [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
-\f
-;; Define move insns for DI, TI, SF, and DF.
-;;
-;; In no case do we support mem->mem directly.
-;;
-;; For DI move of constant to register, split apart at this time since these
-;; can require anywhere from 2 to 4 insns and determining which is complex.
-;;
-;; In other cases, handle similarly to SImode moves.
-;;
-;; However, indicate that DI, TI, and DF moves may clobber CR (reg 179).
-(define_expand "movdi"
- [(parallel [(set (match_operand:DI 0 "general_operand" "")
- (match_operand:DI 1 "general_operand" ""))
- (clobber (scratch:PSI))])]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (DImode, operands[1]);
-}")
-
-(define_expand "movsf"
- [(set (match_operand:SF 0 "general_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
- ""
- "
-{ if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (SFmode, operands[1]);
-}")
-
-(define_expand "movdf"
- [(parallel [(set (match_operand:DF 0 "general_operand" "")
- (match_operand:DF 1 "general_operand" ""))
- (clobber (scratch:PSI))])]
- ""
- "
-{ if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (DFmode, operands[1]);
-}")
-
-(define_expand "movti"
- [(parallel [(set (match_operand:TI 0 "general_operand" "")
- (match_operand:TI 1 "general_operand" ""))
- (clobber (scratch:PSI))])]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (TImode, operands[1]);
-
- /* We can't handle constants in general because there is no rtl to represent
- 128 bit constants. Splitting happens to work for CONST_INTs so we split
- them for good code. Other constants will get forced to memory. */
-
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- rtx part0, part1, part2, part3;
-
- part0 = operand_subword (operands[0], 0, 1, TImode);
- part1 = operand_subword (operands[0], 1, 1, TImode);
- part2 = operand_subword (operands[0], 2, 1, TImode);
- part3 = operand_subword (operands[0], 3, 1, TImode);
-
- emit_move_insn (part0, const0_rtx);
- emit_move_insn (part1, const0_rtx);
- emit_move_insn (part2, const0_rtx);
- emit_move_insn (part3, const0_rtx);
-
- DONE;
- }
- else if (CONSTANT_P (operands[1]))
- {
- operands[1] = force_const_mem (TImode, operands[1]);
- if (! memory_address_p (TImode, XEXP (operands[1], 0))
- && ! reload_in_progress)
- operands[1] = adjust_address (operands[1], TImode, 0);
- }
-}")
-\f
-;; Here are the variants of the above for use during reload.
-
-(define_expand "reload_indf"
- [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
- (match_operand:DF 1 "reload_memory_operand" "m"))
- (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
- ""
- "")
-
-(define_expand "reload_outdf"
- [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m")
- (match_operand:DF 1 "register_operand" "r"))
- (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
- ""
- "")
-
-(define_expand "reload_indi"
- [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
- (match_operand:DI 1 "reload_memory_operand" "m"))
- (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
- ""
- "")
-
-(define_expand "reload_outdi"
- [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m")
- (match_operand:DI 1 "register_operand" "r"))
- (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
- ""
- "")
-
-(define_expand "reload_inti"
- [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
- (match_operand:TI 1 "reload_memory_operand" "m"))
- (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
- ""
- "")
-
-(define_expand "reload_outti"
- [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m")
- (match_operand:TI 1 "register_operand" "r"))
- (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
- ""
- "")
-\f
-;; For compare operations, we simply store the comparison operands and
-;; do nothing else. The following branch or scc insn will output whatever
-;; is needed.
-(define_expand "cmpsi"
- [(set (cc0)
- (compare (match_operand:SI 0 "gpc_reg_operand" "")
- (match_operand:SI 1 "srcb_operand" "")))]
- ""
- "
-{
- a29k_compare_op0 = operands[0];
- a29k_compare_op1 = operands[1];
- a29k_compare_fp_p = 0;
- DONE;
-}")
-
-(define_expand "cmpsf"
- [(set (cc0)
- (compare (match_operand:SF 0 "gpc_reg_operand" "")
- (match_operand:SF 1 "gpc_reg_operand" "")))]
- "! TARGET_SOFT_FLOAT"
- "
-{
- a29k_compare_op0 = operands[0];
- a29k_compare_op1 = operands[1];
- a29k_compare_fp_p = 1;
- DONE;
-}")
-
-(define_expand "cmpdf"
- [(set (cc0)
- (compare (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operand:DF 1 "gpc_reg_operand" "")))]
- "! TARGET_SOFT_FLOAT"
- "
-{
- a29k_compare_op0 = operands[0];
- a29k_compare_op1 = operands[1];
- a29k_compare_fp_p = 1;
- DONE;
-}")
-
-;; We can generate bit-tests better if we use NE instead of EQ, but we
-;; don't have an NE for floating-point. So we have to have two patterns
-;; for EQ and two for NE.
-
-(define_expand "beq"
- [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (ge (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
- {
- emit_insn (gen_beq_fp (operands[0]));
- DONE;
- }
-
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "beq_fp"
- [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bne"
- [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
- {
- emit_insn (gen_bne_fp (operands[0]));
- DONE;
- }
-
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bne_fp"
- [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (ge (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-;; We don't have a floating-point "lt" insn, so we have to use "gt" in that
-;; case with the operands swapped. The operands must both be registers in
-;; the floating-point case, so we know that swapping them is OK.
-(define_expand "blt"
- [(set (match_dup 1) (match_dup 2))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- if (a29k_compare_fp_p)
- operands[2] = gen_rtx_GT (SImode, a29k_compare_op1, a29k_compare_op0);
- else
- operands[2] = gen_rtx_LT (SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-;; Similarly for "le".
-(define_expand "ble"
- [(set (match_dup 1) (match_dup 2))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- if (a29k_compare_fp_p)
- operands[2] = gen_rtx_GE (SImode, a29k_compare_op1, a29k_compare_op0);
- else
- operands[2] = gen_rtx_LE (SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-(define_expand "bltu"
- [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bleu"
- [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bgt"
- [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bge"
- [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bgtu"
- [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bgeu"
- [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3)))
- (set (pc)
- (if_then_else (lt (match_dup 1) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_reg_rtx (SImode);
- operands[2] = a29k_compare_op0;
- operands[3] = a29k_compare_op1;
-}")
-\f
-(define_expand "seq"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (eq:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-}")
-
-;; This is the most complicated case, because we don't have a floating-point
-;; "ne" insn. If integer, handle normally. If floating-point, write the
-;; compare and then write an insn to reverse the test.
-(define_expand "sne_fp"
- [(set (match_dup 3)
- (eq:SI (match_operand 1 "gpc_reg_operand" "")
- (match_operand 2 "gpc_reg_operand" "")))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ge:SI (match_dup 3) (const_int 0)))]
- "! TARGET_SOFT_FLOAT"
- "
-{ operands[3] = gen_reg_rtx (SImode);
-}");
-
-(define_expand "sne"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ne:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-
- if (a29k_compare_fp_p)
- {
- emit_insn (gen_sne_fp (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
-
-;; We don't have a floating-point "lt" insn, so use "gt" and swap the
-;; operands, the same as we do "blt".
-(define_expand "slt"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_dup 1))]
- ""
- "
-{
- if (a29k_compare_fp_p)
- operands[1] = gen_rtx_GT (SImode, a29k_compare_op1, a29k_compare_op0);
- else
- operands[1] = gen_rtx_LT (SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-;; Similarly for "le"
-(define_expand "sle"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_dup 1))]
- ""
- "
-{
- if (a29k_compare_fp_p)
- operands[1] = gen_rtx_GE (SImode, a29k_compare_op1, a29k_compare_op0);
- else
- operands[1] = gen_rtx_LE (SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-(define_expand "sltu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ltu:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sleu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (leu:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sgt"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (gt:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sge"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (ge:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sgtu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (gtu:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sgeu"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (geu:SI (match_dup 1) (match_dup 2)))]
- ""
- "
-{
- operands[1] = a29k_compare_op0;
- operands[2] = a29k_compare_op1;
-}")
-\f
-;; Now define the actual jump insns.
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator 0 "branch_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 0)])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "jmp%b0 %1,%l2%#"
- [(set_attr "type" "branch")])
-
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator 0 "branch_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 0)])
- (return)
- (pc)))]
- "null_epilogue ()"
- "jmp%b0i %1,lr0%#"
- [(set_attr "type" "branch")])
-
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator 0 "branch_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "jmp%B0 %1,%l2%#"
- [(set_attr "type" "branch")])
-
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator 0 "branch_operator"
- [(match_operand:SI 1 "gpc_reg_operand" "r")
- (const_int 0)])
- (pc)
- (return)))]
- "null_epilogue ()"
- "jmp%B0i %1,lr0%#"
- [(set_attr "type" "branch")])
-
-(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
- ""
- "jmp %e0%E0"
- [(set_attr "type" "branch")])
-
-(define_insn "return"
- [(return)]
- "null_epilogue ()"
- "jmpi lr0%#"
- [(set_attr "type" "branch")])
-
-(define_insn "indirect_jump"
- [(set (pc)
- (match_operand:SI 0 "gpc_reg_operand" "r"))]
- ""
- "jmpi %0%#"
- [(set_attr "type" "branch")])
-
-(define_insn "tablejump"
- [(set (pc)
- (match_operand:SI 0 "gpc_reg_operand" "r"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
- "jmpi %0%#"
- [(set_attr "type" "branch")])
-
-;; JMPFDEC
-(define_insn ""
- [(set (pc)
- (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "+r")
- (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))
- (set (match_dup 0)
- (plus:SI (match_dup 0)
- (const_int -1)))]
- ""
- "jmpfdec %0,%l1%#"
- [(set_attr "type" "branch")])
+++ /dev/null
-/* Definitions for rtems targeting a AMD A29K using COFF.
- Copyright (C) 1997, 1998, 2000, 2002 Free Software Foundation, Inc.
- Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Specify predefined symbols in preprocessor. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_AM29K -D_AM29000 -D_EPI -D__rtems__ \
- -Asystem=rtems -Acpu=a29k -Amachine=a29k"
+++ /dev/null
-# We want fine grained libraries, so use the new code to build the
-# floating point emulation libraries.
-FPBIT = fp-bit.c
-DPBIT = dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
- cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
- echo '#define FLOAT' > fp-bit.c
- cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-
+++ /dev/null
-# We don't want to put exit in libgcc.a for VxWorks, because VxWorks
-# does not have _exit.
-TARGET_LIBGCC2_CFLAGS = -Dexit=unused_exit
-
-# We want fine grained libraries, so use the new code to build the
-# floating point emulation libraries.
-FPBIT = fp-bit.c
-DPBIT = dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
- cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
- echo '#define FLOAT' > fp-bit.c
- cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+++ /dev/null
-/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU, Unix.
- Copyright (C) 1991, 1993, 1994, 1996 Free Software Foundation, Inc.
- Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* We define unix instead of EPI and define unix-style machine names. */
-
-/* Set our default target to be the 29050; that is the more interesting chip
- for Unix systems. */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (1+2+16+128)
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dam29k -Da29k -Dam29000 -Asystem=unix -Acpu=a29k -Amachine=a29k"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{!m29000:-Dam29050 -D__am29050__}"
-
-/* Use a default linker configuration file. */
-#undef LINK_SPEC
-#define LINK_SPEC "-T default.gld%s"
-
-/* Define the magic numbers that we recognize as COFF. */
-
-#define MY_ISCOFF(magic) ((magic) == SIPFBOMAGIC || (magic) == SIPRBOMAGIC)
-
-/* For some systems, it is best if double-word objects are aligned on a
- doubleword boundary. We want to maintain compatibility with MetaWare in
- a29k.h, but do not feel constrained to do so here. */
-
-#undef BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT 64
-
-/* Add shared data as a kludge for now. */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-{ const char *p, *after_dir = main_input_filename; \
- if (TARGET_29050) \
- fprintf (FILE, "\t.cputype 29050\n"); \
- for (p = main_input_filename; *p; p++) \
- if (*p == '/') \
- after_dir = p + 1; \
- fprintf (FILE, "\t.file "); \
- output_quoted_string (FILE, after_dir); \
- fprintf (FILE, "\n"); \
- if (flag_shared_data) \
- fprintf (FILE, "\t.sect .shdata,data\n"); \
- fprintf (FILE, "\t.sect .lit,lit\n"); }
-
-/* Output before shared data. */
-
-#define SHARED_SECTION_ASM_OP "\t.use .shdata"
-
-/* If we want shared data, we have to turn off commons. */
-
-#define OVERRIDE_OPTIONS if (flag_shared_data) flag_no_common = 1;
-
-/* Default to -fno-pcc-struct-return, since we don't have to worry about
- compatibility. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-#if 0 /* This would be needed except that the 29k doesn't have strict
- alignment requirements. */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
- (((TYPE) != 0) \
- ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
- ? PARM_BOUNDARY \
- : TYPE_ALIGN(TYPE)) \
- : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
- ? PARM_BOUNDARY \
- : GET_MODE_ALIGNMENT(MODE)))
-#endif
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Vxworks 29k version.
- Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* This file just exists to give specs for the 29k running on VxWorks. */
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_AM29K -D_AM29000 -Acpu=a29k -Amachine=a29k -D__vxworks -D__vxworks_5"
-
-/* Vxworks header files require that the macro CPU be set.
- We could define it in CPP_PREDEFINES, but the value is (or will be)
- dependent upon GCC options. */
-
-#undef CPP_SPEC
-#define CPP_SPEC "-DCPU=AM29200"
-
-/* VxWorks does all the library stuff itself. */
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* VxWorks provides the functionality of crt0.o and friends itself. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "crtbegin.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
+++ /dev/null
-/* Definitions of target machine for GNU compiler, for DEC Alpha.
- Copyright (C) 1992, 1993, 1995, 1996 Free Software Foundation, Inc.
- Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* In OSF 1.2, there is a linker bug that prevents use of -O3 to
- the linker. */
-
-#undef LINK_SPEC
-#define LINK_SPEC \
- "-G 8 -O1 %{static:-non_shared} %{rpath*} \
- %{!static:%{shared:-shared} %{!shared:-call_shared}} %{taso}"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
+++ /dev/null
-/* Definitions of target machine for GNU compiler, for DEC Alpha, osf[23].
- Copyright (C) 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* In OSF 2 or 3, linking with -lprof1 doesn't require -lpdf. */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} %{a:-lprof2} -lc"
-
-/* As of OSF 3.2, as still can't subtract adjacent labels. */
-#undef TARGET_AS_CAN_SUBTRACT_LABELS
-#define TARGET_AS_CAN_SUBTRACT_LABELS 0
-
-/* The frame unwind data requires the ability to subtract labels. */
-#undef DWARF2_UNWIND_INFO
-#define DWARF2_UNWIND_INFO 0
+++ /dev/null
-/* Definitions of target machine for GNU compiler,
- for ARM with PE obj format running under the WinCE operating system.
- Copyright (C) 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define ARM_WINCE 1
-
-#include "pe.h"
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fputs (" (ARM/WinCE/PE)", stderr);
-
-/* The next three definitions are defined in pe.h,
- undefined in arm/arm-pe.h and then redefined back here! */
-#undef LIB_SPEC
-#define LIB_SPEC "-lcoredll -lcorelibc"
-
-#define MATH_LIBRARY ""
-
-#define LIBSTDCXX "-lc"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-#define ENDFILE_SPEC ""
-
-#undef CPP_APCS_PC_DEFAULT_SPEC
-#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__"
-
-#undef CC1_SPEC
-#define CC1_SPEC "%{!mapcs-32:%{!mapcs-26:-mapcs-32}}"
-
-#undef ASM_SPEC
-#define ASM_SPEC " \
-%{mbig-endian:-EB} \
-%{mcpu=*:-mcpu=%*} \
-%{march=*:-march=%*} \
-%{mapcs-*:-mapcs-%*} \
-%{mthumb-interwork:-mthumb-interwork} \
-%{!mapcs-32:%{!mapcs-26:-mapcs-32}} \
-"
-
-/* WinCE headers require -DARM */
-#undef PE_SUBTARGET_CPP_SPEC
-#define PE_SUBTARGET_CPP_SPEC "-D__pe__ -DARM -D__unaligned=__attribute__((aligned(1))) "
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "long unsigned int"
? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
: (target_flags & THUMB_FLAG_BACKTRACE))
-/* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
- Bit 31 is reserved. See riscix.h. */
+/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
#ifndef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES
#endif
+++ /dev/null
-/* Definitions of target machine for GNU compiler. ARM RISCiX version.
- Copyright (C) 1993, 1994, 1995, 1997, 1999, 2000
- Free Software Foundation, Inc.
- Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
- work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
- and Martin Simmons (@harleqn.co.uk).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Translation to find startup files. On RISC iX boxes,
- crt0, mcrt0 and gcrt0.o are in /usr/lib. */
-#define STARTFILE_SPEC "\
- %{pg:/usr/lib/gcrt0.o%s}\
- %{!pg:%{p:/usr/lib/mcrt0.o%s}\
- %{!p:/usr/lib/crt0.o%s}}"
-
-/* RISC iX has no concept of -lg */
-/* If -static is specified then link with -lc_n */
-
-#ifndef LIB_SPEC
-#define LIB_SPEC "\
- %{g*:-lg}\
- %{!p:%{!pg:%{!static:-lc}%{static:-lc_n}}}\
- %{p:-lc_p}\
- %{pg:-lc_p}"
-#endif
-
-/* The RISC iX assembler never deletes any symbols from the object module;
- and, by default, ld doesn't either. -X causes local symbols starting
- with 'L' to be deleted, which is what we want. */
-#ifndef LINK_SPEC
-#define LINK_SPEC "-X"
-#endif
-
-#define TARGET_OS_CPP_BUILTINS() \
- do { \
- builtin_define_std ("arm"); \
- builtin_define_std ("unix"); \
- builtin_define_std ("riscix"); \
- builtin_assert ("system=unix"); \
- } while (0)
-
-/* RISCiX has some weird symbol name munging, that is done to the object module
- after assembly, which enables multiple libraries to be supported within
- one (possibly shared) library. It basically changes the symbol name of
- certain symbols (for example _bcopy is converted to _$bcopy if using BSD)
- Symrename's parameters are determined as follows:
- -mno-symrename Don't run symrename
- -mbsd symrename -BSD <file>
- -mxopen symrename -XOPEN <file>
- -ansi symrename - <file>
- <none> symrename -BSD <file>
- */
-
-#ifndef ASM_FINAL_SPEC
-#if !defined (CROSS_COMPILE)
-#define ASM_FINAL_SPEC "\
-%{!mno-symrename: \
- \n /usr/bin/symrename \
- -%{mbsd:%{pedantic:%e-mbsd and -pedantic incompatible}BSD}\
-%{mxopen:%{mbsd:%e-mbsd and -mxopen incompatible}\
-%{pedantic:%e-mxopen and -pedantic incompatible}XOPEN}\
-%{!mbsd:%{!mxopen:%{!ansi:BSD}}} %{c:%{o*:%*}%{!o*:%b.o}}%{!c:%U.o}}"
-#endif
-#endif
-
-/* None of these is actually used in cc1. If we don't define them in target
- switches cc1 complains about them. For the sake of argument lets allocate
- bit 31 of target flags for such options. */
-#define SUBTARGET_SWITCHES \
- {"bsd", 0x80000000, N_("Do symbol renaming for BSD")}, \
- {"xopen", 0x80000000, N_("Do symbol renaming for X/OPEN")}, \
- {"no-symrename", 0x80000000, N_("Don't do symbol renaming")},
-
-
-/* Run-time Target Specification. */
-#define TARGET_VERSION \
- fputs (" (ARM/RISCiX)", stderr);
-
-/* This is used in ASM_FILE_START */
-#define ARM_OS_NAME "RISCiX"
-
-/* Unsigned chars produces much better code than signed. */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Some systems use __main in a way incompatible with its use in gcc, in these
- cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
- give the same symbol without quotes for an alternative entry point. You
- must define both, or neither. */
-#ifndef NAME__MAIN
-#define NAME__MAIN "__gccmain"
-#define SYMBOL__MAIN __gccmain
-#endif
-
-/* size_t is "unsigned int" in RISCiX */
-#define SIZE_TYPE "unsigned int"
-
-/* ptrdiff_t is "int" in RISCiX */
-#define PTRDIFF_TYPE "int"
-
-/* Maths operation domain error number, EDOM */
-#define TARGET_EDOM 33
-
-/* Override the normal default CPU */
-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm2
-
-/* r10 is reserved by RISCiX */
-#define SUBTARGET_CONDITIONAL_REGISTER_USAGE \
- fixed_regs[10] = 1; \
- call_used_regs[10] = 1;
-
-#include "arm/aout.h"
-
-/* The RISCiX assembler does not understand .set */
-#undef SET_ASM_OP
-
-/* Add to CPP_SPEC, we want to add the right #defines when using the include
- files. */
-#define SUBTARGET_CPP_SPEC "\
- %{mbsd:%{pedantic:%e-mbsd and -pedantic incompatible} -D_BSD_C} \
- %{mxopen:%{mbsd:%e-mbsd and -mxopen incompatible} \
- %{pedantic:%e-mxopen and -pedantic incompatible} -D_XOPEN_C} \
- %{!mbsd:%{!mxopen:%{!ansi: -D_BSD_C}}}"
-
-/* The native RISCiX assembler does not support stabs of any kind; because
- the native assembler is not used by the compiler, Acorn didn't feel it was
- necessary to put them in! */
-
-#ifdef DBX_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#endif
+++ /dev/null
-/* Definitions of target machine for GNU compiler. ARM RISCiX 1.1x version.
- Copyright (C) 1993, 1995, 1997, 1999 Free Software Foundation, Inc.
- Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
- work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
- and Martin Simmons (@harleqn.co.uk).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* RISCiX 1.1x is basically the same as 1.2x except that it doesn't have
- symrename or atexit. */
-
-/* Translation to find startup files. On RISCiX boxes, gcrt0.o is in
- /usr/lib. */
-#define STARTFILE_SPEC \
- "%{pg:/usr/lib/gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#define TARGET_OS_CPP_BUILTINS() \
- do { \
- builtin_define_std ("arm"); \
- builtin_define_std ("unix"); \
- builtin_define_std ("riscix"); \
- builtin_assert ("system=unix"); \
- } while (0)
-
-/* Riscix 1.1 doesn't have X/OPEN support, so only accept -mbsd (but ignore
- it).
- By not having -mxopen and -mno-symrename, we get warning messages,
- but everything still compiles. */
-/* None of these is actually used in cc1, so they modify bit 31 */
-#define SUBTARGET_SWITCHES \
-{"bsd", 0x80000000, ""},
-
-
-/* Run-time Target Specification. */
-#define TARGET_VERSION \
- fputs (" (ARM/RISCiX)", stderr);
-
-/* This is used in ASM_FILE_START */
-#define ARM_OS_NAME "RISCiX"
-
-#ifdef riscos
-#define TARGET_WHEN_DEBUGGING 3
-#else
-#define TARGET_WHEN_DEBUGGING 1
-#endif
-
-/* 'char' is signed by default on RISCiX, unsigned on RISCOS. */
-#ifdef riscos
-#define DEFAULT_SIGNED_CHAR 0
-#else
-#define DEFAULT_SIGNED_CHAR 1
-#endif
-
-/* Define this if the target system lacks the function atexit from the
- ANSI C standard. If this is defined, and ON_EXIT is not
- defined, a default exit function will be provided to support C++.
- The man page only describes on_exit, but atexit is also there.
- This seems to be missing in early versions.
-
- FIXME Should we define ON_EXIT here? */
-#define NEED_ATEXIT
-
-/* Some systems use __main in a way incompatible with its use in gcc, in these
- cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
- give the same symbol without quotes for an alternative entry point. You
- must define both, or neither. */
-#ifndef NAME__MAIN
-#define NAME__MAIN "__gccmain"
-#define SYMBOL__MAIN __gccmain
-#endif
-
-/* Override the normal default CPU */
-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm2
-
-/* r10 is reserved by RISCiX */
-#define SUBTARGET_CONDITIONAL_REGISTER_USAGE \
- fixed_regs[10] = 1; \
- call_used_regs[10] = 1;
-
-
-#include "arm/aout.h"
-
-#define SUBTARGET_CPP_SPEC "%{!ansi: -D_BSD_C}"
-
-
-/* The native RISCiX assembler does not support stabs of any kind; because
- the native assembler is not used by the compiler, Acorn didn't feel it was
- necessary to put them in! */
-
-#ifdef DBX_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#endif
+++ /dev/null
-/* Definitions of target machine for GNU compiler. ARM RISCiX(stabs) version.
- Copyright (C) 1993 Free Software Foundation, Inc.
- Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
- work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
- and Martin Simmons (@harleqn.co.uk).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Limit the length of a stabs entry (for the broken Acorn assembler) */
-#undef DBX_CONTIN_LENGTH
-#define DBX_CONTIN_LENGTH 80
-
-/* The native RISCiX assembler does not support stabs of any kind; because
- the native assembler is not used by the compiler, Acorn didn't feel it was
- necessary to put them in!
- However, this file assumes that we have an assembler that does have stabs,
- so we put them back in. */
-
-#define DBX_DEBUGGING_INFO
-
-/* Unfortunately dbx doesn't understand these */
-/* Dbx on RISCiX is so broken that I've given up trying to support it.
- lets just support gdb. */
-/* #define DEFAULT_GDB_EXTENSIONS 0 */
-/* RISCiX dbx doesn't accept xrefs */
-/* #define DBX_NO_XREFS 1 */
-
+++ /dev/null
-# Just for these, we omit the frame pointer since it makes such a big
-# difference. It is then pointless adding debugging.
-TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer
-LIBGCC2_DEBUG_CFLAGS = -g0
-
-FIXPROTO_DEFINES= -D_POSIX_SOURCE -D_XOPEN_C -D_BSD_C -D_XOPEN_SOURCE
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Clipper version.
- Copyright (C) 2000 Free Software Foundation, Inc.
- Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifdef RTX_CODE
-#ifdef TREE_CODE
-extern void clipper_va_start PARAMS ((int, tree, rtx));
-extern rtx clipper_va_arg PARAMS ((tree, tree));
-#endif /* TREE_CODE */
-extern void clipper_movstr PARAMS ((rtx *));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-extern const char *rev_cond_name PARAMS ((rtx));
-extern int int_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int fp_reg_operand PARAMS ((rtx, enum machine_mode));
-#endif /* RTX_CODE */
-
-extern struct rtx_def *clipper_builtin_saveregs PARAMS ((void));
-extern int clipper_frame_size PARAMS ((int));
-#ifdef TREE_CODE
-extern tree clipper_build_va_list PARAMS ((void));
-#endif /* TREE_CODE */
+++ /dev/null
-/* Subroutines for insn-output.c for Clipper
- Copyright (C) 1987, 1988, 1991, 1997, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
- Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-#include "expr.h"
-#include "optabs.h"
-#include "libfuncs.h"
-#include "c-tree.h"
-#include "function.h"
-#include "flags.h"
-#include "recog.h"
-#include "tm_p.h"
-#include "target.h"
-#include "target-def.h"
-
-static void clipper_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void clipper_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void clix_asm_out_constructor PARAMS ((rtx, int));
-static void clix_asm_out_destructor PARAMS ((rtx, int));
-
-extern char regs_ever_live[];
-
-extern int frame_pointer_needed;
-
-static int frame_size;
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
-
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE clipper_output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE clipper_output_function_epilogue
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* Compute size of a clipper stack frame where 'lsize' is the required
- space for local variables. */
-
-int
-clipper_frame_size (lsize)
- int lsize;
-{
- int i, size; /* total size of frame */
- int save_size;
- save_size = 0; /* compute size for reg saves */
-
- for (i = 16; i < 32; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- save_size += 8;
-
- for (i = 0; i < 16; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- save_size += 4;
-
- size = lsize + save_size;
-
- size = (size + 7) & ~7; /* align to 64 Bit */
- return size;
-}
-
-/* Prologue and epilogue output
- Function is entered with pc pushed, i.e. stack is 32 bit aligned
-
- current_function_args_size == 0 means that the current function's args
- are passed totally in registers i.e fp is not used as ap.
- If frame_size is also 0 the current function does not push anything and
- can run with misaligned stack -> subq $4,sp / add $4,sp on entry and exit
- can be omitted. */
-
-static void
-clipper_output_function_prologue (file, lsize)
- FILE *file;
- HOST_WIDE_INT lsize; /* size for locals */
-{
- int i, offset;
- int size;
-
- frame_size = size = clipper_frame_size (lsize);
-
- if (frame_pointer_needed)
- {
- fputs ("\tpushw fp,sp\n", file);
- fputs ("\tmovw sp,fp\n", file);
- }
- else if (size != 0 || current_function_args_size != 0)
- {
- size += 4; /* keep stack aligned */
- frame_size = size; /* must push data or access args */
- }
-
- if (size)
- {
- if (size < 16)
- fprintf (file, "\tsubq $%d,sp\n", size);
- else
- fprintf (file, "\tsubi $%d,sp\n", size);
-
- /* register save slots are relative to sp, because we have small positive
- displacements and this works whether we have a frame pointer or not */
-
- offset = 0;
- for (i = 16; i < 32; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- {
- if (offset == 0)
- fprintf (file, "\tstord f%d,(sp)\n", i-16);
- else
- fprintf (file, "\tstord f%d,%d(sp)\n", i-16, offset);
- offset += 8;
- }
-
- for (i = 0; i < 16; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- {
- if (offset == 0)
- fprintf (file, "\tstorw r%d,(sp)\n", i);
- else
- fprintf (file, "\tstorw r%d,%d(sp)\n", i, offset);
- offset += 4;
- }
- }
-}
-
-static void
-clipper_output_function_epilogue (file, size)
- FILE *file;
- HOST_WIDE_INT size ATTRIBUTE_UNUSED;
-{
- int i, offset;
-
- if (frame_pointer_needed)
- {
- offset = -frame_size;
-
- for (i = 16; i < 32; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- {
- fprintf (file, "\tloadd %d(fp),f%d\n", offset, i-16);
- offset += 8;
- }
-
- for (i = 0; i < 16; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- {
- fprintf (file, "\tloadw %d(fp),r%d\n", offset, i);
- offset += 4;
- }
-
- fputs ("\tmovw fp,sp\n\tpopw sp,fp\n\tret sp\n",
- file);
- }
-
- else /* no frame pointer */
- {
- offset = 0;
-
- for (i = 16; i < 32; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- {
- if (offset == 0)
- fprintf (file, "\tloadd (sp),f%d\n", i-16);
- else
- fprintf (file, "\tloadd %d(sp),f%d\n", offset, i-16);
- offset += 8;
- }
-
- for (i = 0; i < 16; i++)
- if (regs_ever_live[i] && !call_used_regs[i])
- {
- if (offset == 0)
- fprintf (file, "\tloadw (sp),r%d\n", i);
- else
- fprintf (file, "\tloadw %d(sp),r%d\n", offset, i);
- offset += 4;
- }
-
- if (frame_size > 0)
- {
- if (frame_size < 16)
- fprintf (file, "\taddq $%d,sp\n", frame_size);
- else
- fprintf (file, "\taddi $%d,sp\n", frame_size);
- }
-
- fputs ("\tret sp\n", file);
- }
-}
-
-/*
- * blockmove
- *
- * clipper_movstr ()
- */
-void
-clipper_movstr (operands)
- rtx *operands;
-{
- rtx dst,src,cnt,tmp,top,bottom=NULL_RTX,xops[3];
- int align;
- int fixed;
-
- extern FILE *asm_out_file;
-
- dst = operands[0];
- src = operands[1];
- /* don't change this operands[2]; gcc 2.3.3 doesn't honor clobber note */
- align = INTVAL (operands[3]);
- tmp = operands[4];
- cnt = operands[5];
-
- if (GET_CODE (operands[2]) == CONST_INT) /* fixed size move */
- {
- if ((fixed = INTVAL (operands[2])) <= 0)
- abort ();
-
- if (fixed <16)
- output_asm_insn ("loadq %2,%5", operands);
- else
- output_asm_insn ("loadi %2,%5", operands);
- }
- else
- {
- fixed = 0;
- bottom = (rtx)gen_label_rtx (); /* need a bottom label */
- xops[0] = cnt; xops[1] = bottom;
- output_asm_insn ("movw %2,%5", operands); /* count is scratch reg 5 */
- output_asm_insn ("brle %l1", xops);
- }
-
-
- top = (rtx)gen_label_rtx (); /* top of loop label */
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (top));
-
-
- xops[0] = src; xops[1] = tmp; xops[2] = dst;
-
- if (fixed && (align & 0x3) == 0) /* word aligned move with known size */
- {
- if (fixed >= 4)
- {
- rtx xops1[2];
- output_asm_insn(
- "loadw %a0,%1\n\taddq $4,%0\n\tstorw %1,%a2\n\taddq $4,%2",
- xops);
-
- xops1[0] = cnt; xops1[1] = top;
- output_asm_insn ("subq $4,%0\n\tbrgt %l1", xops1);
- }
-
- if (fixed & 0x2)
- {
- output_asm_insn ("loadh %a0,%1\n\tstorh %1,%a2", xops);
- if (fixed & 0x1)
- output_asm_insn ("loadb 2%a0,%1\n\tstorb %1,2%a2", xops);
- }
- else
- if (fixed & 0x1)
- output_asm_insn ("loadb %a0,%1\n\tstorb %1,%a2", xops);
- }
- else
- {
- output_asm_insn(
- "loadb %a0,%1\n\taddq $1,%0\n\tstorb %1,%a2\n\taddq $1,%2",
- xops);
-
- xops[0] = cnt; xops[1] = top;
- output_asm_insn ("subq $1,%0\n\tbrgt %l1", xops);
- }
-
- if (fixed == 0)
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (bottom));
-}
-
-\f
-void
-print_operand_address (file, addr)
- FILE *file;
- register rtx addr;
-{
- rtx op0,op1;
-
- switch (GET_CODE (addr))
- {
- case REG:
- fprintf (file, "(%s)", reg_names[REGNO (addr)]);
- break;
-
- case PLUS:
- /* can be 'symbol + reg' or 'reg + reg' */
-
- op0 = XEXP (addr, 0);
- op1 = XEXP (addr, 1);
-
- if (GET_CODE (op0) == REG && GET_CODE (op1) == REG)
- {
- fprintf (file, "[%s](%s)",
- reg_names[REGNO (op0)], reg_names[REGNO (op1)]);
- break;
- }
-
- if (GET_CODE (op0) == REG && CONSTANT_ADDRESS_P (op1))
- {
- output_addr_const (file, op1);
- fprintf (file, "(%s)", reg_names[REGNO (op0)]);
- break;
- }
-
- if (GET_CODE (op1) == REG && CONSTANT_ADDRESS_P (op0))
- {
- output_addr_const (file, op0);
- fprintf (file, "(%s)", reg_names[REGNO (op1)]);
- break;
- }
- abort (); /* Oh no */
-
- default:
- output_addr_const (file, addr);
- }
-}
-
-\f
-const char *
-rev_cond_name (op)
- rtx op;
-{
- switch (GET_CODE (op))
- {
- case EQ:
- return "ne";
- case NE:
- return "eq";
- case LT:
- return "ge";
- case LE:
- return "gt";
- case GT:
- return "le";
- case GE:
- return "lt";
- case LTU:
- return "geu";
- case LEU:
- return "gtu";
- case GTU:
- return "leu";
- case GEU:
- return "ltu";
-
- default:
- abort ();
- }
-}
-
-\f
-/* Dump the argument register to the stack; return the location
- of the block. */
-
-struct rtx_def *
-clipper_builtin_saveregs ()
-{
- rtx block, addr, r0_addr, r1_addr, f0_addr, f1_addr, mem;
- int set = get_varargs_alias_set ();
-
- /* Allocate the save area for r0,r1,f0,f1 */
-
- block = assign_stack_local (BLKmode, 6 * UNITS_PER_WORD, 2 * BITS_PER_WORD);
-
- RTX_UNCHANGING_P (block) = 1;
- RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
-
- addr = XEXP (block, 0);
-
- r0_addr = addr;
- r1_addr = plus_constant (addr, 4);
- f0_addr = plus_constant (addr, 8);
- f1_addr = plus_constant (addr, 16);
-
- /* Store int regs */
-
- mem = gen_rtx_MEM (SImode, r0_addr);
- set_mem_alias_set (mem, set);
- emit_move_insn (mem, gen_rtx_REG (SImode, 0));
-
- mem = gen_rtx_MEM (SImode, r1_addr);
- set_mem_alias_set (mem, set);
- emit_move_insn (mem, gen_rtx_REG (SImode, 1));
-
- /* Store float regs */
-
- mem = gen_rtx_MEM (DFmode, f0_addr);
- set_mem_alias_set (mem, set);
- emit_move_insn (mem, gen_rtx_REG (DFmode, 16));
-
- mem = gen_rtx_MEM (DFmode, f1_addr);
- set_mem_alias_set (mem, set);
- emit_move_insn (mem, gen_rtx_REG (DFmode, 17));
-
- return addr;
-}
-
-tree
-clipper_build_va_list ()
-{
- tree record, ap, reg, num;
-
- /*
- struct
- {
- int __va_ap; // pointer to stack args
- void *__va_reg[4]; // pointer to r0,f0,r1,f1
- int __va_num; // number of args processed
- };
- */
-
- record = make_node (RECORD_TYPE);
-
- num = build_decl (FIELD_DECL, get_identifier ("__va_num"),
- integer_type_node);
- DECL_FIELD_CONTEXT (num) = record;
-
- reg = build_decl (FIELD_DECL, get_identifier ("__va_reg"),
- build_array_type (ptr_type_node,
- build_index_type (build_int_2 (3, 0))));
- DECL_FIELD_CONTEXT (reg) = record;
- TREE_CHAIN (reg) = num;
-
- ap = build_decl (FIELD_DECL, get_identifier ("__va_ap"),
- integer_type_node);
- DECL_FIELD_CONTEXT (ap) = record;
- TREE_CHAIN (ap) = reg;
-
- TYPE_FIELDS (record) = ap;
- layout_type (record);
-
- return record;
-}
-
-void
-clipper_va_start (stdarg_p, valist, nextarg)
- int stdarg_p;
- tree valist;
- rtx nextarg ATTRIBUTE_UNUSED;
-{
- tree ap_field, reg_field, num_field;
- tree t, u, save_area;
-
- ap_field = TYPE_FIELDS (TREE_TYPE (valist));
- reg_field = TREE_CHAIN (ap_field);
- num_field = TREE_CHAIN (reg_field);
-
- ap_field = build (COMPONENT_REF, TREE_TYPE (ap_field), valist, ap_field);
- reg_field = build (COMPONENT_REF, TREE_TYPE (reg_field), valist, reg_field);
- num_field = build (COMPONENT_REF, TREE_TYPE (num_field), valist, num_field);
-
- /* Call __builtin_saveregs to save r0, r1, f0, and f1 in a block. */
-
- save_area = make_tree (integer_type_node, expand_builtin_saveregs ());
-
- /* Set __va_ap. */
-
- t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
- if (stdarg_p && current_function_args_info.size != 0)
- t = build (PLUS_EXPR, ptr_type_node, t,
- build_int_2 (current_function_args_info.size, 0));
- t = build (MODIFY_EXPR, TREE_TYPE (ap_field), ap_field, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- /* Set the four entries of __va_reg. */
-
- t = build1 (NOP_EXPR, ptr_type_node, save_area);
- u = build (ARRAY_REF, ptr_type_node, reg_field, build_int_2 (0, 0));
- t = build (MODIFY_EXPR, ptr_type_node, u, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- t = fold (build (PLUS_EXPR, integer_type_node, save_area,
- build_int_2 (8, 0)));
- t = build1 (NOP_EXPR, ptr_type_node, save_area);
- u = build (ARRAY_REF, ptr_type_node, reg_field, build_int_2 (1, 0));
- t = build (MODIFY_EXPR, ptr_type_node, u, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- t = fold (build (PLUS_EXPR, integer_type_node, save_area,
- build_int_2 (4, 0)));
- t = build1 (NOP_EXPR, ptr_type_node, save_area);
- u = build (ARRAY_REF, ptr_type_node, reg_field, build_int_2 (2, 0));
- t = build (MODIFY_EXPR, ptr_type_node, u, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- t = fold (build (PLUS_EXPR, integer_type_node, save_area,
- build_int_2 (16, 0)));
- t = build1 (NOP_EXPR, ptr_type_node, save_area);
- u = build (ARRAY_REF, ptr_type_node, reg_field, build_int_2 (3, 0));
- t = build (MODIFY_EXPR, ptr_type_node, u, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- /* Set __va_num. */
-
- t = build_int_2 (current_function_args_info.num, 0);
- t = build (MODIFY_EXPR, TREE_TYPE (num_field), num_field, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-}
-
-rtx
-clipper_va_arg (valist, type)
- tree valist, type;
-{
- tree ap_field, reg_field, num_field;
- tree addr, t;
- HOST_WIDE_INT align;
- rtx addr_rtx, over_label = NULL_RTX, tr;
-
- /*
- Integers:
-
- if (VA.__va_num < 2)
- addr = VA.__va_reg[2 * VA.__va_num];
- else
- addr = round(VA.__va_ap), VA.__va_ap = round(VA.__va_ap) + sizeof(TYPE);
- VA.__va_num++;
-
- Floats:
-
- if (VA.__va_num < 2)
- addr = VA.__va_reg[2 * VA.__va_num + 1];
- else
- addr = round(VA.__va_ap), VA.__va_ap = round(VA.__va_ap) + sizeof(TYPE);
- VA.__va_num++;
-
- Aggregates:
-
- addr = round(VA.__va_ap), VA.__va_ap = round(VA.__va_ap) + sizeof(TYPE);
- VA.__va_num++;
- */
-
- ap_field = TYPE_FIELDS (TREE_TYPE (valist));
- reg_field = TREE_CHAIN (ap_field);
- num_field = TREE_CHAIN (reg_field);
-
- ap_field = build (COMPONENT_REF, TREE_TYPE (ap_field), valist, ap_field);
- reg_field = build (COMPONENT_REF, TREE_TYPE (reg_field), valist, reg_field);
- num_field = build (COMPONENT_REF, TREE_TYPE (num_field), valist, num_field);
-
- addr_rtx = gen_reg_rtx (Pmode);
-
- if (! AGGREGATE_TYPE_P (type))
- {
- tree inreg;
- rtx false_label;
-
- over_label = gen_label_rtx ();
- false_label = gen_label_rtx ();
-
- emit_cmp_and_jump_insns (expand_expr (num_field, NULL_RTX, 0,
- OPTAB_LIB_WIDEN),
- GEN_INT (2), GE, const0_rtx,
- TYPE_MODE (TREE_TYPE (num_field)),
- TREE_UNSIGNED (num_field), false_label);
-
- inreg = fold (build (MULT_EXPR, integer_type_node, num_field,
- build_int_2 (2, 0)));
- if (FLOAT_TYPE_P (type))
- inreg = fold (build (PLUS_EXPR, integer_type_node, inreg,
- build_int_2 (1, 0)));
- inreg = fold (build (ARRAY_REF, ptr_type_node, reg_field, inreg));
-
- tr = expand_expr (inreg, addr_rtx, VOIDmode, EXPAND_NORMAL);
- if (tr != addr_rtx)
- emit_move_insn (addr_rtx, tr);
-
- emit_jump_insn (gen_jump (over_label));
- emit_barrier ();
- emit_label (false_label);
- }
-
- /* Round to alignment of `type', or at least integer alignment. */
-
- align = TYPE_ALIGN (type);
- if (align < TYPE_ALIGN (integer_type_node))
- align = TYPE_ALIGN (integer_type_node);
- align /= BITS_PER_UNIT;
-
- addr = fold (build (PLUS_EXPR, ptr_type_node, ap_field,
- build_int_2 (align-1, 0)));
- addr = fold (build (BIT_AND_EXPR, ptr_type_node, addr,
- build_int_2 (-align, -1)));
- addr = save_expr (addr);
-
- tr = expand_expr (addr, addr_rtx, Pmode, EXPAND_NORMAL);
- if (tr != addr_rtx)
- emit_move_insn (addr_rtx, tr);
-
- t = build (MODIFY_EXPR, TREE_TYPE (ap_field), ap_field,
- build (PLUS_EXPR, TREE_TYPE (ap_field),
- addr, build_int_2 (int_size_in_bytes (type), 0)));
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- if (over_label)
- emit_label (over_label);
-
- t = build (MODIFY_EXPR, TREE_TYPE (num_field), num_field,
- build (PLUS_EXPR, TREE_TYPE (num_field),
- num_field, build_int_2 (1, 0)));
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- return addr_rtx;
-}
-
-/* Return truth value of whether OP can be used as an word register
- operand. Reject (SUBREG:SI (REG:SF )) */
-
-int
-int_reg_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (register_operand (op, mode) &&
- (GET_CODE (op) != SUBREG ||
- GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_INT));
-}
-
-/* Return truth value of whether OP can be used as a float register
- operand. Reject (SUBREG:SF (REG:SI )) )) */
-
-int
-fp_reg_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (register_operand (op, mode) &&
- (GET_CODE (op) != SUBREG ||
- GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_FLOAT));
-}
-
-static void
-clix_asm_out_constructor (symbol, priority)
- rtx symbol;
- int priority ATTRIBUTE_UNUSED;
-{
- init_section ();
- fputs ("\tloada ", asm_out_file);
- assemble_name (asm_out_file, XSTR (symbol, 0));
- fputs (",r0\n\tsubq $8,sp\n\tstorw r0,(sp)\n", asm_out_file);
-}
-
-static void
-clix_asm_out_destructor (symbol, priority)
- rtx symbol;
- int priority ATTRIBUTE_UNUSED;
-{
- fini_section ();
- assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
- assemble_integer (const0_rtx, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Clipper version.
- Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1998,
- 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
- Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Print subsidiary information on the compiler version in use. */
-
-#define TARGET_VERSION fprintf (stderr, " (clipper)");
-
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags. */
-
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
- { { "c400", 1, N_("Generate code for the C400") }, \
- { "c300", -1, N_("Generate code for the C300") }, \
- { "", TARGET_DEFAULT, NULL} }
-
-#define TARGET_C400 1
-#define TARGET_C300 0
-
-/* Default target_flags if no switches specified. */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT TARGET_C300
-#endif
-
-/* Show that we can debug generated code without a frame pointer. */
-#define CAN_DEBUG_WITHOUT_FP
-\f
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields. */
-
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is the lowest
- numbered. */
-
-#define WORDS_BIG_ENDIAN 0
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 4
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY 32
-
-/* Largest alignment for stack parameters (if greater than PARM_BOUNDARY). */
-#define MAX_PARM_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 128
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this. */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct. */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this. */
-#define BIGGEST_ALIGNMENT 64
-
-/* No structure field wants to be aligned rounder than this. */
-#define BIGGEST_FIELD_ALIGNMENT 64
-
-/* Make strcpy of constants fast. */
-#define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
- ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons. */
-#define DATA_ALIGNMENT(TYPE, ALIGN) \
- (TREE_CODE (TYPE) == ARRAY_TYPE \
- && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
- && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Set this nonzero if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 1
-
-/* Let's keep the stack somewhat aligned. */
-#define STACK_BOUNDARY 64
-
-/* Define this macro if it is advisable to hold scalars in registers
- in a wider mode than that declared by the program. In such cases,
- the value is constrained to be within the bounds of the declared
- type, but kept valid in the wider mode. The signedness of the
- extension may differ from that of the type.
-
- For Clipper, we always store objects in a full register. */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
- if (GET_MODE_CLASS (MODE) == MODE_INT \
- && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
- { \
- (UNSIGNEDP) = 0; \
- (MODE) = SImode; \
- }
-
-
-/* Define this if function arguments should also be promoted using the above
- procedure. */
-
-/* FIXME: do we loose compatibility to acc if we define this? */
-
-/* #define PROMOTE_FUNCTION_ARGS */
-
-/* Likewise, if the function return value is promoted. */
-
-/* #define PROMOTE_FUNCTION_RETURN */
-
-\f
-/* Standard register usage. */
-
-/* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 32
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
- On the clipper, these are the FP and SP . */
-#define FIXED_REGISTERS \
-{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* Default: C300 */
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like. */
-#define CALL_USED_REGISTERS \
-{1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\
- 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* default: C300 */
-
-/* Zero or more C statements that may conditionally modify two
- variables `fixed_regs' and `call_used_regs' (both of type `char
- []') after they have been initialized from the two preceding
- macros. A C400 has additional floating registers f8 -> f15 */
-
-#define CONDITIONAL_REGISTER_USAGE \
- if (target_flags & TARGET_C400) \
- { int i; \
- for (i = 24; i < 32; i++) fixed_regs[i] = call_used_regs[i] = 0; }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers.
- On the clipper, fp registers are 64 bits. */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((REGNO) >= 16 ? 1 \
- : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- On the clipper 0-15 may hold any mode but DImode and DFmode must be even.
- Registers 16-31 hold SFmode and DFmode */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((REGNO) < 16 \
- ? (((MODE) != DImode && (MODE) != DFmode) || ((REGNO) & 1) == 0) \
- : ((MODE) == SFmode || (MODE) == DFmode))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-/* clipper has extra PC */
-/* #define PC_REGNUM */
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED \
- (! leaf_function_p ())
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
-
-/* Register in which static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM 2
-
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM 0
-\f
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
-/* The clipper has general and FP regs. */
-
-enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file. */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. */
-
-#define REG_CLASS_CONTENTS { {0}, {0x0000ffff}, {0xffff0000}, {0xffffffff} }
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-#define REGNO_REG_CLASS(REGNO) ((REGNO) >= 16 ? FLOAT_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'r' ? GENERAL_REGS : ((C) == 'f' ? FLOAT_REGS: NO_REGS))
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C. */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* Similar, but for floating constants, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* Optional extra constraints for this machine. */
-
-/* #define EXTRA_CONSTRAINT(OP, C) */
-
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS. */
-
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((CLASS) == FLOAT_REGS \
- ? 1 \
- : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-\f
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- that is, each additional local variable allocated
- goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated. */
-#define STARTING_FRAME_OFFSET 0
-
-/* Given an rtx for the address of a frame,
- return an rtx for the address of the word in the frame
- that holds the dynamic chain--the previous frame's address. */
-#define DYNAMIC_CHAIN_ADDRESS(frame) (frame)
-
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by. */
-
-/* #define PUSH_ROUNDING(BYTES) (BYTES) */
-
-/* Keep the stack pointer constant throughout the function. */
-/* we can't set this for clipper as library calls may have 3 args and we pass
- only 2 args in regs. */
-
-/* #define ACCUMULATE_OUTGOING_ARGS 1*/
-
-
-/* Offset of first parameter from the argument pointer register value.
- size of PC + FP */
-
-#define FIRST_PARM_OFFSET(FNDECL) 8
-
-/* Value is the number of bytes of arguments automatically
- popped when returning from a subroutine call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
- SIZE is the number of bytes of arguments passed on the stack. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), ((TYPE_MODE (VALTYPE) == SFmode ||\
- TYPE_MODE (VALTYPE) == DFmode) ? \
- 16 : 0))
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG ((MODE), ((MODE) == SFmode || (MODE) == DFmode ? 16 : 0))
-
-
-/* 1 if N is a possible register number for a function value
- as seen by the caller. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
-
-/* 1 if N is a possible register number for function argument passing. */
-
-#define FUNCTION_ARG_REGNO_P(N) \
- ((N) == 0 || (N) == 1 || (N) == 16 || (N) == 17)
-
-/* Define this if PCC uses the nonreentrant convention for returning
- structure and union values. Old Green Hills C-Clipper returns static
- structs but the newer Apogee compiler passes structs as hidden arg 0.
- Structs etc are always passed in memory */
-
-/* #define PCC_STATIC_STRUCT_RETURN */
-
-\f
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go.
-
- Clipper uses 2 register 'slots' that pass arguments in r0/r1 or f0/f1.
- An argument that must be passed in memory (struct... ) leaves that slot
- free.
- We pass 'long long' only in registers when both slots are free.
- Returned structs must be allocated by the caller, the address is passed
- in r0.
-
- struct ss {..}
-
- fun (i,j,k) i in r0, j in r1, k on stack
- fun (s,j,k) s on stack, j in r1, k on stack
- fun (i,s,k) i in r0, s on stack, k on stack
- s1 = fun (i,s,k) &s1 in r0, i in r1, s on stack, k on stack
-
- We must keep enough information for varargs/stdargs.
-
- _clipper_cum_args is a struct of 2 integers, with
- num = slots used
- size = size of all stack args = offset to next arg without alignment
-
- If we use stdarg.h, size points to the first unnamed arg,
- see va-clipper.h */
-
-struct _clipper_cum_args { int num; int size; };
-
-#define CUMULATIVE_ARGS struct _clipper_cum_args
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0.
-
- clipper passes the address of a struct in r0, set num = 1 in this case */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
- ((CUM).num = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE (FNTYPE))), \
- (CUM).size = 0)
-
-/* internal helper : size of an argument */
-
-#define CLIPPER_ARG_SIZE(MODE, TYPE) \
-(((MODE) != BLKmode \
- ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
- : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) \
- * UNITS_PER_WORD)
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.) */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-do \
-{ \
- int reg = 0; \
- \
- if ((CUM).num < 2 \
- && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT) \
- && (GET_MODE_SIZE (MODE) <= 8) \
- && ((TYPE) == NULL || !AGGREGATE_TYPE_P(TYPE)) \
- && ((MODE) != DImode || (CUM).num == 0)) \
- { \
- reg = 1; \
- if ((MODE) == DImode) \
- (CUM).num = 1; \
- } \
- \
- (CUM).num++; \
- \
- if (! reg) \
- { \
- int align = FUNCTION_ARG_BOUNDARY (MODE, TYPE) / BITS_PER_UNIT; \
- (CUM).size += align - 1; \
- (CUM).size &= ~(align - 1); \
- (CUM).size += CLIPPER_ARG_SIZE (MODE, TYPE); \
- } \
-} while (0)
-
-/* Define where to put the arguments to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis).
-
- 2 args may go into regs. These must be MODE_INT or MODE_FLOAT but only
- if they really fit into ONE register. The exception is a DImode arg
- that occupies both register slots. */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
- (((CUM).num < 2 \
- && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT) \
- && (GET_MODE_SIZE (MODE) <= 8) \
- && ((TYPE) == NULL || !AGGREGATE_TYPE_P(TYPE)) \
- && ((MODE) != DImode || (CUM).num == 0)) \
- ? gen_rtx_REG ((MODE), \
- GET_MODE_CLASS(MODE) == MODE_FLOAT \
- ? (CUM).num+16 : (CUM).num) \
- : 0)
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
- of an argument with the specified mode and type. If it is not defined,
- `PARM_BOUNDARY' is used for all arguments. */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
- (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_SIZE (MODE)) <= PARM_BOUNDARY \
- ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
-
-/* For an arg passed partly in registers and partly in memory,
- this is the number of registers used.
- For args passed entirely in registers or entirely in memory, zero.
- Clipper never passed args partially in regs/mem. */
-
-/* #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 */
-
-/* Generate necessary RTL for __builtin_saveregs().
- ARGLIST is the argument list; see expr.c. */
-
-#define EXPAND_BUILTIN_SAVEREGS() clipper_builtin_saveregs ()
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) /* FIXME */
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Store in the variable DEPTH the initial difference between the
- frame pointer reg contents and the stack pointer reg contents,
- as of the start of the function body. This depends on the layout
- of the fixed parts of the stack frame and on how registers are saved. */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
- DEPTH = clipper_frame_size (get_frame_size ())
-
-
-/* Output assembler code for a block containing the constant parts
- of a trampoline, leaving space for the variable parts. */
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
-{ \
- fputs ("\t.word 0x459F,0x0004\t# call sp,.+4\n", FILE); \
- fputs ("\tmovw (sp),r3\n", FILE); \
- fputs ("\taddq $4,sp\n", FILE); \
- fputs ("\tloadw 20(r3),r2\n", FILE); \
- fputs ("\tloadw 24(r3),r3\n", FILE); \
- fputs ("\tb (r3)\n", FILE); \
- fputs ("\t.long 0,0\n", FILE); \
-}
-
-/* Length in units of the trampoline for entering a nested function. */
-
-#define TRAMPOLINE_SIZE 32
-
-/* Alignment required for a trampoline. 128 is used to find the
- beginning of a line in the instruction cache and to allow for
- instruction cache lines of up to 128 bytes. */
-
-#define TRAMPOLINE_ALIGNMENT 128
-
-/* Section in which to place the trampoline. */
-
-#define TRAMPOLINE_SECTION text_section
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 24)), CXT); \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 28)), FNADDR); \
-}
-\f
-/* Addressing modes, and classification of registers for them. */
-
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
-
-#define REGNO_OK_FOR_INDEX_P(regno) \
-((regno) < 16 || (unsigned)reg_renumber[regno] < 16)
-#define REGNO_OK_FOR_BASE_P(regno) \
-((regno) < 16 || (unsigned)reg_renumber[regno] < 16)
-\f
-/* Maximum number of registers that can appear in a valid memory address. */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* 1 if X is an rtx for a constant that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
- /* clipper doesn't have true indexing */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-
-#define REG_OK_FOR_INDEX_P(X) \
- (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
-
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-
-#define REG_OK_FOR_BASE_P(X) \
- (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) (REGNO(X) < 16)
-
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) (REGNO(X) < 16)
-
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
- except for CONSTANT_ADDRESS_P which is actually machine-independent. */
-
-/* Non-zero if X is an address which can be indirected. */
-
-#define INDIRECTABLE_CONSTANT_ADDRESS_P(X) 0
-
-#define INDIRECTABLE_ADDRESS_P(X) \
- (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
-
-/* Go to ADDR if X is a valid address not using indexing.
- (This much is the easy part.) */
-
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
-{ if (CONSTANT_ADDRESS_P (X)) goto ADDR; \
- if (INDIRECTABLE_ADDRESS_P (X)) goto ADDR; }
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ register rtx xfoo = (X); \
- GO_IF_NONINDEXED_ADDRESS (xfoo, ADDR); \
- if (GET_CODE (xfoo) == PLUS) \
- { register rtx xfoo0, xfoo1; \
- xfoo0 = XEXP (xfoo, 0); \
- xfoo1 = XEXP (xfoo, 1); \
- /* handle reg + reg -> [r1](r0) */ \
- if (INDIRECTABLE_ADDRESS_P (xfoo0) && INDIRECTABLE_ADDRESS_P (xfoo1)) \
- goto ADDR; \
- /* Handle <symbol>(reg) -> xxx(r0) */ \
- if (INDIRECTABLE_ADDRESS_P (xfoo0) && CONSTANT_ADDRESS_P (xfoo1)) \
- goto ADDR; \
- if (INDIRECTABLE_ADDRESS_P (xfoo1) && CONSTANT_ADDRESS_P (xfoo0)) \
- goto ADDR; }}
-
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output.
-
- For the clipper, nothing needs to be done. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
-
-\f
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this if the case instruction drops through after the table
- when the index is out of range. Don't define it if the case insn
- jumps to the default label instead. */
-/* #define CASE_DROPS_THROUGH */
-
-/* Define if operations between registers always perform the operation
- on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
- will either zero-extend or sign-extend. The value of this macro should
- be the code that says which one of the two operations is implicitly
- done, NIL if none. */
-#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
-
-/* Define this as 1 if `char' should by default be signed; else as 0. */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
- also convert validly to an unsigned one. */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
- in one reasonably fast instruction. */
-#define MOVE_MAX 4
-
-/* If a memory-to-memory move would take MOVE_RATIO or more simple
- move-instruction pairs, we will do a movstr or libcall instead.
-
- Make this large on clipper, since the block move is very
- inefficient with small blocks, and the hard register needs of the
- block move require much reload work. */
-
-#define MOVE_RATIO 20
-
-/* Nonzero if access to memory by bytes is slow and undesirable. */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
- which implies one can omit a sign-extension or zero-extension
- of a shift count. */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
- After generation of rtl, the compiler makes no further distinction
- between pointers and any other objects of this machine mode. */
-#define Pmode SImode
-
-/* A function address in a call instruction
- is a byte address (for indexing purposes)
- so give the MEM rtx a byte's mode. */
-#define FUNCTION_MODE QImode
-
-/* This machine uses IEEE floats. */
-
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-/* Check a `double' value for validity for a particular machine mode.
- This is defined to avoid crashes outputting certain constants.
- Since we output the number in hex, the assembler won't choke on it. */
-/* #define CHECK_FLOAT_VALUE(MODE,VALUE) */
-
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-/* On a Clipper, constants from 0..15 are cheap because they can use the
- 'quick' mode. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST_INT: \
- if (0 <= INTVAL (RTX) && INTVAL(RTX) <= 15 ) return 0; \
- return 1; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 3; \
- case CONST_DOUBLE: \
- return 5;
-
-/* Provide the costs of a rtl expression. This is in the body of a
- switch on CODE. */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE) \
- case MULT: \
- return COSTS_N_INSNS (4); \
- case DIV: \
- case UDIV: \
- case MOD: \
- case UMOD: \
- return COSTS_N_INSNS (40); \
- case ASHIFT: \
- case LSHIFTRT: \
- case ASHIFTRT: \
- return COSTS_N_INSNS (2); \
- case SIGN_EXTEND: \
- return (GET_CODE (XEXP (X,0)) == REG ? COSTS_N_INSNS (3) : 4);
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
- should be added to avoid a branch */
-
-/* #define BRANCH_COST 0 */
-
-\f
-/* Tell final.c how to eliminate redundant test instructions. */
-
-/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). No extra ones are needed for the clipper. */
-
-/* Store in cc_status the expressions
- that the condition codes will describe
- after execution of an instruction whose pattern is EXP.
- Do not alter them if the instruction would not alter the cc's. */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ \
- enum attr_cc cc = get_attr_cc (INSN); \
- rtx dest = SET_DEST (EXP); \
- switch (cc) \
- { \
- case CC_CHANGE0: \
- if (GET_CODE (EXP) == PARALLEL) abort(); \
- if ((cc_status.value1 && rtx_equal_p (dest, cc_status.value1)) || \
- (cc_status.value2 && rtx_equal_p (dest, cc_status.value2))) \
- CC_STATUS_INIT; \
- break; \
- \
- case CC_SET1: \
- if (GET_CODE (EXP) == PARALLEL) abort(); \
- cc_status.flags = 0; \
- cc_status.value1 = dest; \
- cc_status.value2 = 0; \
- break; \
- \
- case CC_SET2: \
- if (GET_CODE (EXP) == PARALLEL) abort(); \
- cc_status.flags = 0; \
- cc_status.value1 = dest; \
- cc_status.value2 = SET_SRC (EXP); \
- break; \
- \
- case CC_UNCHANGED: \
- break; \
- \
- case CC_CLOBBER: \
- CC_STATUS_INIT; \
- break; \
- \
- default: \
- abort (); \
- } \
-}
-
-\f
-/* Control the assembler format that we output. */
-
-/* Output at beginning of assembler file. */
-
-#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n");
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output before read-only data. */
-
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", \
- "r9", "r10", "r11", "r12", "r13", "fp", "sp", \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", \
- "f9", "f10", "f11", "f12", "f13", "f14", "f15" }
-
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
- do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tsubq $8,sp\n\t%s %s,(sp)\n", \
- (REGNO) < 16 ? "storw" : "stord", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\t%s (sp),%s\n\taddq $8,sp\n", \
- (REGNO) < 16 ? "loadw" : "loadd", reg_names[REGNO])
-/* This is how to output an element of a case-vector that is absolute */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- fprintf (FILE, "\t.long .L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative. */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
- that says to advance the location counter by SIZE bytes. */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-/* ??? The use of .bss here seems odd. */
-
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
-( data_section (), \
- fputs ("\t.bss\t", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN)/BITS_PER_UNIT))
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Print an instruction operand X on file FILE.
- CODE is the code from the %-spec that requested printing this operand;
- if `%z3' was used to print operand 3, then CODE is 'z'.
-
-Clipper operand formatting codes:
-
- letter print
- C reverse branch condition
-*/
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
- ((CODE) == 'C')
-
-#define PRINT_OPERAND(FILE, X, CODE) \
-{ if (CODE == 'C') \
- fputs (rev_cond_name (X), FILE); \
- else if (GET_CODE (X) == REG) \
- fprintf (FILE, "%s", reg_names[REGNO (X)]); \
- else if (GET_CODE (X) == MEM) \
- output_address (XEXP (X, 0)); \
- else { putc ('$', FILE); output_addr_const (FILE, X); }}
-
-/* Print a memory operand whose address is X, on file FILE.
- This uses a function in output-clipper.c. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
- print_operand_address (FILE, ADDR)
-
-/* Define the codes that are matched by predicates in clipper.c */
-
-#define PREDICATE_CODES \
- {"int_reg_operand", {SUBREG, REG}}, \
- {"fp_reg_operand", {SUBREG, REG}},
-\f
-/* Define the `__builtin_va_list' type for the ABI. */
-#define BUILD_VA_LIST_TYPE(VALIST) \
- (VALIST) = clipper_build_va_list ()
-
-/* Implement `va_start' for varargs and stdarg. */
-#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
- clipper_va_start (stdarg, valist, nextarg)
-
-/* Implement `va_arg'. */
-#define EXPAND_BUILTIN_VA_ARG(valist, type) \
- clipper_va_arg (valist, type)
+++ /dev/null
-;;- Machine description for GNU compiler, Clipper Version
-;; Copyright (C) 1987, 1988, 1991, 1993, 1994, 1997, 1998, 1999, 2001
-;; Free Software Foundation, Inc.
-;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- Instruction patterns. When multiple patterns apply,
-;;- the first one in the file is chosen.
-;;-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;
-;; define attributes
-;;
-;; instruction type
-;;
-;; unknown is temporary in order to generate 'cc clobber' until attribute
-;; assignment is consistent
-;;
-(define_attr "type" "load,store,arith,fp,branch,unknown"
- (const_string "unknown"))
-
-;; condition code setting
-;;
-;; clobber destroyed
-;; unchanged
-;; set1 set cc_status.value1, e.g. sub r0,r1
-;; set2 set value1 and value2, e.g. mov r0,r1
-;; change0 may be side effect, i.e. load mem,r0
-;;
-;; note: loadi and loadq are 'arith' instructions that set the condition codes
-;; mul,div,mod do NOT set the condition codes
-;;
-(define_attr "cc" "clobber,unchanged,set1,set2,change0"
- (cond [(eq_attr "type" "load") (const_string "change0")
- (eq_attr "type" "store,branch") (const_string "unchanged")
- (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "")
- (const_string "set1")
- (const_string "clobber"))
- ]
- (const_string "clobber")))
-
-;;
-;; clipper seems to be a traditional risc processor
-;; we define a functional unit 'memory'
-;;
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0)
-
-\f
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information. Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
- [(set (cc0)
- (match_operand:SI 0 "int_reg_operand" "r"))]
- ""
- "cmpq $0,%0")
-
-(define_insn "cmpsi"
- [(set (cc0)
- (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n")
- (match_operand:SI 1 "nonmemory_operand" "r,n,r")))]
- ""
- "*
-{
- int val;
-
- if (which_alternative == 0)
- return \"cmpw %1,%0\";
-
- if (which_alternative == 1)
- {
- val = INTVAL (operands[1]);
- if (0 <= val && val < 16)
- return \"cmpq %1,%0\";
- return \"cmpi %1,%0\";
- }
-
- cc_status.flags |= CC_REVERSED; /* immediate must be first */
-
- val = INTVAL (operands[0]);
-
- if (0 <= val && val < 16)
- return \"cmpq %0,%1\";
-
- return \"cmpi %0,%1\";
-}")
-
-(define_insn "cmpdf"
- [(set (cc0)
- (compare (match_operand:DF 0 "fp_reg_operand" "f")
- (match_operand:DF 1 "fp_reg_operand" "f")))]
- ""
- "cmpd %1,%0")
-
-(define_insn "cmpsf"
- [(set (cc0)
- (compare (match_operand:SF 0 "fp_reg_operand" "f")
- (match_operand:SF 1 "fp_reg_operand" "f")))]
- ""
- "cmps %1,%0")
-
-\f
-;;
-;; double and single float move
-;;
-(define_expand "movdf"
- [(set (match_operand:DF 0 "general_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = force_reg (DFmode,
- force_const_mem (DFmode, operands[1]));
- else if (GET_CODE (operands[1]) != REG)
- operands[1] = force_reg (DFmode, operands[1]);
- }
-
- else if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = force_const_mem (DFmode, operands[1]);
-}")
-
-;;
-;; provide two patterns with different predicates as we don't want combine
-;; to recombine a mem -> mem move
-;;
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=*rf")
- (match_operand:DF 1 "nonimmediate_operand" "*rfo"))]
- ""
- "*
-{
-#define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
-
- if (FP_REG_P (operands[0]))
- {
- if (FP_REG_P (operands[1])) /* f -> f */
- return \"movd %1,%0\";
-
- if (GET_CODE (operands[1]) == REG) /* r -> f */
- return \"movld %1,%0\";
-
- return \"loadd %1,%0\"; /* m -> f */
- }
-
- if (FP_REG_P (operands[1]))
- {
- if (GET_CODE (operands[0]) == REG) /* f -> r */
- return \"movdl %1,%0\";
-
- abort ();
- }
-
- if (GET_CODE (operands[1]) == MEM) /* m -> r */
- {
- rtx xops[4];
- xops[0] = operands[0];
- xops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- xops[2] = operands[1];
- xops[3] = adjust_address (operands[1], SImode, 4);
- output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops);
- return \"\";
- }
-
- if (GET_CODE (operands[1]) == REG) /* r -> r */
- {
- rtx xops[4];
- xops[0] = operands[0];
- xops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- xops[2] = operands[1];
- xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops);
- return \"\";
- }
-
- abort ();
-#undef FP_REG_P
-}")
-
-
-(define_insn ""
- [(set (match_operand:DF 0 "memory_operand" "=o,m")
- (match_operand:DF 1 "register_operand" "*rf,f"))]
- ""
- "*
-{
- rtx xops[4];
-
- if (REGNO (operands[1]) >= 16) /* f -> m */
- return \"stord %1,%0\";
-
- xops[0] = operands[0]; /* r -> o */
- xops[1] = adjust_address (operands[0], SImode, 4);
- xops[2] = operands[1];
- xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
- return \"\";
-}"
-[(set_attr "type" "store,store")
- (set_attr "cc" "clobber,unchanged")])
-
-
-(define_expand "movsf"
- [(set (match_operand:SF 0 "general_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = force_reg (SFmode,
- force_const_mem (SFmode, operands[1]));
- else if (GET_CODE (operands[1]) != REG)
- operands[1] = force_reg (SFmode, operands[1]);
- }
-
- else if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = force_const_mem (SFmode, operands[1]);
-}")
-
-;;
-;; provide two patterns with different predicates as we don't want combine
-;; to recombine a mem -> mem move
-;;
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=*rf")
- (match_operand:SF 1 "nonimmediate_operand" "*rfm"))]
- ""
- "*
-{
-#define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
-
- if (FP_REG_P (operands[0]))
- {
- if (FP_REG_P (operands[1])) /* f -> f */
- return \"movs %1,%0\";
- if (GET_CODE (operands[1]) == REG) /* r -> f */
- return
- \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\";
- return \"loads %1,%0\"; /* m -> f */
- }
-
- if (FP_REG_P (operands[1]))
- {
- if (GET_CODE (operands[0]) == REG) /* f -> r */
- return
- \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\";
- abort ();
- }
-
- if (GET_CODE (operands[1]) == MEM) /* m -> r */
- return \"loadw %1,%0\";
-
- if (GET_CODE (operands[1]) == REG) /* r -> r */
- return \"movw %1,%0\";
-
- abort ();
-#undef FP_REG_P
-}")
-
-(define_insn ""
- [(set (match_operand:SF 0 "memory_operand" "=m")
- (match_operand:SF 1 "register_operand" "*rf"))]
- ""
- "*
-{
- if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16)
- return \"stors %1,%0\"; /* f-> m */
-
- return \"storw %1,%0\"; /* r -> m */
-}"
-[(set_attr "type" "store")])
-
-
-(define_expand "movdi"
- [(set (match_operand:DI 0 "general_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
- operands[1] = force_reg (DImode, operands[1]);
-}")
-
-;; If an operand is a MEM but not offsettable, we can't load it into
-;; a register, so we must force the third alternative to be the one
-;; reloaded. Hence we show the first as more expensive.
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=?r,r,r")
- (match_operand:DI 1 "general_operand" "r,n,o"))]
- ""
- "*
-{
- rtx xoperands[2],yoperands[2];
-
- xoperands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-
- if (which_alternative == 0) /* r -> r */
- {
- output_asm_insn (\"movw %1,%0\", operands);
- xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- output_asm_insn (\"movw %1,%0\", xoperands);
- return \"\";
- }
-
- if (which_alternative == 1) /* n -> r */
- {
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- output_asm_insn (\"loadi %1,%0\", operands);
- output_asm_insn (\"loadq $0,%0\", xoperands);
- return \"\";
- }
-
- if (GET_CODE (operands[1]) != CONST_DOUBLE)
- abort ();
-
- yoperands[0] = operands[0];
- yoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
- output_asm_insn (\"loadi %1,%0\", yoperands);
-
- xoperands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
- output_asm_insn (\"loadi %1,%0\", xoperands);
- return \"\";
- }
- /* m -> r */
- output_asm_insn (\"loadw %1,%0\", operands);
- xoperands[1] = adjust_address (operands[1], SImode, 4);
- output_asm_insn (\"loadw %1,%0\", xoperands);
- return \"\";
-}"
-[(set_attr "type" "arith,arith,load")
- (set_attr "cc" "clobber,clobber,clobber")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "memory_operand" "=o")
- (match_operand:DI 1 "register_operand" "r"))]
- ""
- "*
-{
- rtx xops[4];
- xops[0] = operands[0];
- xops[1] = adjust_address (operands[0], SImode, 4);
- xops[2] = operands[1];
- xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
- return \"\";
-}"
-[(set_attr "type" "store")
- (set_attr "cc" "clobber")])
-
-(define_expand "movsi"
- [(set (match_operand:SI 0 "general_operand" "")
- (match_operand:SI 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM &&
- GET_CODE (operands[1]) != REG)
- operands[1] = force_reg (SImode, operands[1]);
-}")
-
-;; Reject both args with `general_operand' if not reloading because a
-;; mem -> mem move that was split by 'movsi' can be recombined to
-;; mem -> mem by the combiner.
-;;
-;; As a pseudo register can end up in a stack slot during reloading we must
-;; allow a r->m move for the next pattern.
-;; The first predicate must be `general_operand' because a predicate must
-;; be true for each constraint.
-;;
-(define_insn ""
- [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m")
- (match_operand:SI 1 "general_operand" "r,m,n,i,r"))]
- "reload_in_progress || register_operand (operands[0], SImode)"
- "*
-{
- int val;
-
- if (which_alternative == 0)
- return \"movw %1,%0\"; /* reg -> reg */
-
- if (which_alternative == 1)
- return \"loadw %1,%0\"; /* mem -> reg */
-
- if (which_alternative == 2)
- {
- val = INTVAL (operands[1]); /* known const ->reg */
-
- if (val == -1)
- return \"notq $0,%0\";
-
- if (val < 0 || val >= 16)
- return \"loadi %1,%0\";
-
- return \"loadq %1,%0\";
- }
-
- if (which_alternative == 3) /* unknown const */
- return \"loada %a1,%0\";
-
- return \"storw %1,%0\";
-}"
-[(set_attr "type" "arith,load,arith,load,store")
- (set_attr "cc" "set2,change0,set1,change0,unchanged")])
-
-
-(define_insn ""
- [(set (match_operand:SI 0 "memory_operand" "=m")
- (match_operand:SI 1 "int_reg_operand" "r"))]
- ""
- "storw %1,%0"
-[(set_attr "type" "store")])
-
-;; movhi
-;;
-;; loadh mem to reg
-;; storh reg to mem
-;;
-;;
-(define_expand "movhi"
- [(set (match_operand:HI 0 "general_operand" "")
- (match_operand:HI 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM
- && ! register_operand (operands[1], HImode))
- operands[1] = force_reg (HImode, operands[1]);
-}")
-
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r,r,r")
- (match_operand:HI 1 "general_operand" "r,m,n"))]
- ""
- "@
- movw %1,%0
- loadh %1,%0
- loadi %1,%0"
-[(set_attr "type" "arith,load,arith")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "memory_operand" "=m")
- (match_operand:HI 1 "register_operand" "r"))]
- ""
- "storh %1,%0"
- [(set_attr "type" "store")])
-
-;; movqi
-;;
-;; loadb mem to reg
-;; storb reg to mem
-;;
-(define_expand "movqi"
- [(set (match_operand:QI 0 "general_operand" "")
- (match_operand:QI 1 "general_operand" ""))]
- ""
- "
-{
- if (GET_CODE (operands[0]) == MEM &&
- ! register_operand (operands[1], QImode))
- operands[1] = force_reg (QImode, operands[1]);
-}")
-
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r,r,r")
- (match_operand:QI 1 "general_operand" "r,m,n"))]
- ""
- "@
- movw %1,%0
- loadb %1,%0
- loadi %1,%0"
-[(set_attr "type" "arith,load,arith")])
-
-(define_insn ""
- [(set (match_operand:QI 0 "memory_operand" "=m")
- (match_operand:QI 1 "register_operand" "r"))]
- ""
- "storb %1,%0"
-[(set_attr "type" "store")])
-
-\f
-;;
-;; block move
-;;
-(define_expand "movstrsi"
- [(parallel
- [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:SI 2 "general_operand" ""))
- (use (match_operand:SI 3 "const_int_operand" ""))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_dup 6))
- (clobber (match_dup 7))])]
- ""
- "
-{
- rtx addr0, addr1;
-
- addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
- addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-
- operands[6] = addr0;
- operands[7] = addr1;
-
- operands[0] = replace_equiv_address (operands[0], addr0);
- operands[1] = replace_equiv_address (operands[1], addr1);
-
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = force_reg (SImode, operands[2]);
-}")
-
-;;
-;; there is a problem with this insn in gcc-2.2.3
-;; (clobber (match_dup 2)) does not prevent use of this operand later
-;; we always use a scratch register and leave operand 2 unchanged
-;;
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
- (mem:BLK (match_operand:SI 1 "register_operand" "r")))
- (use (match_operand:SI 2 "nonmemory_operand" "rn"))
- (use (match_operand:SI 3 "const_int_operand" "n"))
- (clobber (match_scratch:SI 4 "=r"))
- (clobber (match_scratch:SI 5 "=r"))
- (clobber (match_dup 0))
- (clobber (match_dup 1))]
- ""
- "*
-{
- clipper_movstr (operands);
- return \"\";
-}"
-[(set_attr "cc" "clobber")])
-
-
-\f
-;; Extension and truncation insns.
-(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
- ""
- "@
- andi $65535,%0\;xori $32768,%0\;subi $32768,%0
- loadh %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
- (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
- ""
- "@
- andi $255,%0\;xori $128,%0\;subi $128,%0
- loadb %1,%0"
-[(set_attr "type" "arith,load")
- (set_attr "cc" "set1,change0")])
-
-
-(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
- ""
- "@
- andi $255,%0\;xori $128,%0\;subi $128,%0
- loadb %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "fp_reg_operand" "=f")
- (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))]
- ""
- "cnvsd %1,%0")
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "fp_reg_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))]
- ""
- "cnvds %1,%0")
-
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
- ""
- "@
- andi $65535,%0
- loadhu %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
- (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
- ""
- "@
- andi $255,%0
- loadbu %1,%0"
-[(set_attr "type" "arith,load")
- (set_attr "cc" "clobber,clobber")])
-
-
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
- ""
- "@
- andi $255,%0
- loadbu %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-\f
-;; Fix-to-float conversion insns.
-
-(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "fp_reg_operand" "=f")
- (float:SF (match_operand:SI 1 "int_reg_operand" "r")))]
- ""
- "cnvws %1,%0")
-
-(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "fp_reg_operand" "=f")
- (float:DF (match_operand:SI 1 "int_reg_operand" "r")))]
- ""
- "cnvwd %1,%0")
-
-
-;; Float-to-fix conversion insns.
-
-(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))]
- ""
- "cnvtsw %1,%0")
-
-(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))]
- ""
- "cnvtdw %1,%0")
-\f
-;;- All kinds of add instructions.
-
-(define_insn "adddf3"
- [(set (match_operand:DF 0 "fp_reg_operand" "=f")
- (plus:DF (match_operand:DF 1 "fp_reg_operand" "0")
- (match_operand:DF 2 "fp_reg_operand" "f")))]
- ""
- "addd %2,%0"
- [(set_attr "type" "fp")])
-
-
-(define_insn "addsf3"
- [(set (match_operand:SF 0 "fp_reg_operand" "=f")
- (plus:SF (match_operand:SF 1 "fp_reg_operand" "0")
- (match_operand:SF 2 "fp_reg_operand" "f")))]
- ""
- "adds %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "adddi3"
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (plus:DI (match_operand:DI 1 "int_reg_operand" "%0")
- (match_operand:DI 2 "int_reg_operand" "r")))]
- ""
- "*
-{
- rtx xoperands[4];
-
- xoperands[0] = operands[0];
- xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- xoperands[2] = operands[2];
- xoperands[3] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
- output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands);
- return \"\";
-}"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r")
- (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r")
- (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))]
- ""
- "*
-{
- if (which_alternative == 2) /* 3 address version */
- {
- if (GET_CODE (operands[2]) == CONST_INT)
- return \"loada %a2(%1),%0\";
- return \"loada [%2](%1),%0\";
- }
- /* 2 address version */
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- int val = INTVAL (operands[2]);
-
- if (val >= 16 || val == 0x80000000)
- return \"addi %2,%0\";
-
- if (val < 0) /* change to sub */
- {
- rtx xops[2];
-
- val = -val;
-
- xops[0] = operands[0];
- xops[1] = GEN_INT (val);
-
- if (val >= 16)
- output_asm_insn (\"subi %1,%0\", xops);
- else
- output_asm_insn (\"subq %1,%0\", xops);
-
- return \"\";
- }
-
- return \"addq %2,%0\";
- }
-
- if (which_alternative == 0)
- return \"addw %2,%0\";
-
- return \"addw %1,%0\";
-}"
-[(set_attr "type" "arith,arith,arith")
- (set_attr "cc" "set1,set1,change0")])
-
-\f
-;;- All kinds of subtract instructions.
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (minus:DI (match_operand:DI 1 "int_reg_operand" "0")
- (match_operand:DI 2 "int_reg_operand" "r")))]
- ""
- "*
-{
- rtx xoperands[4];
-
- xoperands[0] = operands[0];
- xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- xoperands[2] = operands[2];
- xoperands[3] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
- output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands);
- return \"\";
-}"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (minus:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "rn")))]
- ""
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- int val = INTVAL (operands[2]);
-
- if (val < 0 || val >= 16)
- return \"subi %2,%0\";
- else
- return \"subq %2,%0\";
- }
-
- return \"subw %2,%0\";
-}"
-[(set_attr "type" "arith")])
-
-(define_insn "subdf3"
- [(set (match_operand:DF 0 "fp_reg_operand" "=f")
- (minus:DF (match_operand:DF 1 "fp_reg_operand" "0")
- (match_operand:DF 2 "fp_reg_operand" "f")))]
- ""
- "subd %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "subsf3"
- [(set (match_operand:SF 0 "fp_reg_operand" "=f")
- (minus:SF (match_operand:SF 1 "fp_reg_operand" "0")
- (match_operand:SF 2 "fp_reg_operand" "f")))]
- ""
- "subs %2,%0"
- [(set_attr "type" "fp")])
-
-\f
-;;- Multiply instructions.
-
-(define_insn "muldf3"
- [(set (match_operand:DF 0 "fp_reg_operand" "=f")
- (mult:DF (match_operand:DF 1 "fp_reg_operand" "0")
- (match_operand:DF 2 "fp_reg_operand" "f")))]
- ""
- "muld %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "mulsf3"
- [(set (match_operand:SF 0 "fp_reg_operand" "=f")
- (mult:SF (match_operand:SF 1 "fp_reg_operand" "0")
- (match_operand:SF 2 "fp_reg_operand" "f")))]
- ""
- "muls %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "mulsidi3"
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
- (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
- ""
- "mulwx %2,%0"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "umulsidi3"
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
- (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
- ""
- "mulwux %2,%0"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (mult:SI (match_operand:SI 1 "int_reg_operand" "%0")
- (match_operand:SI 2 "int_reg_operand" "r")))]
- ""
- "mulw %2,%0"
- [(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-\f
-;;- Divide and mod instructions.
-
-(define_insn "divdf3"
- [(set (match_operand:DF 0 "fp_reg_operand" "=f")
- (div:DF (match_operand:DF 1 "fp_reg_operand" "0")
- (match_operand:DF 2 "fp_reg_operand" "f")))]
- ""
- "divd %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "divsf3"
- [(set (match_operand:SF 0 "fp_reg_operand" "=f")
- (div:SF (match_operand:SF 1 "fp_reg_operand" "0")
- (match_operand:SF 2 "fp_reg_operand" "f")))]
- ""
- "divs %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "divsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "int_reg_operand" "r")))]
- ""
- "divw %2,%0"
- [(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "udivsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (udiv:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "int_reg_operand" "r")))]
- ""
- "divwu %2,%0"
- [(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-
-(define_insn "modsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (mod:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "int_reg_operand" "r")))]
- ""
- "modw %2,%0"
- [(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "umodsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (umod:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "int_reg_operand" "r")))]
- ""
- "modwu %2,%0"
- [(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-\f
-;;
-;; bit and/or instructions
-;;
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- ""
- "@
- andw %2,%0
- andi %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "iorsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- ""
- "@
- orw %2,%0
- ori %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "xorsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- ""
- "@
- xorw %2,%0
- xori %2,%0"
- [(set_attr "type" "arith")])
-\f
-(define_insn "negdf2"
- [(set (match_operand:DF 0 "fp_reg_operand" "=f")
- (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))]
- ""
- "negd %1,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "negsf2"
- [(set (match_operand:SF 0 "fp_reg_operand" "=f")
- (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
- ""
- "negs %1,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))]
- ""
- "negw %1,%0"
- [(set_attr "type" "arith")])
-
-\f
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (not:SI (match_operand:SI 1 "int_reg_operand" "r")))]
- ""
- "notw %1,%0"
- [(set_attr "type" "arith")])
-
-
-\f
-;; Right shift on the clipper works by negating the shift count,
-;; then emitting a right shift with the shift count negated. This means
-;; that all actual shift counts in the RTL will be positive.
-
-(define_expand "ashrdi3"
- [(set (match_operand:DI 0 "int_reg_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- ""
- "
-{
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))]
- ""
- "shali $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
- ""
- "shal %2,%0"
- [(set_attr "type" "arith")])
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- ""
- "
-{
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))]
- ""
- "shai $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
- ""
- "shaw %2,%0"
- [(set_attr "type" "arith")])
-
-;;
-;; left shift
-;;
-
-(define_insn "ashldi3"
- [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
- (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- ""
- "@
- shal %2,%0
- shali %2,%0"
- [(set_attr "type" "arith")])
-
-
-(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- ""
- "*
-{
- int val;
-
- if (which_alternative == 0)
- return \"shaw %2,%0\";
-
- val = INTVAL (operands[2]);
-
- if (val == 2)
- return \"addw %0,%0\;addw %0,%0\";
-
- if (val == 1)
- return \"addw %0,%0\";
-
- return \"shai %2,%0\";
-}"
-[(set_attr "type" "arith")])
-
-;;
-;; logical shift
-;;
-
-(define_expand "lshrdi3"
- [(set (match_operand:DI 0 "int_reg_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- ""
- "
-{
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))]
- ""
- "shlli $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
- ""
- "shll %2,%0"
- [(set_attr "type" "arith")])
-
-(define_expand "lshrsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- ""
- "
-{
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))]
- ""
- "shli $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
- ""
- "shlw %2,%0"
- [(set_attr "type" "arith")])
-
-
-;;
-;; rotate insn
-;;
-(define_expand "rotrdi3"
- [(set (match_operand:DI 0 "int_reg_operand" "")
- (rotatert:DI (match_operand:DI 1 "int_reg_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- ""
- "
-{
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))]
- ""
- "rotli $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "int_reg_operand" "=r")
- (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
- ""
- "rotl %2,%0"
- [(set_attr "type" "arith")])
-
-(define_expand "rotrsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "")
- (rotatert:SI (match_operand:SI 1 "int_reg_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- ""
- "
-{
- if (GET_CODE (operands[2]) != CONST_INT)
- operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))]
- ""
- "roti $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "int_reg_operand" "=r")
- (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
- ""
- "rotw %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "rotldi3"
- [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
- (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- ""
- "@
- rotl %2,%0
- rotli %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "rotlsi3"
- [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
- (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- ""
- "@
- rotw %2,%0
- roti %2,%0"
- [(set_attr "type" "arith")])
-
-\f
-;;
-;; jump and branch insns
-;;
-(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
- ""
- "b %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "tablejump"
- [(set (pc) (match_operand:SI 0 "register_operand" "r"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
- "b (%0)"
- [(set_attr "type" "branch")])
-
-(define_insn "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "breq %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brne %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brgt %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brgtu %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brlt %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brltu %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brge %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brgeu %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brle %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "brleu %l0"
- [(set_attr "type" "branch")])
-
-;; Recognize reversed jumps.
-(define_insn ""
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(cc0)
- (const_int 0)])
- (pc)
- (label_ref (match_operand 1 "" ""))))]
- ""
- "br%C0 %l1" ; %C0 negates condition
- [(set_attr "type" "branch")])
-\f
-;;
-;; call instructions
-;;
-(define_insn "call"
- [(call (match_operand:QI 0 "general_operand" "m")
- (match_operand:SI 1 "general_operand" ""))]
- ;; Operand 1 not used on the clipper.
- ""
- "call sp,%0")
-
-(define_insn "call_value"
- [(set (match_operand 0 "" "=rf")
- (call (match_operand:QI 1 "general_operand" "m")
- (match_operand:SI 2 "general_operand" "g")))]
- ;; Operand 2 not used on the clipper
- ""
- "call sp,%1")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
- (const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
- ""
- "
-{
- int i;
-
- emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
-
- for (i = 0; i < XVECLEN (operands[2], 0); i++)
- {
- rtx set = XVECEXP (operands[2], 0, i);
- emit_move_insn (SET_DEST (set), SET_SRC (set));
- }
-
- /* The optimizer does not know that the call sets the function value
- registers we stored in the result block. We avoid problems by
- claiming that all hard registers are used and clobbered at this
- point. */
- emit_insn (gen_blockage ());
-
- DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory. This blocks insns from being moved across this point.
-
-(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
- ""
- "")
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
- ""
- "b (%0)"
- [(set_attr "type" "branch")])
-
-
-(define_insn "nop"
- [(const_int 0)]
- ""
- "noop"
- [(set_attr "type" "arith")
- (set_attr "cc" "unchanged")])
-
-\f
-
-;; while (--foo >= 0)
-;;
-;; Combiners for 'decrement test and branch' do not work for clipper.
-;; These patters are jump_insns that do not allow output reloads and clipper
-;; can only decrement and test registers.
-;;
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Clipper/Clix version.
- Copyright (C) 1988, 1993, 1996, 1997, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Dclipper -Dunix -Asystem=unix -Asystem=svr3 -Acpu=clipper -Amachine=clipper"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-#undef LIB_SPEC
-
-#define TARGET_MEM_FUNCTIONS
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-do { \
- const unsigned char *s = (const unsigned char *)(PTR);\
- size_t i, limit = (LEN); \
- for (i = 0; i < limit; s++, i++) \
- { \
- if ((i % 8) == 0) \
- fputs ("\n\t.byte\t", (FILE)); \
- fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
- } \
- fputs ("\n", (FILE)); \
-} while (0)
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- fprintf(FILE, "\t.align %d\n", 1 << (LOG))
-
-
-#define BSS_SECTION_ASM_OP "\t.bss"
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP "\t.section .init,\"x\""
-
-\f
-/* Define a few machine-specific details of the implementation of
- constructors.
-
- The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN
- and CTOR_LIST_END to contribute to the .init section an instruction to
- push a word containing 0 (or some equivalent of that).
-
- TARGET_ASM_CONSTRUCTOR should be defined to push the address of the
- constructor. */
-
-#define CTOR_LIST_BEGIN \
- asm (INIT_SECTION_ASM_OP); \
- asm ("subq $8,sp"); \
- asm ("loadq $0,r0"); \
- asm ("storw r0,(sp)")
-
-/* don't need end marker */
-
-#undef CTOR_LIST_END
-
-/* fini psect is 8 aligned */
-
-#define DTOR_LIST_BEGIN \
- asm (DTORS_SECTION_ASM_OP); \
- func_ptr __DTOR_LIST__[2] = { (func_ptr) (-1), 0 };
-
-#undef TARGET_ASM_CONSTRUCTOR
-#define TARGET_ASM_CONSTRUCTOR clix_asm_out_constructor
-#undef TARGET_ASM_DESTRUCTOR
-#define TARGET_ASM_DESTRUCTOR clix_asm_out_destructor
-
-/* On clix crt1.o first calls init code and then sets environ and a valid
- chrclass. Unfortunately stdio routines bomb with unset chrclass.
- Therefore we set chrclass prior to calling global constructors. */
-
-#undef DO_GLOBAL_CTORS_BODY
-#define DO_GLOBAL_CTORS_BODY \
-do { \
- func_ptr *p, *beg = alloca (0); \
- _setchrclass (0); \
- for (p = beg; *p; p+=2) \
- ; \
- while (p != beg) \
- { p-= 2; (*p) (); } \
-} while (0)
-
-
-#undef DO_GLOBAL_DTORS_BODY
-#define DO_GLOBAL_DTORS_BODY \
- func_ptr *f = &__DTOR_LIST__[2]; /* 0,1 contains -1,0 */ \
- int n = 0; \
- while (*f) \
- { \
- f+= 2; /* skip over alignment 0 */ \
- n++; \
- } \
- f -= 2; \
- while (--n >= 0) \
- { \
- (*f) (); \
- f-= 2; /* skip over alignment 0 */ \
- }
-
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Convex version.
- Copyright (C) 2000 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifdef RTX_CODE
-extern int const_double_low_int PARAMS ((rtx));
-extern int const_double_high_int PARAMS ((rtx));
-extern const char *output_cmp PARAMS ((rtx, rtx, int));
-extern const char *output_condjump PARAMS ((rtx, const char *, int));
-extern const char *output_call PARAMS ((rtx, rtx *));
-extern rtx simplify_for_convex PARAMS ((rtx));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-extern void expand_movstr PARAMS ((rtx *));
-
-extern int nonmemory_operand PARAMS ((rtx, enum machine_mode));
-extern int nonmemory_cmpsf_operand PARAMS ((rtx, enum machine_mode));
-#endif /* RTX_CODE */
-
-#ifdef TREE_CODE
-extern void asm_declare_function_name PARAMS ((FILE *, const char *, tree));
-#endif /* TREE_CODE */
-
-#ifdef REAL_VALUE_TYPE
-extern int check_float_value PARAMS ((enum machine_mode, REAL_VALUE_TYPE *,
- int));
-extern void outfloat PARAMS ((FILE *, REAL_VALUE_TYPE, const char *,
- const char *, const char *));
-#endif /* REAL_VALUE_TYPE */
-
-extern void psw_disable_float PARAMS ((void));
-extern void init_convex PARAMS ((void));
-extern void replace_arg_pushes PARAMS ((void));
-extern void emit_ap_optimizations PARAMS ((void));
+++ /dev/null
-/* Subroutines for insn-output.c for Convex.
- Copyright (C) 1988, 1993, 1994, 1997, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "config.h"
-#include "system.h"
-#include "tree.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-attr.h"
-#include "output.h"
-#include "function.h"
-#include "expr.h"
-#include "tm_p.h"
-#include "target.h"
-#include "target-def.h"
-
-/* Tables used in convex.h */
-
-char regno_ok_for_index_p_base[1 + LAST_VIRTUAL_REGISTER + 1];
-enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
-enum reg_class reg_class_from_letter[256];
-
-/* Target cpu index. */
-
-int target_cpu;
-
-/* Boolean to keep track of whether the current section is .text or not.
- Used by .align handler in convex.h. */
-
-int current_section_is_text;
-
-/* Communication between output_compare and output_condjump. */
-
-static rtx cmp_operand0, cmp_operand1;
-static char cmp_modech;
-
-/* Forwards */
-
-#if 0
-static rtx frame_argblock;
-static int frame_argblock_size;
-static rtx convert_arg_pushes ();
-#endif
-static void expand_movstr_call PARAMS ((rtx *));
-static void convex_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void convex_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static int convex_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_BYTE_OP
-#define TARGET_ASM_BYTE_OP "\tds.b\t"
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\tds.h\t"
-#undef TARGET_ASM_ALIGNED_SI_OP
-#define TARGET_ASM_ALIGNED_SI_OP "\tds.w\t"
-
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE convex_output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE convex_output_function_epilogue
-#undef TARGET_SCHED_ADJUST_COST
-#define TARGET_SCHED_ADJUST_COST convex_adjust_cost
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* Generate the assembly code for function entry. FILE is a stdio
- stream to output the code to. SIZE is an int: how many units of
- temporary storage to allocate.
-
- Refer to the array `regs_ever_live' to determine which registers to
- save; `regs_ever_live[I]' is nonzero if register number I is ever
- used in the function. This function is responsible for knowing
- which registers should not be saved even if used. */
-
-static void
-convex_output_function_prologue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- size = ((size) + 7) & -8;
- if (size)
- {
- fprintf (file, "\tsub.w #");
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
- fprintf (file, ",sp\n");
- }
-}
-
-/* This function generates the assembly code for function exit.
- Args are as for output_function_prologue ().
-
- The function epilogue should not depend on the current stack
- pointer! It should use the frame pointer only. This is mandatory
- because of alloca; we also take advantage of it to omit stack
- adjustments before returning. */
-
-static void
-convex_output_function_epilogue (file, size)
- FILE *file;
- HOST_WIDE_INT size ATTRIBUTE_UNUSED;
-{
- /* Follow function with a zero to stop c34 icache prefetching. */
- fprintf (file, "\tds.h 0\n");
-}
-
-/* Adjust the cost of dependences. */
-static int
-convex_adjust_cost (insn, link, dep, cost)
- rtx insn;
- rtx link;
- rtx dep;
- int cost;
-{
- /* Antidependencies don't block issue. */
- if (REG_NOTE_KIND (link) != 0)
- cost = 0;
- /* C38 situations where delay depends on context */
- else if (TARGET_C38
- && GET_CODE (PATTERN (insn)) == SET
- && GET_CODE (PATTERN (dep)) == SET)
- {
- enum attr_type insn_type = get_attr_type (insn);
- enum attr_type dep_type = get_attr_type (dep);
- /* index register must be ready one cycle early */
- if (insn_type == TYPE_MLDW || insn_type == TYPE_MLDL
- || (insn_type == TYPE_MST
- && reg_mentioned_p (SET_DEST (PATTERN (dep)),
- SET_SRC (PATTERN (insn)))))
- cost += 1;
- /* alu forwarding off alu takes two */
- if (dep_type == TYPE_ALU
- && insn_type != TYPE_ALU
- && ! (insn_type == TYPE_MST
- && SET_DEST (PATTERN (dep)) == SET_SRC (PATTERN (insn))))
- cost += 1;
- }
-
- return cost;
-}
-
-
-
-/* Here from OVERRIDE_OPTIONS at startup. Initialize constant tables. */
-
-void
-init_convex ()
-{
- int regno;
-
- /* Set A and S reg classes. */
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
- if (A_REGNO_P (regno))
- {
- regno_ok_for_index_p[regno] = 1;
- regno_reg_class[regno] = INDEX_REGS;
- }
- else
- {
- regno_ok_for_index_p[regno] = 0;
- regno_reg_class[regno] = S_REGS;
- }
-
- /* Can't index off the stack pointer, register 0. */
- regno_ok_for_index_p[STACK_POINTER_REGNUM] = 0;
- regno_reg_class[STACK_POINTER_REGNUM] = SP_REGS;
-
- /* Can't index off aliases of the stack pointer. */
- regno_ok_for_index_p[VIRTUAL_INCOMING_ARGS_REGNUM] = 1;
- regno_ok_for_index_p[VIRTUAL_STACK_VARS_REGNUM] = 1;
- regno_ok_for_index_p[VIRTUAL_STACK_DYNAMIC_REGNUM] = 0;
- regno_ok_for_index_p[VIRTUAL_OUTGOING_ARGS_REGNUM] = 0;
-
- /* Can't index off hard reg -1 == pseudos not assigned */
- regno_ok_for_index_p[-1] = 0;
-
- /* Set reg class letters */
- reg_class_from_letter['a'] = A_REGS;
- reg_class_from_letter['A'] = INDEX_REGS;
- reg_class_from_letter['d'] = S_REGS;
-
- /* Turn off floating point exception enables in the psw. */
- psw_disable_float ();
-}
-
-void
-psw_disable_float ()
-{
-#if __convex__ && __GNUC__
- register int *p;
- asm ("mov fp,%0" : "=a" (p));
- while (p)
- {
- p[1] &= ~0x1000c400;
- p = (int *) p[2];
- }
-#endif
-}
-\f
-/* Here to output code for a compare insn. Output nothing, just
- record the operands and their mode. */
-
-const char *
-output_cmp (operand0, operand1, modech)
- rtx operand0, operand1;
- int modech;
-{
- cmp_operand0 = operand0;
- cmp_operand1 = operand1;
- cmp_modech = modech;
- return "";
-}
-
-/* Output code for a conditional jump. The preceding instruction
- is necessarily a compare. Output two instructions, for example
- eq.w a1,a2
- jbra.t L5
- for
- (cmpsi a1 a2)
- (beq L5)
- */
-
-const char *
-output_condjump (label, cond, jbr_sense)
- rtx label;
- const char *cond;
- int jbr_sense;
-{
- rtx operands[3];
- char cmp_op[4];
- char buf[80];
- char jbr_regch;
-
- strcpy (cmp_op, cond);
-
- /* [BL] mean the value is being compared against immediate 0.
- Use neg.x, which produces the same carry that eq.x #0 would if it
- existed. In this case operands[1] is a scratch register, not a
- compare operand. */
-
- if (cmp_modech == 'B' || cmp_modech == 'L')
- {
- cmp_modech = cmp_modech - 'A' + 'a';
- strcpy (cmp_op, "neg");
- }
-
- /* [WH] mean the value being compared resulted from "add.[wh] #-1,rk"
- when rk was nonnegative -- we can omit equality compares against -1
- or inequality compares against 0. */
-
- else if (cmp_modech == 'W' || cmp_modech == 'H')
- {
- if (! strcmp (cmp_op, "eq") && cmp_operand1 == constm1_rtx)
- jbr_sense ^= 't' ^ 'f';
- else if (! strcmp (cmp_op, "lt") && cmp_operand1 == const0_rtx)
- ;
- else
- cmp_modech = cmp_modech - 'A' + 'a';
- }
-
- /* Constant must be first; swap operands if necessary.
- If lt, le, ltu, leu are swapped, change to le, lt, leu, ltu
- and reverse the sense of the jump. */
-
- if (! REG_P (cmp_operand1))
- {
- operands[0] = cmp_operand1;
- operands[1] = cmp_operand0;
- if (cmp_op[0] == 'l')
- {
- cmp_op[1] ^= 'e' ^ 't';
- jbr_sense ^= 't' ^ 'f';
- }
- }
- else
- {
- operands[0] = cmp_operand0;
- operands[1] = cmp_operand1;
- }
-
- operands[2] = label;
-
- if (S_REG_P (operands[1]))
- jbr_regch = 's';
- else if (A_REG_P (operands[1]))
- jbr_regch = 'a';
- else
- abort ();
-
- if (cmp_modech == 'W' || cmp_modech == 'H')
- sprintf (buf, "jbr%c.%c %%l2", jbr_regch, jbr_sense);
- else
- sprintf (buf, "%s.%c %%0,%%1\n\tjbr%c.%c %%l2",
- cmp_op, cmp_modech, jbr_regch, jbr_sense);
- output_asm_insn (buf, operands);
- return "";
-}
-
-/* Return 1 if OP is valid for cmpsf.
- In IEEE mode, +/- zero compares are not handled by
- the immediate versions of eq.s and on some machines, lt.s, and le.s.
- So disallow 0.0 as the immediate operand of xx.s compares in IEEE mode. */
-
-int
-nonmemory_cmpsf_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
-#if _IEEE_FLOAT_
- if (op == CONST0_RTX (SFmode))
- return 0;
-#endif
-
- return nonmemory_operand (op, mode);
-}
-\f
-/* Convex /bin/as does not like unary minus in some contexts.
- Simplify CONST addresses to remove it. */
-
-rtx
-simplify_for_convex (x)
- rtx x;
-{
- switch (GET_CODE (x))
- {
- case MINUS:
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
- && INTVAL (XEXP (x, 1)) < 0)
- {
- PUT_CODE (x, PLUS);
- XEXP (x, 1) = GEN_INT (- INTVAL (XEXP (x, 1)));
- }
- break;
-
- case CONST:
- return simplify_for_convex (XEXP (x, 0));
- default:
- break;
- }
-
- return x;
-}
-\f
-/* Routines to separate CONST_DOUBLEs into component parts. */
-
-int
-const_double_high_int (x)
- rtx x;
-{
- if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
- return CONST_DOUBLE_LOW (x);
- else
- return CONST_DOUBLE_HIGH (x);
-}
-
-int
-const_double_low_int (x)
- rtx x;
-{
- if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
- return CONST_DOUBLE_HIGH (x);
- else
- return CONST_DOUBLE_LOW (x);
-}
-\f
-/* Inline block copy. */
-
-void
-expand_movstr (operands)
- rtx *operands;
-{
- rtx dest = operands[0];
- rtx src = operands[1];
- int align = INTVAL (operands[3]);
- int nregs, maxsize;
- unsigned len;
- enum machine_mode mode;
- rtx reg, load, store, prev_store, prev_store_2;
- int size;
-
- /* Decide how many regs to use, depending on load latency, and what
- size pieces to move, depending on whether machine does unaligned
- loads and stores efficiently. */
-
- if (TARGET_C1)
- {
- /* ld.l latency is 4, no alignment problems. */
- nregs = 3, maxsize = 8;
- }
- else if (TARGET_C2)
- {
- /* loads are latency 2 if we avoid ld.l not at least word aligned. */
- if (align >= 4)
- nregs = 2, maxsize = 8;
- else
- nregs = 2, maxsize = 4;
- }
- else if (TARGET_C34)
- {
- /* latency is 4 if aligned, horrible if not. */
- nregs = 3, maxsize = align;
- }
- else if (TARGET_C38)
- {
- /* latency is 2 if at least word aligned, 3 or 4 if unaligned. */
- if (align >= 4)
- nregs = 2, maxsize = 8;
- else
- nregs = 3, maxsize = 8;
- }
- else
- abort ();
-
- /* Caller is not necessarily prepared for us to fail in this
- expansion. So fall back by generating memcpy call here. */
-
- if (GET_CODE (operands[2]) != CONST_INT
- || (len = INTVAL (operands[2])) > (unsigned) 32 * maxsize)
- {
- expand_movstr_call (operands);
- return;
- }
-
- reg = 0;
- prev_store = prev_store_2 = 0;
-
- while (len > 0)
- {
- if (len >= 8 && maxsize >= 8)
- mode = DImode;
- else if (len >= 4 && maxsize >= 4)
- mode = SImode;
- else if (len >= 2 && maxsize >= 2)
- mode = HImode;
- else
- mode = QImode;
-
- /* If no temp pseudo to reuse, or not the right mode, make one */
- if (! reg || GET_MODE (reg) != mode)
- reg = gen_reg_rtx (mode);
-
- /* Get src and dest in the right mode */
- if (GET_MODE (src) != mode)
- {
- src = adjust_address (src, mode, 0);
- dest = adjust_address (dest, mode, 0);
- }
-
- /* Make load and store patterns for this piece */
- load = gen_rtx_SET (VOIDmode, reg, src);
- store = gen_rtx_SET (VOIDmode, dest, reg);
-
- /* Emit the load and the store from last time.
- When we emit a store, we can reuse its temp reg. */
- emit_insn (load);
- if (prev_store)
- {
- reg = SET_SRC (prev_store);
- emit_insn (prev_store);
- }
- else
- reg = 0;
-
- /* Queue up the store, for next time or the time after that. */
- if (nregs == 2)
- prev_store = store;
- else
- prev_store = prev_store_2, prev_store_2 = store;
-
- /* Advance to next piece. */
- size = GET_MODE_SIZE (mode);
- src = adjust_address (src, mode, size);
- dest = adjust_address (dest, mode, size);
- len -= size;
- }
-
- /* Finally, emit the last stores. */
- if (prev_store)
- emit_insn (prev_store);
- if (prev_store_2)
- emit_insn (prev_store_2);
-}
-
-static void
-expand_movstr_call (operands)
- rtx *operands;
-{
- emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
- VOIDmode, 3,
- XEXP (operands[0], 0), Pmode,
- XEXP (operands[1], 0), Pmode,
- convert_to_mode (TYPE_MODE (sizetype), operands[2],
- TREE_UNSIGNED (sizetype)),
- TYPE_MODE (sizetype));
-}
-\f
-#if TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT
-#define MAX_FLOAT "3.4028234663852886e+38"
-#define MIN_FLOAT "1.1754943508222875e-38"
-#else
-#define MAX_FLOAT "1.7014117331926443e+38"
-#define MIN_FLOAT "2.9387358770557188e-39"
-#endif
-
-int
-check_float_value (mode, dp, overflow)
- enum machine_mode mode;
- REAL_VALUE_TYPE *dp;
- int overflow;
-{
- REAL_VALUE_TYPE d = *dp;
- REAL_VALUE_TYPE maxfloat = REAL_VALUE_ATOF (MAX_FLOAT, mode);
- REAL_VALUE_TYPE minfloat = REAL_VALUE_ATOF (MIN_FLOAT, mode);
- REAL_VALUE_TYPE neg_maxfloat = REAL_VALUE_NEGATE (maxfloat);
- REAL_VALUE_TYPE neg_minfloat = REAL_VALUE_NEGATE (minfloat);
-
- if (overflow)
- {
- *dp = maxfloat;
- return 1;
- }
-
- if (mode == SFmode)
- {
- if (REAL_VALUES_LESS (maxfloat, d))
- {
- *dp = maxfloat;
- return 1;
- }
- else if (REAL_VALUES_LESS (d, neg_maxfloat))
- {
- *dp = neg_maxfloat;
- return 1;
- }
- else if ((REAL_VALUES_LESS (dconst0, d)
- && REAL_VALUES_LESS (d, minfloat))
- || (REAL_VALUES_LESS (d, dconst0)
- && REAL_VALUES_LESS (neg_minfloat, d)))
- {
- *dp = dconst0;
- return 1;
- }
- }
-
- return 0;
-}
-\f
-/* Output the label at the start of a function.
- Precede it with the number of formal args so debuggers will have
- some idea of how many args to print. */
-
-void
-asm_declare_function_name (file, name, decl)
- FILE *file;
- const char *name;
- tree decl;
-{
- int nargs = list_length (DECL_ARGUMENTS (decl));
-
- const char *p;
- char c;
- static char vers[4];
- int i;
-
- p = version_string;
- for (i = 0; i < 3; ) {
- c = *p;
- if (ISDIGIT (c))
- vers[i++] = c;
- if (c == 0 || c == ' ')
- vers[i++] = '0';
- else
- p++;
- }
- fprintf (file, "\tds.b \"g%s\"\n", vers);
-
- if (nargs < 100)
- fprintf (file, "\tds.b \"+%02d\\0\"\n", nargs);
- else
- fprintf (file, "\tds.b \"+00\\0\"\n");
-
- ASM_OUTPUT_LABEL (file, name);
-}
-\f
-/* Print an instruction operand X on file FILE.
- CODE is the code from the %-spec that requested printing this operand;
- if `%z3' was used to print operand 3, then CODE is 'z'. */
-/* Convex codes:
- %u prints a CONST_DOUBLE's high word
- %v prints a CONST_DOUBLE's low word
- %z prints a CONST_INT shift count as a multiply operand -- viz. 1 << n.
- */
-
-void
-print_operand (file, x, code)
- FILE *file;
- rtx x;
- int code;
-{
- long u[2];
- REAL_VALUE_TYPE d;
-
- switch (GET_CODE (x))
- {
- case REG:
- fprintf (file, "%s", reg_names[REGNO (x)]);
- break;
-
- case MEM:
- output_address (XEXP (x, 0));
- break;
-
- case CONST_DOUBLE:
- REAL_VALUE_FROM_CONST_DOUBLE (d, x);
- switch (GET_MODE (x)) {
- case DFmode:
- REAL_VALUE_TO_TARGET_DOUBLE (d, u);
- if (code == 'u')
- fprintf (file, "#%#lx", u[0]);
- else if (code == 'v')
- fprintf (file, "#%#lx", u[1]);
- else
- outfloat (file, d, "%.17e", "#", "");
- break;
- case SFmode:
- outfloat (file, d, "%.9e", "#", "");
- break;
- default:
- if (code == 'u')
- {
- fprintf (file, "#");
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_HIGH (x));
- }
- else
- {
- fprintf (file, "#");
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
- }
- }
- break;
-
- default:
- if (code == 'z')
- {
- if (GET_CODE (x) != CONST_INT)
- abort ();
- fprintf (file, "#%d", 1 << INTVAL (x));
- }
- else
- {
- putc ('#', file);
- output_addr_const (file, x);
- }
- }
-}
-
-/* Print a memory operand whose address is X, on file FILE. */
-
-void
-print_operand_address (file, addr)
- FILE *file;
- rtx addr;
-{
- rtx index = 0;
- rtx offset = 0;
-
- if (GET_CODE (addr) == MEM)
- {
- fprintf (file, "@");
- addr = XEXP (addr, 0);
- }
-
- switch (GET_CODE (addr))
- {
- case REG:
- index = addr;
- break;
-
- case PLUS:
- index = XEXP (addr, 0);
- if (REG_P (index))
- offset = XEXP (addr, 1);
- else
- {
- offset = XEXP (addr, 0);
- index = XEXP (addr, 1);
- if (! REG_P (index))
- abort ();
- }
- break;
-
- default:
- offset = addr;
- break;
- }
-
- if (offset)
- output_addr_const (file, offset);
-
- if (index)
- fprintf (file, "(%s)", reg_names[REGNO (index)]);
-}
-
-/* Output a float to FILE, value VALUE, format FMT, preceded by PFX
- and followed by SFX. */
-
-void
-outfloat (file, value, fmt, pfx, sfx)
- FILE *file;
- REAL_VALUE_TYPE value;
- const char *fmt, *pfx, *sfx;
-{
- char buf[64];
- fputs (pfx, file);
- REAL_VALUE_TO_DECIMAL (value, fmt, buf);
- fputs (buf, file);
- fputs (sfx, file);
-}
-\f
-/* Here during RTL generation of return. If we are at the final return
- in a function, go through the function and replace pushes with stores
- into a frame arg block. This is similar to what ACCUMULATE_OUTGOING_ARGS
- does, but we must index off the frame pointer, not the stack pointer,
- and the calling sequence does not require the arg block to be at the
- top of the stack. */
-
-void
-replace_arg_pushes ()
-{
- /* Doesn't work yet. */
-}
-
-/* Output the insns needed to do a call. operands[] are
- 0 - MEM, the place to call
- 1 - CONST_INT, the number of bytes in the arg list
- 2 - CONST_INT, the number of arguments
- 3 - CONST_INT, the number of bytes to pop
- 4 - address of the arg list.
- */
-
-const char *
-output_call (insn, operands)
- rtx insn ATTRIBUTE_UNUSED, *operands;
-{
- if (operands[4] == stack_pointer_rtx)
- output_asm_insn ("mov sp,ap", operands);
- else
- abort ();
-
- if (TARGET_ARGCOUNT)
- output_asm_insn ("pshea %a2", operands);
-
- output_asm_insn ("calls %0", operands);
-
- output_asm_insn ("ld.w 12(fp),ap", operands);
-
- if (operands[4] == stack_pointer_rtx && operands[3] != const0_rtx)
- output_asm_insn ("add.w %3,sp", operands);
-
- return "";
-}
-
-
-/* Here after reloading, before the second scheduling pass. */
-
-void
-emit_ap_optimizations ()
-{
- /* Removed for now. */
-}
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Convex version.
- Copyright (C) 1988, 1994, 1995, 1996, 2000, 2001, 2002
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Standard GCC variables that we reference. */
-
-extern int target_flags;
-
-/* Convex machine-specific flags
- -mc1 target instruction set, libraries, scheduling
- -mc2
- -mc32
- -mc34
- -mc38
- -margcount use standard calling sequence, with arg count word
- -mno-argcount don't push arg count, depend on symbol table
- -margcount-nop place arg count in a nop instruction (faster than push)
- -mvolatile-cache use data cache for volatile mem refs (default)
- -mvolatile-nocache bypass data cache for volatile mem refs
- -mlong32 cc- and libc-compatible 32-bit longs
- -mlong64 64-bit longs
-*/
-
-/* Macro to define tables used to set -mXXX flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-#define TARGET_SWITCHES \
- { { "c1", 001, N_("Generate code for c1") }, \
- { "c2", 002, N_("Generate code for c2") }, \
- { "c32", 004, N_("Generate code for c32") }, \
- { "c34", 010, N_("Generate code for c34") }, \
- { "c38", 020, N_("Generate code for c34") }, \
- { "argcount", 0100, \
- N_("Use standard calling sequence, with arg count word")}, \
- { "argcount-nop", 0200, \
- N_("Place arg count in a nop instruction (faster than push)") }, \
- { "no-argcount", -0300, \
- N_("Don't push arg count, depend on symbol table") }, \
- { "volatile-cache", -0400, \
- N_("Use data cache for volatile mem refs (default)") }, \
- { "no-volatile-cache", 0400, \
- N_("Don't use data cache for volatile mem refs") }, \
- { "volatile-nocache", 0400, \
- N_("Bypass data cache for volatile mem refs") }, \
- { "long64", 01000, N_("Use 64-bit longs") }, \
- { "long32", -01000, N_("Use cc- and libc-compatible 32-bit longs")},\
- { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
-
-/* Macros used in the machine description to test the flags. */
-
-#define TARGET_C1 (target_cpu == 0)
-#define TARGET_C2 (target_cpu == 1)
-#define TARGET_C34 (target_cpu == 2)
-#define TARGET_C38 (target_cpu == 3)
-#define TARGET_ARGCOUNT (target_flags & 0100)
-#define TARGET_ARGCOUNT_NOP (target_flags & 0200)
-#define TARGET_LONG64 (target_flags & 01000)
-#define TARGET_VOLATILE_NOCACHE (target_flags & 0400)
-
-#define OVERRIDE_OPTIONS \
-{ \
- init_convex (); \
- if ((target_flags & 077) != ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 077)) \
- target_flags &= ~ (TARGET_DEFAULT | TARGET_CPU_DEFAULT); \
- if (target_flags & 001) \
- target_cpu = 0; \
- else if (target_flags & 006) \
- target_cpu = 1; \
- else if (target_flags & 010) \
- target_cpu = 2; \
- else if (target_flags & 020) \
- target_cpu = 3; \
-}
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Dconvex -Dunix -Asystem=unix -Acpu=convex -Amachine=convex"
-
-/* Print subsidiary information on the compiler version in use. */
-
-#define TARGET_VERSION fprintf (stderr, " (convex)");
-
-/* Target-dependent specs.
- Some libraries come in c1 and c2+ versions; use the appropriate ones.
- Make a target-dependent __convex_cxx__ define to relay the target cpu
- to the program being compiled. */
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1
-
-/* C1 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC \
-"%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \
- %{mc2:-D__convex_c2__} \
- %{mc32:-D__convex_c32__} \
- %{mc34:-D__convex_c34__} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_IEEE_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC \
-"%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \
- %{mc2:-D__convex_c2__} \
- %{mc32:-D__convex_c32__} \
- %{mc34:-D__convex_c34__} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_CONVEX_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC \
-"%{!mc2:%{!mc32:%{!mc34:%{!mc38:-lC1%{p:_p}%{pg:_p}}}}} \
- %{mc2:-lC2%{p:_p}%{pg:_p}} \
- %{mc32:-lC2%{p:_p}%{pg:_p}} \
- %{mc34:-lC2%{p:_p}%{pg:_p}} \
- %{mc38:-lC2%{p:_p}%{pg:_p}} \
- -lc%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 2
-
-/* C2 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \
- %{mc32:-D__convex_c32__} \
- %{mc34:-D__convex_c34__} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_IEEE_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \
- %{mc32:-D__convex_c32__} \
- %{mc34:-D__convex_c34__} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_CONVEX_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC \
-"%{mc1:-lC1%{p:_p}%{pg:_p}} \
- %{!mc1:%{!mc32:%{!mc34:%{!mc38:-lC2%{p:_p}%{pg:_p}}}}} \
- %{mc32:-lC2%{p:_p}%{pg:_p}} \
- %{mc34:-lC2%{p:_p}%{pg:_p}} \
- %{mc38:-lC2%{p:_p}%{pg:_p}} \
- -lc%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 4
-
-/* C32 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{mc2:-D__convex_c2__} \
- %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \
- %{mc34:-D__convex_c34__} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_IEEE_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{mc2:-D__convex_c2__} \
- %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \
- %{mc34:-D__convex_c34__} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_CONVEX_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC \
-"%{mc1:-lC1%{p:_p}%{pg:_p}} \
- %{mc2:-lC2%{p:_p}%{pg:_p}} \
- %{!mc1:%{!mc2:%{!mc34:%{!mc38:-lC2%{p:_p}%{pg:_p}}}}} \
- %{mc34:-lC2%{p:_p}%{pg:_p}} \
- %{mc38:-lC2%{p:_p}%{pg:_p}} \
- -lc%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 010
-
-/* C34 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{mc2:-D__convex_c2__} \
- %{mc32:-D__convex_c32__} \
- %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_IEEE_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{mc2:-D__convex_c2__} \
- %{mc32:-D__convex_c32__} \
- %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \
- %{mc38:-D__convex_c38__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_CONVEX_FLOAT_ \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC \
-"%{mc1:-lC1%{p:_p}%{pg:_p}} \
- %{mc2:-lC2%{p:_p}%{pg:_p}} \
- %{mc32:-lC2%{p:_p}%{pg:_p}} \
- %{!mc1:%{!mc2:%{!mc32:%{!mc38:-lC2%{p:_p}%{pg:_p}}}}} \
- %{mc38:-lC2%{p:_p}%{pg:_p}} \
- -lc%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 020
-
-/* C38 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{mc2:-D__convex_c2__} \
- %{mc32:-D__convex_c32__} \
- %{mc34:-D__convex_c34__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_IEEE_FLOAT_ \
- %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC \
-"%{mc1:-D__convex_c1__} \
- %{mc2:-D__convex_c2__} \
- %{mc32:-D__convex_c32__} \
- %{mc34:-D__convex_c34__} \
- %{fno-builtin:-D__NO_INLINE} \
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
- -D_CONVEX_FLOAT_ \
- %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \
- %{.S:-P} \
- -D__stdc__ -D_LONGLONG \
- -Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long \
- %{!ansi:-D_POSIX_SOURCE} \
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC \
-"%{mc1:-lC1%{p:_p}%{pg:_p}} \
- %{mc2:-lC2%{p:_p}%{pg:_p}} \
- %{mc32:-lC2%{p:_p}%{pg:_p}} \
- %{mc34:-lC2%{p:_p}%{pg:_p}} \
- %{!mc1:%{!mc2:%{!mc32:%{!mc34:-lC2%{p:_p}%{pg:_p}}}}} \
- -lc%{p:_p}%{pg:_p}"
-
-#endif
-
-#if _IEEE_FLOAT_
-
-/* ieee default */
-
-#define ASM_SPEC "-fi"
-
-#define LINK_SPEC \
-"-Eposix \
- -X \
- %{F} %{M*} %{y*} \
- -fi \
- -A__iob=___ap$iob \
- -A_use_libc_sema=___ap$use_libc_sema \
- %-A___gcc_cleanup=___ap$do_registered_functions \
- -L/usr/lib"
-
-#define STARTFILE_SPEC \
-"%{!pg:%{!p:/usr/lib/crt/crt0.o}} \
- %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \
- %{pg:/usr/lib/crt/gcrt0.o} \
- /usr/lib/crt/fpmode_i.o"
-
-#else
-
-/* native default */
-
-#define ASM_SPEC "-fn"
-
-#define LINK_SPEC \
-"-Eposix \
- -X \
- %{F} %{M*} %{y*} \
- -fn \
- -A__iob=___ap$iob \
- -A_use_libc_sema=___ap$use_libc_sema \
- -A___gcc_cleanup=___ap$do_registered_functions \
- -L/usr/lib"
-
-#define STARTFILE_SPEC \
-"%{!pg:%{!p:/usr/lib/crt/crt0.o}} \
- %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \
- %{pg:/usr/lib/crt/gcrt0.o}"
-
-#endif
-
-/* Use /path/libgcc.a instead of -lgcc, makes bootstrap work more smoothly. */
-
-#define LINK_LIBGCC_SPECIAL_1
-
-\f
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields. */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is numbered. */
-#define WORDS_BIG_ENDIAN 1
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 8
-
-/* Width in bits of a pointer.
- See also the macro `Pmode' defined below. */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#define STACK_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this. */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct. */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this. */
-/* beware of doubles in structs -- 64 is incompatible with cc */
-#define BIGGEST_ALIGNMENT 32
-
-/* Set this nonzero if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 0
-
-/* Define sizes of basic C types to conform to ordinary usage -- these
- types depend on BITS_PER_WORD otherwise. */
-#define SHORT_TYPE_SIZE 16
-#define INT_TYPE_SIZE 32
-#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
-#define LONG_LONG_TYPE_SIZE 64
-#define FLOAT_TYPE_SIZE 32
-#define DOUBLE_TYPE_SIZE 64
-#define LONG_DOUBLE_TYPE_SIZE 64
-#define MAX_LONG_TYPE_SIZE 64
-
-/* Declare the standard types used by builtins to match convex stddef.h --
- with int rather than long. */
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-\f
-/* Standard register usage. */
-
-/* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
- For Convex, these are AP, FP, and SP. */
-#define FIXED_REGISTERS \
- { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 }
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like. */
-#define CALL_USED_REGISTERS \
- { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* List the order in which to allocate registers. Each register must be
- listed once, even those in FIXED_REGISTERS.
- For Convex, put S0 (the return register) last. */
-#define REG_ALLOC_ORDER \
- { 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 0, 8, 14, 15 }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- On Convex, S registers can hold any type, A registers any nonfloat. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (S_REGNO_P (REGNO) \
- || (GET_MODE_SIZE (MODE) <= 4 && (MODE) != SFmode))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
- ((GET_MODE_SIZE (MODE1) <= 4 && (MODE1) != SFmode) \
- == (GET_MODE_SIZE (MODE2) <= 4 && (MODE2) != SFmode))
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-#define S0_REGNUM 0
-#define A0_REGNUM 8
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM A0_REGNUM
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM (A0_REGNUM + 7)
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM (A0_REGNUM + 6)
-
-/* Register in which static-chain is passed to a function.
- Use S0, not an A reg, because this rare use would otherwise prevent
- an A reg from being available to global-alloc across calls. */
-#define STATIC_CHAIN_REGNUM S0_REGNUM
-
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM (A0_REGNUM + 1)
-\f
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
-/* Convex has classes A (address) and S (scalar).
- A is further divided into SP_REGS (stack pointer) and INDEX_REGS.
- SI_REGS is S_REGS + INDEX_REGS -- all the regs except SP. */
-
-enum reg_class {
- NO_REGS, S_REGS, INDEX_REGS, SP_REGS, A_REGS, SI_REGS,
- ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Since GENERAL_REGS is the same class as ALL_REGS,
- don't give it a different class number; just make it an alias. */
-
-#define GENERAL_REGS ALL_REGS
-
-/* Give names of register classes as strings for dump file. */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "S_REGS", "INDEX_REGS", "SP_REGS", "A_REGS", "SI_REGS", \
- "ALL_REGS" }
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. */
-
-#define REG_CLASS_CONTENTS \
- { {0}, {0x00ff}, {0xfe00}, {0x0100}, {0xff00}, {0xfeff}, {0xffff} }
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-#define REGNO_REG_CLASS(REGNO) (regno_reg_class[REGNO])
-
-#define S_REGNO_P(REGNO) ((unsigned)((REGNO) - S0_REGNUM) < 8)
-#define A_REGNO_P(REGNO) ((unsigned)((REGNO) - A0_REGNUM) < 8)
-
-#define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
-#define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
-
-/* The class value for index registers, and the one for base regs. */
-
-#define INDEX_REG_CLASS INDEX_REGS
-#define BASE_REG_CLASS INDEX_REGS
-
-/* Get reg_class from a letter such as appears in the machine description. */
-/* a => A_REGS
- d => S_REGS ('s' is taken)
- A => INDEX_REGS (i.e., A_REGS except sp) */
-
-#define REG_CLASS_FROM_LETTER(C) \
- reg_class_from_letter[(unsigned char) (C)]
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C. */
-/* 'I' is used to pass any CONST_INT and reject any CONST_DOUBLE.
- CONST_DOUBLE integers are handled by G and H constraint chars. */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) 1
-
-/* Similar, but for floating constants, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself. */
-/* Convex uses G, H:
- value usable in ld.d (low word 0) or ld.l (high word all sign) */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- (((C) == 'G' && LD_D_P (VALUE)) || \
- ((C) == 'H' && LD_L_P (VALUE)) || \
- 0)
-
-#define LD_D_P(X) (const_double_low_int (X) == 0)
-
-#define LD_L_P(X) (const_double_low_int (X) >= 0 \
- ? const_double_high_int (X) == 0 \
- : const_double_high_int (X) == -1)
-
-/* Optional extra constraints for this machine.
- For Convex, 'Q' means that OP is a volatile MEM.
- For volatile scalars, we use instructions that bypass the data cache. */
-
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'Q' ? (GET_CODE (OP) == MEM && MEM_VOLATILE_P (OP) \
- && ! TARGET_C1 && TARGET_VOLATILE_NOCACHE) \
- : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-
-/* Put 2-word constants that can't be immediate operands into memory. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
- ((GET_CODE (X) != CONST_DOUBLE \
- || GET_MODE (X) == SFmode \
- || LD_L_P (X) || LD_D_P (X)) ? (CLASS) : NO_REGS)
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS. */
-#define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) + 7) / 8)
-\f
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- that is, each additional local variable allocated
- goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
-
-/* Define this if should default to -fcaller-saves. */
-#define DEFAULT_CALLER_SAVES
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated. */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by. */
-#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
-
-/* Offset of first parameter from the argument pointer register value. */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
- popped when returning from a subroutine call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
- SIZE is the number of bytes of arguments passed on the stack. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx (REG, TYPE_MODE (VALTYPE), S0_REGNUM)
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, S0_REGNUM)
-
-/* Define this if PCC uses the nonreentrant convention for returning
- structure and union values. */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for a function value.
- On the Convex, S0 is the only register thus used. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == S0_REGNUM)
-
-/* 1 if N is a possible register number for function argument passing. */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-\f
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go. */
-/* On convex, simply count the arguments in case TARGET_ARGCOUNT is set. */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0. */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.) */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- ((CUM) += 1)
-
-/* Define where to put the arguments to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis).
-
- Convex: all args go on the stack. But return the arg count
- as the "next arg register" to be passed to gen_call. */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
- ((MODE) == VOIDmode ? GEN_INT ((CUM)) : 0)
-
-/* Output assembler code for a block containing the constant parts
- of a trampoline, leaving space for the variable parts. */
-
-/* On convex, the code for a trampoline is
- ld.w #<link>,s0
- jmp <func> */
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
-{ \
- fprintf (FILE, "\tld.w #69696969,s0\n"); \
- fprintf (FILE, "\tjmp 52525252\n"); \
-}
-
-/* Length in units of the trampoline for entering a nested function. */
-
-#define TRAMPOLINE_SIZE 12
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 2)), CXT); \
- emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 8)), FNADDR); \
- emit_call_insn (gen_call_pop (gen_rtx (MEM, QImode, \
- gen_rtx (SYMBOL_REF, Pmode, \
- "__enable_execute_stack")), \
- const0_rtx, const0_rtx, const0_rtx)); \
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tldea LP%d,a1\n\tcallq mcount\n", (LABELNO));
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Store in the variable DEPTH the initial difference between the
- frame pointer reg contents and the stack pointer reg contents,
- as of the start of the function body. This depends on the layout
- of the fixed parts of the stack frame and on how registers are saved. */
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
-{ (DEPTH) = (get_frame_size () + 7) & -8; }
-\f
-/* Addressing modes, and classification of registers for them. */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
-
-#define REGNO_OK_FOR_INDEX_P(regno) \
- ((regno) <= LAST_VIRTUAL_REGISTER \
- ? regno_ok_for_index_p[regno] \
- : regno_ok_for_index_p[reg_renumber[regno]])
-
-#define REGNO_OK_FOR_BASE_P(regno) REGNO_OK_FOR_INDEX_P (regno)
-\f
-/* Maximum number of registers that can appear in a valid memory address. */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* 1 if X is an rtx for a constant that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-
-/* For convex, bounce 2-word constants that can't be immediate operands. */
-
-#define LEGITIMATE_CONSTANT_P(X) \
- (GET_CODE (X) != CONST_DOUBLE \
- || GET_MODE (X) == SFmode \
- || LD_L_P (X) || LD_D_P (X))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) \
- (REGNO (X) > LAST_VIRTUAL_REGISTER || regno_ok_for_index_p[REGNO (X)])
-
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- For Convex, valid addresses are
- indirectable or (MEM indirectable)
- where indirectable is
- const, reg, (PLUS reg const)
-
- We don't use indirection since with insn scheduling, load + indexing
- is better. */
-
-/* 1 if X is an address that we could indirect through. */
-#define INDIRECTABLE_ADDRESS_P(X) \
- (CONSTANT_ADDRESS_P (X) \
- || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
- || (GET_CODE (X) == PLUS \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
- && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
- || (GET_CODE (X) == PLUS \
- && GET_CODE (XEXP (X, 1)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 1)) \
- && CONSTANT_ADDRESS_P (XEXP (X, 0))))
-
-/* Go to ADDR if X is a valid address. */
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ register rtx xfoob = (X); \
- if (INDIRECTABLE_ADDRESS_P (xfoob)) \
- goto ADDR; \
- if (GET_CODE (xfoob) == PRE_DEC && XEXP (xfoob, 0) == stack_pointer_rtx) \
- goto ADDR; \
-}
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output.
-
- For Convex, nothing needs to be done. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
-\f
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this if the case instruction drops through after the table
- when the index is out of range. Don't define it if the case insn
- jumps to the default label instead. */
-/* #define CASE_DROPS_THROUGH */
-
-/* Define this as 1 if `char' should by default be signed; else as 0. */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
- also convert validly to an unsigned one. */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
- in one reasonably fast instruction. */
-#define MOVE_MAX 8
-
-/* Nonzero if access to memory by bytes is slow and undesirable. */
-#define SLOW_BYTE_ACCESS (! TARGET_C2)
-
-/* Define if shifts truncate the shift count
- which implies one can omit a sign-extension or zero-extension
- of a shift count. */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* On Convex, it is as good to call a constant function address as to
- call an address kept in a register. */
-#define NO_FUNCTION_CSE
-
-/* When a prototype says `char' or `short', really pass an `int'. */
-#define PROMOTE_PROTOTYPES 1
-
-/* Specify the machine mode that pointers have.
- After generation of rtl, the compiler makes no further distinction
- between pointers and any other objects of this machine mode. */
-#define Pmode SImode
-
-/* A function address in a call instruction
- is a byte address (for indexing purposes)
- so give the MEM rtx a byte's mode. */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- case CONST_INT: \
- case CONST_DOUBLE: \
- return 0;
-
-/* Provide the costs of a rtl expression. This is in the body of a
- switch on CODE. */
-
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
- case PLUS: \
- if (GET_CODE (XEXP (RTX, 0)) == REG \
- && REG_POINTER (XEXP (RTX, 0)) \
- && GET_CODE (XEXP (RTX, 1)) == CONST_INT) \
- return 0; \
- else break; \
- case MULT: \
- return 4 * (char) (0x03060403 >> target_cpu * 8); \
- case ASHIFT: \
- case LSHIFTRT: \
- case ASHIFTRT: \
- return 4 * (char) (0x03010403 >> target_cpu * 8); \
- case MEM: \
- return 5;
-
-/* Compute the cost of an address. This is meant to approximate the size
- and/or execution delay of an insn using that address. If the cost is
- approximated by the RTL complexity, including CONST_COSTS above, as
- is usually the case for CISC machines, this macro should not be defined.
- For aggressively RISCy machines, only one insn format is allowed, so
- this macro should be a constant. The value of this macro only matters
- for valid addresses. */
-
-#define ADDRESS_COST(RTX) 0
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
- should be added to avoid a branch. */
-
-#define BRANCH_COST 0
-
-/* Convex uses VAX or IEEE floats. Default to IEEE. */
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-/* Check a `double' value for validity for a particular machine mode. */
-#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
- (OVERFLOW = check_float_value (MODE, &D, OVERFLOW))
-\f
-/* Tell final.c how to eliminate redundant test instructions. */
-
-/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). No extra ones are needed for convex. */
-
-/* Store in cc_status the expressions
- that the condition codes will describe
- after execution of an instruction whose pattern is EXP.
- Do not alter them if the instruction would not alter the cc's. */
-
-#define NOTICE_UPDATE_CC(EXP,INSN) {}
-\f
-/* Control the assembler format that we output. */
-
-/* Output at beginning of assembler file. */
-
-#if _IEEE_FLOAT_
-#define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode ieee\n")
-#else
-#define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode native\n")
-#endif
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#define ASM_APP_ON ";APP\n"
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#define ASM_APP_OFF ";NO_APP\n"
-
-/* Alignment with Convex's assembler goes like this:
- .text can be .aligned up to a halfword.
- .data and .bss can be .aligned up to a longword.
- .lcomm is not supported, explicit declarations in .bss must be used instead.
- We get alignment for word and longword .text data by conventionally
- using .text 2 for word-aligned data and .text 3 for longword-aligned
- data. This requires that the data's size be a multiple of its alignment,
- which seems to be always true. */
-
-/* Output before read-only data. */
-
-#define TEXT_SECTION_ASM_OP (current_section_is_text = 1, "\t.text")
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP (current_section_is_text = 0, "\t.data")
-
-/* Output before uninitialized data. */
-
-#define BSS_SECTION_ASM_OP (current_section_is_text = 0, "\t.bss")
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) do { \
- if (current_section_is_text && (LOG) > 1) \
- fprintf (FILE, ".text %d\n", LOG); \
- else if (current_section_is_text) \
- fprintf (FILE, ".text\n.align %d\n", 1 << (LOG)); \
- else \
- fprintf (FILE, ".align %d\n", 1 << (LOG)); } while (0)
-
-/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
-
-#define REGISTER_NAMES \
-{ \
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
- "sp", "a1", "a2", "a3", "a4", "a5", "ap", "fp", \
-}
-
-/* This is BSD, so it wants DBX format. */
-
-#define DBX_DEBUGGING_INFO
-
-/* Do not break .stabs pseudos into continuations. */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
- continuation back on). */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't use stab extensions until GDB v4 port is available for convex. */
-
-#define DEFAULT_GDB_EXTENSIONS 0
-#define DBX_NO_XREFS
-
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
- do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* Put case tables in .text 2, where they will be word-aligned */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
- ASM_OUTPUT_ALIGN (FILE, 2); \
- ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM)
-
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \
- ASM_OUTPUT_ALIGN (FILE, 1)
-
-/* This is how to store into the string LABEL
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output a string */
-
-#define ASM_OUTPUT_ASCII(FILE,STR,SIZE) do { \
- size_t i, limit = (SIZE); \
- fprintf ((FILE), "\tds.b \""); \
- for (i = 0; i < limit; i++) { \
- register int c = (STR)[i] & 0377; \
- if (c >= ' ' && c < 0177 && c != '\\' && c != '"') \
- putc (c, (FILE)); \
- else \
- fprintf ((FILE), "\\%03o", c);} \
- fprintf ((FILE), "\"\n");} while (0)
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tpsh.%c %s\n", \
- S_REGNO_P (REGNO) ? 'l' : 'w', \
- reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tpop.%c %s\n", \
- S_REGNO_P (REGNO) ? 'l' : 'w', \
- reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- fprintf (FILE, "\tds.w L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
- (not used on Convex) */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\tds.w L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
- that says to advance the location counter by SIZE bytes. */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\tds.b %u(0)\n", (SIZE))
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( bss_section (), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ":\tbs.b %u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Output an arg count before function entries. */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
- asm_declare_function_name (FILE, NAME, DECL)
-
-/* Print an instruction operand X on file FILE.
- CODE is the code from the %-spec that requested printing this operand;
- if `%z3' was used to print operand 3, then CODE is 'z'. */
-
-#define PRINT_OPERAND(FILE, X, CODE) \
- print_operand (FILE, X, CODE)
-
-/* Print a memory operand whose address is X, on file FILE. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
- print_operand_address (FILE, ADDR)
-\f
-/* Do not put out GNU stabs for constructors and destructors.
- ld bounces them. */
-
-#define FASCIST_ASSEMBLER
-
-/* __gcc_cleanup is loader-aliased to __ap$do_registered_functions if we
- are linking against standard libc. */
-
-#define EXIT_BODY \
-{ \
- extern void __gcc_cleanup (); \
- if (__gcc_cleanup != _cleanup) \
- __gcc_cleanup (); \
- _cleanup (); \
-}
-\f
-/* Header for convex.c.
- Here at the end so we can use types defined above. */
-
-extern int target_cpu;
-extern int current_section_is_text;
-extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
-extern enum reg_class reg_class_from_letter[256];
-extern char regno_ok_for_index_p_base[];
-#define regno_ok_for_index_p (regno_ok_for_index_p_base + 1)
-
+++ /dev/null
-;;- Machine description for GNU compiler, Convex Version
-;; Copyright (C) 1988, 1994, 1995, 1998, 1999 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-\f
-;; Attribute specifications
-
-; Target CPU
-(define_attr "cpu" "c1,c32,c34,c38"
- (const (symbol_ref "(enum attr_cpu) target_cpu")))
-
-;; Instruction classification
-
-(define_attr "type"
- "alu,xalu,mldw,mldl,mldb,mst,adds,addd,mulw,mull,muls,muld,divw,divl,divs,divd,shfw,shfl,cvts,cvtd"
- (const_string "alu"))
-
-;; Instruction times
-
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "mldw")) 2 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "mldl")) 4 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "mldw,mldl")) 2 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "mldw,mldl")) 4 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "mldw,mldl")) 2 0)
-
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "mldb")) 9 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "mldb")) 36 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "mldb")) 21 0)
-
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "xalu")) 1 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "xalu")) 1 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "xalu")) 5 0)
-(define_function_unit "mem" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "xalu")) 2 0)
-
-(define_function_unit "add" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "adds,addd")) 3 2)
-(define_function_unit "add" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "adds,addd")) 2 1)
-(define_function_unit "add" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "adds,addd")) 5 2)
-(define_function_unit "add" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "adds,addd")) 2 1)
-
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "mulw,muls")) 3 2)
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "mulw,muls")) 4 2)
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "mulw,muls")) 6 2)
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "mulw,muls")) 3 2)
-
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "mull,muld")) 4 3)
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "mull")) 10 7)
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "muld")) 5 2)
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "mull,muld")) 7 3)
-(define_function_unit "mul" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "mull,muld")) 4 3)
-
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "divw")) 24 24)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "divw")) 44 6)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "divw")) 14 10)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "divw")) 11 10)
-
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "divl")) 41 42)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "divl")) 76 5)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "divl")) 22 18)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "divl")) 19 18)
-
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "divs")) 22 22)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "divs")) 8 6)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "divs")) 13 9)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "divs")) 10 9)
-
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "divd")) 37 38)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "divd")) 12 8)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "divd")) 20 16)
-(define_function_unit "div" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "divd")) 17 16)
-
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "cvts,cvtd")) 4 3)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "cvts")) 9 7)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "cvtd")) 9 6)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "cvts")) 6 2)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c34") (eq_attr "type" "cvtd")) 6 1)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "cvts,cvtd")) 3 1)
-
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c1") (eq_attr "type" "shfw,shfl")) 3 2)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "shfw")) 7 5)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c32") (eq_attr "type" "shfl")) 7 4)
-(define_function_unit "misc" 1 0
- (and (eq_attr "cpu" "c38") (eq_attr "type" "shfw,shfl")) 3 1)
-
-(define_function_unit "mystery_latch" 1 1
- (and (eq_attr "type" "!alu,mldw,mldl,adds,addd") (eq_attr "cpu" "c32")) 2 2)
-
-;(define_function_unit "ip" 1 1
-; (and (eq_attr "cpu" "c1")
-; (eq_attr "type" "divw,divl,divs,divd,xalu")) 2 2)
-;(define_function_unit "ip" 1 1
-; (and (eq_attr "cpu" "c1")
-; (eq_attr "type" "!divw,divl,divs,divd,xalu")) 1 1)
-;(define_function_unit "ip" 1 1
-; (and (eq_attr "cpu" "c32")
-; (eq_attr "type" "mull,muld,divl,divd,shfl,cvtd,xalu")) 2 2)
-;(define_function_unit "ip" 1 1
-; (and (eq_attr "cpu" "c32")
-; (eq_attr "type" "!mull,muld,divl,divd,shfl,cvtd,xalu")) 1 1)
-;(define_function_unit "ip" 1 1
-; (and (eq_attr "cpu" "c34")
-; (eq_attr "type" "addd,mull,muld,divl,divd,cvtd,xalu")) 2 2)
-;(define_function_unit "ip" 1 1
-; (and (eq_attr "cpu" "c34")
-; (eq_attr "type" "!addd,mull,muld,divl,divd,cvtd,xalu")) 1 1)
-\f
-;; Make the first thing a real insn in case of genattrtab bug
-
-(define_insn "nop"
- [(const_int 0)]
- ""
- "nop")
-\f
-;; Moves
-
-(define_expand "movdf"
- [(set (match_operand:DF 0 "general_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
- ""
- "if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (DFmode, operands[1]);")
-
-(define_insn ""
- [(set (match_operand:DF 0 "general_operand" "=d,d,d,d,d,<,m")
- (match_operand:DF 1 "general_operand" "d,Q,m,G,H,d,d"))]
- "register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)"
- "@
- mov %1,%0
- ldb.d %1,%0
- ld.d %1,%0
- ld.d %u1,%0
- ld.l %v1,%0
- psh.l %1
- st.d %1,%0"
- [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])
-
-;; This is here so we can load any result of RTL constant folding
-;; but do not use it on constants that can be loaded from memory.
-;; It is never better and can be worse.
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=d")
- (match_operand:DF 1 "const_double_operand" "F"))]
- "mem_for_const_double (operands[1]) == 0"
- "ld.u %u1,%0\;ld.w %v1,%0"
- [(set_attr "type" "xalu")])
-
-(define_expand "movsf"
- [(set (match_operand:SF 0 "general_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
- ""
- "if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (SFmode, operands[1]);")
-
-(define_insn ""
- [(set (match_operand:SF 0 "general_operand" "=d,d,d,d,<,m")
- (match_operand:SF 1 "general_operand" "d,Q,m,F,d,d"))]
- "register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode)"
- "@
- mov.s %1,%0
- ldb.s %1,%0
- ld.s %1,%0
- ld.s %1,%0
- psh.w %1
- st.s %1,%0"
- [(set_attr "type" "alu,mldb,mldw,alu,alu,mst")])
-
-(define_expand "movdi"
- [(set (match_operand:DI 0 "general_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
- ""
- "if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (DImode, operands[1]);")
-
-(define_insn ""
- [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,d,<,m")
- (match_operand:DI 1 "general_operand" "d,Q,m,G,HI,d,d"))]
- "register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode)"
- "@
- mov %1,%0
- ldb.l %1,%0
- ld.l %1,%0
- ld.d %u1,%0
- ld.l %1,%0
- psh.l %1
- st.l %1,%0"
- [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])
-
-;; This is here so we can load any result of RTL constant folding
-;; but do not use it on constants that can be loaded from memory.
-;; It is never better and can be worse.
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:DI 1 "const_double_operand" "F"))]
- "mem_for_const_double (operands[1]) == 0"
- "ld.u %u1,%0\;ld.w %v1,%0"
- [(set_attr "type" "xalu")])
-
-(define_expand "movsi"
- [(set (match_operand:SI 0 "general_operand" "")
- (match_operand:SI 1 "general_operand" ""))]
- ""
- "if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (SImode, operands[1]);")
-
-(define_insn ""
- [(set (match_operand:SI 0 "push_operand" "=<,<")
- (match_operand:SI 1 "nonmemory_operand" "Ad,i"))]
- ""
- "@
- psh.w %1
- pshea %a1")
-
-(define_insn ""
- [(set (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m")
- (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
- "register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)"
- "@
- mov.w %1,%0
- mov %1,%0
- ldb.w %1,%0
- ld.w %1,%0
- ld.w %1,%0
- st.w %1,%0"
- [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])
-
-(define_expand "movstrictsi"
- [(set (strict_low_part (match_operand:SI 0 "general_operand" ""))
- (match_operand:SI 1 "general_operand" ""))]
- ""
- "if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (SImode, operands[1]);")
-
-(define_insn ""
- [(set (strict_low_part (match_operand:SI 0 "general_operand" "+d,r,d,r,r,m"))
- (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
- "register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)"
- "@
- mov.w %1,%0
- mov %1,%0
- ldb.w %1,%0
- ld.w %1,%0
- ld.w %1,%0
- st.w %1,%0"
- [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])
-
-(define_expand "movhi"
- [(set (match_operand:HI 0 "general_operand" "")
- (match_operand:HI 1 "general_operand" ""))]
- ""
- "if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (HImode, operands[1]);")
-
-(define_insn ""
- [(set (match_operand:HI 0 "general_operand" "=d,r,d,r,r,<,m")
- (match_operand:HI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
- "register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode)"
- "@
- mov.w %1,%0
- mov %1,%0
- ldb.h %1,%0
- ld.h %1,%0
- ld.w %1,%0
- psh.w %1
- st.h %1,%0"
- [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])
-
-(define_expand "movqi"
- [(set (match_operand:QI 0 "general_operand" "")
- (match_operand:QI 1 "general_operand" ""))]
- ""
- "if (GET_CODE (operands[0]) != REG)
- operands[1] = force_reg (QImode, operands[1]);")
-
-(define_insn ""
- [(set (match_operand:QI 0 "general_operand" "=d,r,d,r,r,<,m")
- (match_operand:QI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
- "register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode)"
- "@
- mov.w %1,%0
- mov %1,%0
- ldb.b %1,%0
- ld.b %1,%0
- ld.w %1,%0
- psh.w %1
- st.b %1,%0"
- [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])
-
-;; Expand block moves manually to get code that pipelines the loads.
-
-(define_expand "movstrsi"
- [(set (match_operand:BLK 0 "memory_operand" "=m")
- (match_operand:BLK 1 "memory_operand" "m"))
- (use (match_operand:SI 2 "const_int_operand" "i"))
- (use (match_operand:SI 3 "const_int_operand" "i"))]
- ""
- " expand_movstr (operands); DONE; ")
-\f
-;; Extension and truncation insns.
-;; Those for integer source operand
-;; are ordered widest source type first.
-
-(define_insn "truncsiqi2"
- [(set (match_operand:QI 0 "register_operand" "=d,a")
- (truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]
- ""
- "cvtw.b %1,%0")
-
-(define_insn "truncsihi2"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]
- ""
- "cvtw.h %1,%0")
-
-(define_insn "trunchiqi2"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (truncate:QI (match_operand:HI 1 "register_operand" "0")))]
- ""
- "")
-
-(define_insn "truncdisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (truncate:SI (match_operand:DI 1 "register_operand" "d")))]
- ""
- "cvtl.w %1,%0")
-
-(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
- ""
- "cvtw.l %1,%0")
-
-(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]
- ""
- "cvth.w %1,%0")
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]
- ""
- "cvtb.w %1,%0")
-
-(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]
- ""
- "cvtb.w %1,%0")
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (float_extend:DF (match_operand:SF 1 "register_operand" "d")))]
- ""
- "cvts.d %1,%0"
- [(set_attr "type" "cvts")])
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]
- ""
- "cvtd.s %1,%0"
- [(set_attr "type" "cvtd")])
-
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
- ""
- "and #0xffff,%0")
-
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]
- ""
- "and #0xff,%0")
-
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
- ""
- "and #0xff,%0")
-
-(define_insn "zero_extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]
- ""
- "ld.u #0,%0")
-\f
-;; Fix-to-float conversion insns.
-;; Note that the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (float:SF (match_operand:SI 1 "register_operand" "d")))]
- ""
- "cvtw.s %1,%0"
- [(set_attr "type" "cvts")])
-
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (float:SF (match_operand:DI 1 "register_operand" "d")))]
- ""
- "cvtl.s %1,%0"
- [(set_attr "type" "cvtd")])
-
-(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (float:DF (match_operand:SI 1 "register_operand" "d")))]
- "! TARGET_C1"
- "cvtw.d %1,%0"
- [(set_attr "type" "cvts")])
-
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (float:DF (match_operand:DI 1 "register_operand" "d")))]
- ""
- "cvtl.d %1,%0"
- [(set_attr "type" "cvtd")])
-
-;; These are a little slower than gcc's normal way of doing unsigned
-;; DI floats (if the DI number is "negative") but they avoid double
-;; rounding and they avoid explicit constants.
-
-(define_expand "floatunsdidf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (float:DF (match_operand:DI 1 "register_operand" "d")))
- (set (cc0) (compare:DI (match_dup 3) (match_dup 1)))
- (set (pc)
- (if_then_else (le (cc0) (const_int 0))
- (label_ref (match_dup 4))
- (pc)))
- (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1)))
- (set (match_dup 0) (float:DF (match_dup 2)))
- (set (match_dup 0) (plus:DF (match_dup 0) (match_dup 0)))
- (match_dup 4)
- (set (match_dup 0) (match_dup 0))]
- ""
- "
-{
- operands[2] = gen_reg_rtx (DImode);
- operands[3] = force_reg (DImode, const0_rtx);
- operands[4] = gen_label_rtx ();
-}")
-
-(define_expand "floatunsdisf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (float:SF (match_operand:DI 1 "register_operand" "d")))
- (set (cc0) (compare:DI (match_dup 3) (match_dup 1)))
- (set (pc)
- (if_then_else (le (cc0) (const_int 0))
- (label_ref (match_dup 4))
- (pc)))
- (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1)))
- (set (match_dup 0) (float:SF (match_dup 2)))
- (set (match_dup 0) (plus:SF (match_dup 0) (match_dup 0)))
- (match_dup 4)
- (set (match_dup 0) (match_dup 0))]
- ""
- "
-{
- operands[2] = gen_reg_rtx (DImode);
- operands[3] = force_reg (DImode, const0_rtx);
- operands[4] = gen_label_rtx ();
-}")
-
-;; These patterns are identical to gcc's default action
-;; if DI->DF and DI->SF are not present. There are here
-;; only to prevent SI->*F from promoting to DI->*F.
-
-(define_expand "floatunssidf2"
- [(set (match_dup 2)
- (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
- (set (match_operand:DF 0 "register_operand" "")
- (float:DF (match_dup 2)))]
- ""
- "operands[2] = gen_reg_rtx (DImode);")
-
-(define_expand "floatunssisf2"
- [(set (match_dup 2)
- (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
- (set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_dup 2)))]
- ""
- "operands[2] = gen_reg_rtx (DImode);")
-\f
-;; Float-to-fix conversion insns.
-
-(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
- ""
- "cvts.w %1,%0"
- [(set_attr "type" "cvts")])
-
-(define_insn "fix_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
- ""
- "cvts.l %1,%0"
- [(set_attr "type" "cvts")])
-
-(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
- ""
- "cvtd.l %1,%0"
- [(set_attr "type" "cvtd")])
-
-(define_insn "fix_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
- ""
- "cvtd.l %1,%0"
- [(set_attr "type" "cvtd")])
-\f
-;;- All kinds of add instructions.
-
-(define_insn "adddf3"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (plus:DF (match_operand:DF 1 "register_operand" "%0")
- (match_operand:DF 2 "register_operand" "d")))]
- ""
- "add.d %2,%0"
- [(set_attr "type" "addd")])
-
-(define_insn "addsf3"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (plus:SF (match_operand:SF 1 "register_operand" "%0")
- (match_operand:SF 2 "nonmemory_operand" "dF")))]
- ""
- "add.s %2,%0"
- [(set_attr "type" "adds")])
-
-(define_insn "adddi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (plus:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "add.l %2,%0")
-
-(define_expand "addsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=a")
- (plus:SI (match_operand:SI 1 "register_operand" "%A")
- (match_operand:SI 2 "immediate_operand" "i")))]
- "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx"
- "ldea %a2(%1),%0")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=a")
- (plus:SI (match_operand:SI 1 "register_operand" "%a")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
- "operands[1] == stack_pointer_rtx && operands[0] != stack_pointer_rtx"
- "mov %1,%0\;add.w %2,%0")
-
-(define_insn ""
- [(set (match_operand:SI 0 "push_operand" "=<")
- (plus:SI (match_operand:SI 1 "register_operand" "A")
- (match_operand:SI 2 "immediate_operand" "i")))]
- "operands[1] != stack_pointer_rtx"
- "pshea %a2(%1)"
- [(set_attr "type" "mst")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,a,a")
- (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A")
- (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
- "TARGET_C1"
- "@
- add.w %2,%0
- add.w %2,%0
- ldea %a2(%1),%0")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,a,r")
- (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A")
- (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
- ""
- "@
- add.w %2,%0
- add.w %2,%0
- ldea %a2(%1),%0")
-
-(define_insn "addhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
- ""
- "add.h %2,%0")
-
-(define_insn "addqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,d")
- (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "d,i")))]
- ""
- "@
- add.b %2,%0
- add.w %2,%0")
-\f
-;;- All kinds of subtract instructions.
-
-(define_insn "subdf3"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (minus:DF (match_operand:DF 1 "register_operand" "0")
- (match_operand:DF 2 "register_operand" "d")))]
- ""
- "sub.d %2,%0"
- [(set_attr "type" "addd")])
-
-(define_insn "subsf3"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (minus:SF (match_operand:SF 1 "register_operand" "0")
- (match_operand:SF 2 "nonmemory_operand" "dF")))]
- ""
- "sub.s %2,%0"
- [(set_attr "type" "adds")])
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "sub.l %2,%0")
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,a,?d,?a")
- (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,0,di,ai")
- (match_operand:SI 2 "nonmemory_operand" "di,ai,0,0")))]
- ""
- "@
- sub.w %2,%0
- sub.w %2,%0
- sub.w %1,%0\;neg.w %0,%0
- sub.w %1,%0\;neg.w %0,%0")
-
-(define_insn "subhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (minus:HI (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
- ""
- "sub.h %2,%0")
-
-(define_insn "subqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,d")
- (minus:QI (match_operand:QI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "d,i")))]
- ""
- "@
- sub.b %2,%0
- sub.w %2,%0")
-\f
-;;- Multiply instructions.
-
-(define_insn "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (mult:DF (match_operand:DF 1 "register_operand" "%0")
- (match_operand:DF 2 "register_operand" "d")))]
- ""
- "mul.d %2,%0"
- [(set_attr "type" "muld")])
-
-(define_insn "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (mult:SF (match_operand:SF 1 "register_operand" "%0")
- (match_operand:SF 2 "nonmemory_operand" "dF")))]
- ""
- "mul.s %2,%0"
- [(set_attr "type" "muls")])
-
-(define_insn "muldi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (mult:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "mul.l %2,%0"
- [(set_attr "type" "mull")])
-
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- ""
- "mul.w %2,%0"
- [(set_attr "type" "mulw")])
-
-(define_insn "mulhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
- ""
- "mul.h %2,%0"
- [(set_attr "type" "mulw")])
-
-(define_insn "mulqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,d")
- (mult:QI (match_operand:QI 1 "register_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "d,i")))]
- ""
- "@
- mul.b %2,%0
- mul.w %2,%0"
- [(set_attr "type" "mulw,mulw")])
-\f
-;;- Divide instructions.
-
-(define_insn "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (div:DF (match_operand:DF 1 "register_operand" "0")
- (match_operand:DF 2 "register_operand" "d")))]
- ""
- "div.d %2,%0"
- [(set_attr "type" "divd")])
-
-(define_insn "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (div:SF (match_operand:SF 1 "register_operand" "0")
- (match_operand:SF 2 "nonmemory_operand" "dF")))]
- ""
- "div.s %2,%0"
- [(set_attr "type" "divs")])
-
-(define_insn "divdi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (div:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "div.l %2,%0"
- [(set_attr "type" "divl")])
-
-(define_expand "udivsi3"
- [(set (match_dup 3)
- (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
- (set (match_dup 4)
- (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
- (set (match_dup 3)
- (div:DI (match_dup 3) (match_dup 4)))
- (set (match_operand:SI 0 "register_operand" "")
- (subreg:SI (match_dup 3) 0))]
- ""
- "operands[3] = gen_reg_rtx (DImode);
- operands[4] = gen_reg_rtx (DImode); ")
-
-(define_insn "udivdi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (udiv:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp")
-
-(define_insn "divsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (div:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- ""
- "div.w %2,%0"
- [(set_attr "type" "divw")])
-
-(define_insn "divhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (div:HI (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
- ""
- "div.h %2,%0"
- [(set_attr "type" "divw")])
-
-(define_insn "divqi3"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (div:QI (match_operand:QI 1 "register_operand" "0")
- (match_operand:QI 2 "register_operand" "d")))]
- ""
- "div.b %2,%0"
- [(set_attr "type" "divw")])
-\f
-;;- Bit clear instructions.
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "" "")))]
- "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- || (GET_CODE (operands[2]) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (operands[2]) == -1)"
- "and %2,%0")
-
-(define_insn "anddi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "and %2,%0")
-
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (and:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- ""
- "and %2,%0")
-
-(define_insn "andhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (and:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
- ""
- "and %2,%0")
-
-(define_insn "andqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,a")
- (and:QI (match_operand:QI 1 "register_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
- ""
- "and %2,%0")
-
-;;- Bit set instructions.
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ior:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "" "")))]
- "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
- || (GET_CODE (operands[2]) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (operands[2]) == 0)"
- "or %2,%0")
-
-(define_insn "iordi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ior:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "or %2,%0")
-
-(define_insn "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- ""
- "or %2,%0")
-
-(define_insn "iorhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
- ""
- "or %2,%0")
-
-(define_insn "iorqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,a")
- (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
- ""
- "or %2,%0")
-
-;;- xor instructions.
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (xor:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "" "")))]
- "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
- || (GET_CODE (operands[2]) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (operands[2]) == 0)"
- "xor %2,%0")
-
-(define_insn "xordi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (xor:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "register_operand" "d")))]
- ""
- "xor %2,%0")
-
-(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- ""
- "xor %2,%0")
-
-(define_insn "xorhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (xor:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
- ""
- "xor %2,%0")
-
-(define_insn "xorqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,a")
- (xor:QI (match_operand:QI 1 "register_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
- ""
- "xor %2,%0")
-\f
-(define_insn "negdf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (neg:DF (match_operand:DF 1 "register_operand" "d")))]
- ""
- "neg.d %1,%0"
- [(set_attr "type" "addd")])
-
-(define_insn "negsf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (neg:SF (match_operand:SF 1 "register_operand" "d")))]
- ""
- "neg.s %1,%0"
- [(set_attr "type" "adds")])
-
-(define_insn "negdi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))]
- ""
- "neg.l %1,%0")
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (neg:SI (match_operand:SI 1 "register_operand" "d,a")))]
- ""
- "neg.w %1,%0")
-
-(define_insn "neghi2"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (neg:HI (match_operand:HI 1 "register_operand" "d,a")))]
- ""
- "neg.h %1,%0")
-
-(define_insn "negqi2"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (neg:QI (match_operand:QI 1 "register_operand" "d")))]
- ""
- "neg.b %1,%0")
-\f
-(define_insn "one_cmpldi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (not:DI (match_operand:DI 1 "register_operand" "d")))]
- ""
- "not %1,%0")
-
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (not:SI (match_operand:SI 1 "register_operand" "d,a")))]
- ""
- "not %1,%0")
-
-(define_insn "one_cmplhi2"
- [(set (match_operand:HI 0 "register_operand" "=d,a")
- (not:HI (match_operand:HI 1 "register_operand" "d,a")))]
- ""
- "not %1,%0")
-
-(define_insn "one_cmplqi2"
- [(set (match_operand:QI 0 "register_operand" "=d,a")
- (not:QI (match_operand:QI 1 "register_operand" "d,a")))]
- ""
- "not %1,%0")
-\f
-;;- Shifts
-;;
-;; The extreme profusion of patterns here is due to the different-speed
-;; shifts on different machines, and the C1's lack of word shift S-register
-;; instructions.
-
-;; SImode
-
-;; Arithmetic left 1, 1 cycle on all machines via add
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashift:SI (match_operand:SI 1 "register_operand" "0")
- (const_int 1)))]
- ""
- "add.w %0,%0")
-
-;; C34 general shift is 1 cycle
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- "TARGET_C34"
- "@
- shf.w %2,%0
- shf %2,%0"
- [(set_attr "type" "shfw,shfw")])
-
-;; else shift left 0..7 is 1 cycle if we use an A register
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=a,?d")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "immediate_operand" "ai,di")))]
- "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8"
- "@
- shf %2,%0
- shf %2,%0"
- [(set_attr "type" "alu,shfl")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=a,?d")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "immediate_operand" "ai,di")))]
- "INTVAL (operands[2]) < (unsigned) 8"
- "@
- shf %2,%0
- shf.w %2,%0"
- [(set_attr "type" "alu,shfw")])
-
-;; else general left shift
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- "TARGET_C1"
- "@
- shf %2,%0
- shf %2,%0"
- [(set_attr "type" "shfl,shfw")])
-
-;; but C2 left shift by a constant is faster via multiply
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashift:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "const_int_operand" "i")))]
- "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32"
- "mul.w %z2,%0"
- [(set_attr "type" "mulw")])
-
-(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,a")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
- ""
- "@
- shf.w %2,%0
- shf %2,%0"
- [(set_attr "type" "shfw,shfw")])
-
-;; Logical right, general
-;; The hardware wants the negative of the shift count
-
-(define_expand "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
- ""
- "operands[2] = negate_rtx (SImode, operands[2]);")
-
-;; C1 lacks word shift S reg
-
-(define_insn ""
- [(set
- (match_operand:SI 0 "register_operand" "=a,?d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "ai,di"))))]
- "TARGET_C1"
- "@
- shf %2,%0
- ld.u #0,%0\;shf %2,%0"
- [(set_attr "type" "shfw,shfl")])
-
-;; general case
-
-(define_insn ""
- [(set
- (match_operand:SI 0 "register_operand" "=d,a")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))]
- ""
- "@
- shf.w %2,%0
- shf %2,%0"
- [(set_attr "type" "shfw,shfw")])
-
-;; Patterns without neg produced by constant folding
-
-(define_insn ""
- [(set
- (match_operand:SI 0 "register_operand" "=a,?d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "immediate_operand" "i,i")))]
- "TARGET_C1"
- "@
- shf #%n2,%0
- ld.u #0,%0\;shf #%n2,%0"
- [(set_attr "type" "shfw,shfl")])
-
-(define_insn ""
- [(set
- (match_operand:SI 0 "register_operand" "=d,a")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "immediate_operand" "i,i")))]
- ""
- "@
- shf.w #%n2,%0
- shf #%n2,%0"
- [(set_attr "type" "shfw,shfw")])
-
-;; Arithmetic right, general
-;; Sign-extend to 64 bits, then shift that. Works for 0..32.
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
- ""
- "operands[2] = negate_rtx (SImode, operands[2]);")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,&d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
- (neg:SI
- (match_operand:SI 2 "nonmemory_operand" "di,di"))))]
- ""
- "cvtw.l %1,%0\;shf %2,%0"
- [(set_attr "type" "shfl,shfl")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "immediate_operand" "i")))]
- ""
- "cvtw.l %1,%0\;shf #%n2,%0"
- [(set_attr "type" "shfl")])
-
-;; DImode
-;; Arithmetic left, 1-cycle
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "0")
- (const_int 1)))]
- ""
- "add.l %0,%0")
-
-;; Arithmetic left, general
-
-(define_insn "ashldi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "di")))]
- ""
- "shf %2,%0"
- [(set_attr "type" "shfl")])
-
-;; Can omit zero- or sign-extend if shift is 32 or more.
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
- (match_operand:SI 2 "const_int_operand" "i")))]
- "INTVAL (operands[2]) >= 32"
- "shf %2,%0"
- [(set_attr "type" "shfl")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
- (match_operand:SI 2 "const_int_operand" "i")))]
- "INTVAL (operands[2]) >= 32"
- "shf %2,%0"
- [(set_attr "type" "shfl")])
-
-;; Logical right, general
-
-(define_expand "lshrdi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
- ""
- "operands[2] = negate_rtx (SImode, operands[2]);")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
- ""
- "shf %2,%0"
- [(set_attr "type" "shfl")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")))]
- ""
- "shf #%n2,%0"
- [(set_attr "type" "shfl")])
-
-;; Arithmetic right, general
-;; Use
-;; ((a >> b) ^ signbit) - signbit
-;; where signbit is (1 << 63) >> b
-;; Works for 0..63. Does not work for 64; unfortunate but valid.
-
-(define_expand "ashrdi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))
- (set (match_dup 3) (lshiftrt:DI (match_dup 3) (neg:SI (match_dup 2))))
- (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 3)))
- (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
- ""
- "
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- switch (INTVAL (operands[2]))
- {
- case 32:
- emit_insn (gen_ashrdi3_32 (operands[0], operands[1]));
- DONE;
- }
-
- operands[2] = negate_rtx (SImode, operands[2]);
- operands[3] = force_reg (DImode, immed_double_const (0, 1 << 31, DImode));
-}")
-
-;; Arithmetic right 32, a common case that can save a couple of insns.
-
-(define_expand "ashrdi3_32"
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 32)))
- (set (match_dup 0)
- (sign_extend:DI (subreg:SI (match_dup 0) 0)))]
- ""
- "")
-\f
-;; __builtin instructions
-
-(define_insn "sqrtdf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
- "! TARGET_C1 && flag_unsafe_math_optimizations"
- "sqrt.d %0"
- [(set_attr "type" "divd")])
-
-(define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
- "! TARGET_C1 && flag_unsafe_math_optimizations"
- "sqrt.s %0"
- [(set_attr "type" "divs")])
-
-(define_insn "sindf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
- "! TARGET_C1 && flag_unsafe_math_optimizations"
- "sin.d %0")
-
-(define_insn "sinsf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
- "! TARGET_C1 && flag_unsafe_math_optimizations"
- "sin.s %0")
-
-(define_insn "cosdf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
- "! TARGET_C1 && flag_unsafe_math_optimizations"
- "cos.d %0")
-
-(define_insn "cossf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
- "! TARGET_C1 && flag_unsafe_math_optimizations"
- "cos.s %0")
-
-(define_insn "ftruncdf2"
- [(set (match_operand:DF 0 "register_operand" "=d")
- (fix:DF (match_operand:DF 1 "register_operand" "d")))]
- "! TARGET_C1"
- "frint.d %1,%0"
- [(set_attr "type" "cvtd")])
-
-(define_insn "ftruncsf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (fix:SF (match_operand:SF 1 "register_operand" "d")))]
- "! TARGET_C1"
- "frint.s %1,%0"
- [(set_attr "type" "cvts")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
- (const_int 1)))]
- ""
- "tzc %1,%0\;le.w #32,%0\;jbrs.f L0%=\;ld.w #-1,%0\\nL0%=:")
-
-(define_expand "ffssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
- (const_int 1)))
- (set (match_dup 0)
- (plus:SI (match_dup 0)
- (const_int 1)))]
- ""
- "")
-
-(define_insn "abssf2"
- [(set (match_operand:SF 0 "register_operand" "=d")
- (abs:SF (match_operand:SF 1 "register_operand" "0")))]
- ""
- "and #0x7fffffff,%0")
-
-(define_expand "absdf2"
- [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0)
- (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0)
- (match_dup 2)))]
- ""
- "operands[2] = force_reg (DImode,
- immed_double_const (-1, 0x7fffffff, DImode));")
-\f
-;;- Compares
-
-(define_insn "cmpdi"
- [(set (cc0)
- (compare (match_operand:DI 0 "register_operand" "d")
- (match_operand:DI 1 "register_operand" "d")))]
- ""
- "* return output_cmp (operands[0], operands[1], 'l');")
-
-(define_insn ""
- [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
- (clobber (match_scratch:DI 1 "=d"))]
- "next_insn_tests_no_inequality (insn)"
- "* return output_cmp (operands[0], operands[1], 'L');")
-
-(define_insn "cmpsi"
- [(set (cc0)
- (compare (match_operand:SI 0 "register_operand" "d,a")
- (match_operand:SI 1 "nonmemory_operand" "di,ai")))]
- ""
- "* return output_cmp (operands[0], operands[1], 'w');")
-
-(define_insn "cmphi"
- [(set (cc0)
- (compare (match_operand:HI 0 "register_operand" "d,a")
- (match_operand:HI 1 "nonmemory_operand" "di,ai")))]
- ""
- "* return output_cmp (operands[0], operands[1], 'h');")
-
-; cmpqi is intentionally omitted.
-;
-; gcc will sign-extend or zero-extend the operands to the next
-; wider mode, HImode.
-;
-; For reg .cmp. constant, we just go with the halfword immediate
-; instruction. Perhaps the widening insn can be cse'd or combined away.
-; If not, we're still as good as loading a byte constant into a register
-; to do a reg-reg byte compare.
-;
-; The following patterns pick up cases that can use reg .cmp. reg after all.
-
-(define_insn ""
- [(set (cc0)
- (compare
- (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
- (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))))]
- ""
- "* return output_cmp (operands[0], operands[1], 'b');")
-
-(define_insn ""
- [(set (cc0)
- (compare
- (ashift:HI (subreg:HI (match_operand:QI 0 "register_operand" "d") 0)
- (const_int 8))
- (ashift:HI (subreg:HI (match_operand:QI 1 "register_operand" "d") 0)
- (const_int 8))))]
- ""
- "* return output_cmp (operands[0], operands[1], 'b');")
-
-(define_insn ""
- [(set (cc0)
- (compare (match_operand:QI 0 "register_operand" "d")
- (match_operand:QI 1 "register_operand" "d")))]
- ""
- "* return output_cmp (operands[0], operands[1], 'b');")
-
-(define_insn ""
- [(set (cc0) (match_operand:QI 0 "register_operand" "d"))
- (clobber (match_scratch:QI 1 "=d"))]
- "next_insn_tests_no_inequality (insn)"
- "* return output_cmp (operands[0], operands[1], 'B');")
-
-(define_insn ""
- [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d") 0))
- (clobber (match_scratch:QI 1 "=d"))]
- "next_insn_tests_no_inequality (insn)"
- "* return output_cmp (operands[0], operands[1], 'B');")
-
-(define_insn ""
- [(set (cc0)
- (zero_extend (subreg (match_operand:QI 0 "register_operand" "d") 0)))
- (clobber (match_scratch:QI 1 "=d"))]
- "next_insn_tests_no_inequality (insn)"
- "* return output_cmp (operands[0], operands[1], 'B');")
-
-(define_insn "cmpdf"
- [(set (cc0)
- (compare (match_operand:DF 0 "register_operand" "d")
- (match_operand:DF 1 "register_operand" "d")))]
- ""
- "* return output_cmp (operands[0], operands[1], 'd');")
-
-(define_insn "cmpsf"
- [(set (cc0)
- (compare (match_operand:SF 0 "register_operand" "d")
- (match_operand:SF 1 "nonmemory_cmpsf_operand" "dF")))]
- ""
- "* return output_cmp (operands[0], operands[1], 's');")
-\f
-;; decrement-and-set-cc0 insns.
-;;
-;; The most important case where we can use the carry bit from an
-;; arithmetic insn to eliminate a redundant compare is the decrement in
-;; constructs like while (n--) and while (--n >= 0).
-;;
-;; We do it with combine patterns instead of NOTICE_UPDATE_CC because
-;; the decrement needs to be kept at the end of the block during scheduling.
-;;
-;; These patterns must have memory alternatives because reload refuses
-;; to do output reloads for an insn that sets cc0 (since it does not
-;; want to clobber cc0 with its moves). Convex moves do not clobber
-;; cc0, but there is no evident way to get reload to know that.
-
-(define_insn ""
- [(set (cc0)
- (match_operand:SI 0 "register_operand" "+r,*m"))
- (set (match_dup 0)
- (plus:SI (match_dup 0)
- (const_int -1)))]
- "next_insn_tests_no_inequality (insn)"
- "*
-{
- if (which_alternative == 0)
- {
- output_cmp (operands[0], constm1_rtx, 'W');
- return \"add.w #-1,%0\";
- }
- else
- {
- output_cmp (gen_rtx_REG (SImode, 7), constm1_rtx, 'W');
- return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
- }
-}")
-
-(define_insn ""
- [(set (cc0)
- (plus:SI (match_operand:SI 0 "register_operand" "+r,*m")
- (const_int -1)))
- (set (match_dup 0)
- (plus:SI (match_dup 0)
- (const_int -1)))]
- "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
- "*
-{
- if (which_alternative == 0)
- {
- output_cmp (operands[0], const0_rtx, 'W');
- return \"add.w #-1,%0\";
- }
- else
- {
- output_cmp (gen_rtx_REG (SImode, 7), const0_rtx, 'W');
- return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
- }
-}")
-
-(define_insn ""
- [(set (cc0)
- (match_operand:HI 0 "register_operand" "+r,*m"))
- (set (match_dup 0)
- (plus:HI (match_dup 0)
- (const_int -1)))]
- "next_insn_tests_no_inequality (insn)"
- "*
-{
- if (which_alternative == 0)
- {
- output_cmp (operands[0], constm1_rtx, 'H');
- return \"add.h #-1,%0\";
- }
- else
- {
- output_cmp (gen_rtx_REG (HImode, 7), constm1_rtx, 'H');
- return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
- }
-}")
-
-(define_insn ""
- [(set (cc0)
- (plus:HI (match_operand:HI 0 "register_operand" "+r,*m")
- (const_int -1)))
- (set (match_dup 0)
- (plus:HI (match_dup 0)
- (const_int -1)))]
- "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
- "*
-{
- if (which_alternative == 0)
- {
- output_cmp (operands[0], const0_rtx, 'H');
- return \"add.h #-1,%0\";
- }
- else
- {
- output_cmp (gen_rtx_REG (HImode, 7), const0_rtx, 'H');
- return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
- }
-}")
-\f
-;;- Jumps
-
-(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
- ""
- "jbr %l0")
-
-(define_insn "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"eq\", 't'); ")
-
-(define_insn "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"eq\", 'f'); ")
-
-(define_insn "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"le\", 'f'); ")
-
-(define_insn "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"leu\", 'f'); ")
-
-(define_insn "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"lt\", 't'); ")
-
-(define_insn "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"ltu\", 't'); ")
-
-(define_insn "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"lt\", 'f'); ")
-
-(define_insn "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"ltu\", 'f'); ")
-
-(define_insn "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"le\", 't'); ")
-
-(define_insn "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return output_condjump (operands[0], \"leu\", 't'); ")
-\f
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"eq\", 'f'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"eq\", 't'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"le\", 't'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"leu\", 't'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"lt\", 'f'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"ltu\", 'f'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"lt\", 't'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"ltu\", 't'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"le\", 'f'); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return output_condjump (operands[0], \"leu\", 'f'); ")
-\f
-;;- Calls
-
-(define_expand "call_pop"
- [(parallel [(call (match_operand:QI 0 "memory_operand" "m")
- (match_operand:SI 1 "const_int_operand" "i"))
- (match_operand:SI 2 "const_int_operand" "i")
- (match_operand:SI 3 "const_int_operand" "i")
- (reg:SI 8)])]
- ""
- "")
-
-(define_insn ""
- [(call (match_operand:QI 0 "memory_operand" "m")
- (match_operand:SI 1 "const_int_operand" "i"))
- (match_operand:SI 2 "const_int_operand" "i")
- (match_operand:SI 3 "const_int_operand" "i")
- (match_operand:SI 4 "" "")]
- ""
- "* return output_call (insn, &operands[0]);")
-
-(define_expand "call_value_pop"
- [(parallel [(set (match_operand 0 "" "=g")
- (call (match_operand:QI 1 "memory_operand" "m")
- (match_operand:SI 2 "const_int_operand" "i")))
- (match_operand:SI 3 "const_int_operand" "i")
- (match_operand:SI 4 "const_int_operand" "i")
- (reg:SI 8)])]
- ""
- "")
-
-(define_insn ""
- [(set (match_operand 0 "" "=g")
- (call (match_operand:QI 1 "memory_operand" "m")
- (match_operand:SI 2 "const_int_operand" "i")))
- (match_operand:SI 3 "const_int_operand" "i")
- (match_operand:SI 4 "const_int_operand" "i")
- (match_operand:SI 5 "" "")]
- ""
- "* return output_call (insn, &operands[1]); ")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
- (const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
- ""
- "
-{
- int i;
-
- emit_call_insn (gen_call_pop (operands[0], const0_rtx,
- const0_rtx, const0_rtx));
-
- for (i = 0; i < XVECLEN (operands[2], 0); i++)
- {
- rtx set = XVECEXP (operands[2], 0, i);
- emit_move_insn (SET_DEST (set), SET_SRC (set));
- }
-
- /* The optimizer does not know that the call sets the function value
- registers we stored in the result block. We avoid problems by
- claiming that all hard registers are used and clobbered at this
- point. */
- emit_insn (gen_blockage ());
-
- DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory. This blocks insns from being moved across this point.
-
-(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
- ""
- "")
-
-(define_expand "return"
- [(return)]
- ""
- " replace_arg_pushes (); ")
-
-(define_insn ""
- [(return)]
- ""
- "rtn")
-
-(define_expand "prologue"
- [(const_int 0)]
- ""
- "
-{
- emit_ap_optimizations ();
- DONE;
-}")
-
-(define_insn "tablejump"
- [(set (pc) (match_operand:SI 0 "address_operand" "p"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
- "jmp %a0")
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
- ""
- "jmp %a0")
+++ /dev/null
-
-# This is a shell archive. Remove anything before this line,
-# then unpack it by saving it in a file and typing "sh file".
-#
-# Wrapped by on Fri Mar 12 08:41:28 CST 1993
-# Contents: include/ include/limits.h include/math.h include/stddef.h
-# include/stdlib.h
-
-echo mkdir - include
-mkdir include
-chmod u=rwx,g=rwx,o=rx include
-
-echo x - include/limits.h
-sed 's/^@//' > "include/limits.h" <<'@//E*O*F include/limits.h//'
-#ifndef _LIMITS_H
-#define _LIMITS_H
-
- #include_next <limits.h>
-
-/* Minimum and maximum values a `char' can hold. */
-#ifdef __CHAR_UNSIGNED__
-#undef CHAR_MIN
-#define CHAR_MIN 0
-#undef CHAR_MAX
-#define CHAR_MAX 255
-#endif
-
-#endif /* _LIMITS_H */
-@//E*O*F include/limits.h//
-chmod u=rw,g=rw,o=r include/limits.h
-
-echo x - include/math.h
-sed 's/^@//' > "include/math.h" <<'@//E*O*F include/math.h//'
-#ifndef _MATH_H
-#define _MATH_H
-
- #include_next <math.h>
-
-#undef HUGE_VAL
-
-#if _IEEE_FLOAT_
-#define HUGE_VAL 1.79769313486231570e+308
-#else
-#define HUGE_VAL 8.98846567431157854e+307
-#endif
-
-#if __OPTIMIZE__ && ! __NO_INLINE
-
-#define frexp(x,y) __inline_frexp ((x), (y))
-#define ldexp(x,y) __inline_ldexp ((x), (y))
-#define irint(x) __inline_irint (x)
-#define frexpf(x,y) __inline_frexpf ((x), (y))
-#define ldexpf(x,y) __inline_ldexpf ((x), (y))
-#define irintf(x) __inline_irintf (x)
-
-#if __convex_c2__ || __convex_c32__ || __convex_c34__ || __convex_c38__
-
-#define atan(x) __inline_atan (x)
-#define ceil(x) __inline_ceil (x)
-#define cos(x) __inline_cos (x)
-#define exp(x) __inline_exp (x)
-#define floor(x) __inline_floor (x)
-#define log(x) __inline_log (x)
-#define log10(x) __inline_log10 (x)
-#define modf(x,y) __inline_modf ((x), (y))
-#define rint(x) __inline_rint (x)
-#define sin(x) __inline_sin (x)
-#define sqrt(x) __inline_sqrt (x)
-
-#define atanf(x) __inline_atanf (x)
-#define ceilf(x) __inline_ceilf (x)
-#define cosf(x) __inline_cosf (x)
-#define expf(x) __inline_expf (x)
-#define floorf(x) __inline_floorf (x)
-#define logf(x) __inline_logf (x)
-#define log10f(x) __inline_log10f (x)
-#define modff(x,y) __inline_modff ((x), (y))
-#define rintf(x) __inline_rintf (x)
-#define sinf(x) __inline_sinf (x)
-#define sqrtf(x) __inline_sqrtf (x)
-
-#endif /* __convex_c[23*]__ */
-
-#endif /* __OPTIMIZE__ */
-
-static __inline__ __const__ double __inline_atan (double x)
-{
- double z;
- __asm__ ("atan.d %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ float __inline_atanf (float x)
-{
- float z;
- __asm__ ("atan.s %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ double __inline_cos (double x)
-{
- double z;
- __asm__ ("cos.d %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ float __inline_cosf (float x)
-{
- float z;
- __asm__ ("cos.s %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ double __inline_exp (double x)
-{
- double z;
- __asm__ ("exp.d %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ float __inline_expf (float x)
-{
- float z;
- __asm__ ("exp.s %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ double __inline_log (double x)
-{
- double z;
- __asm__ ("ln.d %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ float __inline_logf (float x)
-{
- float z;
- __asm__ ("ln.s %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ double __inline_sin (double x)
-{
- double z;
- __asm__ ("sin.d %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ float __inline_sinf (float x)
-{
- float z;
- __asm__ ("sin.s %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ double __inline_sqrt (double x)
-{
- double z;
- __asm__ ("sqrt.d %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ float __inline_sqrtf (float x)
-{
- float z;
- __asm__ ("sqrt.s %0" : "=d" (z) : "0" (x));
- return z;
-}
-
-static __inline__ __const__ double __inline_ceil (double x)
-{
- double z;
- __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x));
- if (z < x) z += 1.0;
- return z;
-}
-
-static __inline__ __const__ float __inline_ceilf (float x)
-{
- float z;
- __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x));
- if (z < x) z += 1.0F;
- return z;
-}
-
-static __inline__ __const__ double __inline_floor (double x)
-{
- double z;
- __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x));
- if (z > x) z -= 1.0;
- return z;
-}
-
-static __inline__ __const__ float __inline_floorf (float x)
-{
- float z;
- __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x));
- if (z > x) z -= 1.0F;
- return z;
-}
-
-static __inline__ __const__ double __inline_log10 (double x)
-{
- return 0.43429448190325182765 * __inline_log (x);
-}
-
-static __inline__ __const__ float __inline_log10f (float x)
-{
- return 0.43429448190325182765F * __inline_logf (x);
-}
-
-static __inline__ double __inline_modf (double x, double *np)
-{
- double intpart;
- __asm__ ("frint.d %1,%0" : "=d" (intpart) : "d" (x));
- *np = intpart;
- return x - intpart;
-}
-
-static __inline__ float __inline_modff (float x, float *np)
-{
- float intpart;
- __asm__ ("frint.s %1,%0" : "=d" (intpart) : "d" (x));
- *np = intpart;
- return x - intpart;
-}
-
-static __inline__ double __inline_frexp (double x, int *np)
-{
- union u { double d; unsigned long long ll; } u;
- if ((u.d = x) == 0)
- *np = 0;
- else
- {
-#if _IEEE_FLOAT_
- *np = ((u.ll >> 52) & 03777) - 01776;
- u.ll = (u.ll & 0x800fffffffffffffLL) | 0x3fe0000000000000LL;
-#else
- *np = ((u.ll >> 52) & 03777) - 02000;
- u.ll = (u.ll & 0x800fffffffffffffLL) | 0x4000000000000000LL;
-#endif
- }
- return u.d;
-}
-
-static __inline__ float __inline_frexpf (float x, int *np)
-{
- union u { float f; unsigned int i; } u;
- if ((u.f = x) == 0)
- *np = 0;
- else
- {
-#if _IEEE_FLOAT_
- *np = ((u.i >> 23) & 0377) - 0176;
- u.i = (u.i & 0x807fffff) | 0x3f000000;
-#else
- *np = ((u.i >> 23) & 0377) - 0200;
- u.i = (u.i & 0x807fffff) | 0x40000000;
-#endif
- }
- return u.f;
-}
-
-static __inline__ double __inline_ldexp (double x, int n)
-{
- extern int errno;
- union { double d; long long ll; unsigned sexp : 12; } u;
- if ((u.d = x) != 0)
- {
- int exp = n + (u.sexp & 03777);
- long long nn = (long long) n << 52;
-#if _IEEE_FLOAT_
- if (exp <= 0)
- u.ll &= 0x8000000000000000LL, errno = 34;
- else if (exp > 03776)
- u.ll = u.ll & 0x8000000000000000LL | 0x7fefffffffffffffLL, errno = 34;
-#else
- if (exp <= 0)
- u.ll = 0, errno = 34;
- else if (exp > 03777)
- u.ll |= 0x7fffffffffffffffLL, errno = 34;
-#endif
- else
- u.ll += nn;
- }
- return u.d;
-}
-
-static __inline__ float __inline_ldexpf (float x, int n)
-{
- extern int errno;
- union { float f; int i; unsigned sexp : 9; } u;
- if ((u.f = x) != 0)
- {
- int exp = n + (u.sexp & 0377);
- int nn = n << 23;
-#if _IEEE_FLOAT_
- if (exp <= 0)
- u.i &= 0x80000000, errno = 34;
- else if (exp > 0376)
- u.i = u.i & 0x80000000 | 0x7f7fffff, errno = 34;
-#else
- if (exp <= 0)
- u.i = 0, errno = 34;
- else if (exp > 0377)
- u.i |= 0x7fffffff, errno = 34;
-#endif
- else
- u.i += nn;
- }
- return u.f;
-}
-
-static __inline__ __const__ double __inline_rint (double x)
-{
- double z;
- union { double d; unsigned long long ll; } u;
- u.d = x;
-#if _IEEE_FLOAT_
- u.ll = (u.ll & 0x8000000000000000LL) | 0x3fe0000000000000LL;
-#else
- u.ll = (u.ll & 0x8000000000000000LL) | 0x4000000000000000LL;
-#endif
- __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x + u.d));
- return z;
-}
-
-static __inline__ __const__ float __inline_rintf (float x)
-{
- float z;
- union { float f; unsigned int i; } u;
- u.f = x;
-#if _IEEE_FLOAT_
- u.i = (u.i & 0x80000000) | 0x3f000000;
-#else
- u.i = (u.i & 0x80000000) | 0x40000000;
-#endif
- __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x + u.f));
- return z;
-}
-
-static __inline__ __const__ int __inline_irint (double x)
-{
- union { double d; unsigned long long ll; } u;
- u.d = x;
-#if _IEEE_FLOAT_
- u.ll = (u.ll & 0x8000000000000000LL) | 0x3fe0000000000000LL;
-#else
- u.ll = (u.ll & 0x8000000000000000LL) | 0x4000000000000000LL;
-#endif
- return x + u.d;
-}
-
-static __inline__ __const__ int __inline_irintf (float x)
-{
- union { float f; unsigned int i; } u;
- u.f = x;
-#if _IEEE_FLOAT_
- u.i = (u.i & 0x80000000) | 0x3f000000;
-#else
- u.i = (u.i & 0x80000000) | 0x40000000;
-#endif
- return x + u.f;
-}
-
-#endif /* _MATH_H */
-@//E*O*F include/math.h//
-chmod u=rw,g=rw,o=r include/math.h
-
-echo x - include/stddef.h
-sed 's/^@//' > "include/stddef.h" <<'@//E*O*F include/stddef.h//'
-#ifndef _STDDEF_H
-#define _STDDEF_H
-
-#ifndef __WCHAR_T
-#define __WCHAR_T
-
-#ifdef __GNUG__
-/* In C++, wchar_t is a distinct basic type,
- and we can expect __wchar_t to be defined by cc1plus. */
-typedef __wchar_t wchar_t;
-#else
-/* In C, cpp tells us which type to make an alias for. */
-typedef __WCHAR_TYPE__ wchar_t;
-#endif
-
-#endif /* __WCHAR_T */
-
- #include_next <stddef.h>
-
-#endif /* _STDDEF_H */
-@//E*O*F include/stddef.h//
-chmod u=rw,g=rw,o=r include/stddef.h
-
-echo x - include/stdlib.h
-sed 's/^@//' > "include/stdlib.h" <<'@//E*O*F include/stdlib.h//'
-#ifndef _STDLIB_H
-#define _STDLIB_H
-
-#if _CONVEX_SOURCE
-
-#define alloca __non_builtin_alloca
- #include_next <stdlib.h>
-#undef alloca
-
-#else
-
- #include_next <stdlib.h>
-
-#endif /* _CONVEX_SOURCE */
-
-#endif /* _STDLIB_H */
-@//E*O*F include/stdlib.h//
-chmod u=rw,g=rw,o=r include/stdlib.h
-
-exit 0
+++ /dev/null
-/* This header file is to avoid trouble with semi-ANSI header files
- on the Convex in system version 8.0. */
-
-#define _PROTO(list) ()
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Elxsi version.
- Copyright (C) 2000 Free Software Foundation, Inc.
- Contributed by Mike Stump <mrs@cygnus.com> in 1988. This is the first
- 64 bit port of GNU CC.
- Based upon the VAX port.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Functions used in the md file. */
-
-#ifdef RTX_CODE
-extern const char *cmp_set PARAMS ((const char *, const char *, rtx));
-extern const char *cmp_jmp PARAMS ((const char *, int, rtx));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-#endif /* RTX_CODE */
-
+++ /dev/null
-/* Subroutines for insn-output.c for GNU compiler. Elxsi version.
- Copyright (C) 1987, 1992, 1998, 1999, 2000 Free Software Foundation, Inc
- Contributrd by Mike Stump <mrs@cygnus.com> in 1988 and is the first
- 64 bit port of GNU CC.
- Based upon the VAX port.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "function.h"
-#include "output.h"
-#include "tree.h"
-#include "expr.h"
-#include "regs.h"
-#include "flags.h"
-#include "hard-reg-set.h"
-#include "tm_p.h"
-#include "target.h"
-#include "target-def.h"
-
-extern const char *reg_names[];
-rtx cmp_op0=0, cmp_op1=0;
-
-/* table of relations for compares and branches */
-static const char *const cmp_tab[] = {
- "gt", "gt", "eq", "eq", "ge", "ge", "lt", "lt", "ne", "ne",
- "le", "le" };
-
-static bool elxsi_assemble_integer PARAMS ((rtx, unsigned int, int));
-static void elxsi_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void elxsi_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_BYTE_OP
-#define TARGET_ASM_BYTE_OP NULL
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP NULL
-#undef TARGET_ASM_ALIGNED_SI_OP
-#define TARGET_ASM_ALIGNED_SI_OP NULL
-#undef TARGET_ASM_INTEGER
-#define TARGET_ASM_INTEGER elxsi_assemble_integer
-
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE elxsi_output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE elxsi_output_function_epilogue
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* Target hook for assembling integer objects. The ELXSI assembler
- syntax uses a suffix to indicate the size of data, so we can't use
- the usual string hooks. */
-
-static bool
-elxsi_assemble_integer (x, size, aligned_p)
- rtx x;
- unsigned int size;
- int aligned_p;
-{
- if (aligned_p)
- switch (size)
- {
- case 1:
- case 2:
- case 4:
- fputs ("\t.data\t", asm_out_file);
- output_addr_const (asm_out_file, x);
- fprintf (asm_out_file, "{%d}\n", size * BITS_PER_UNIT);
- return true;
- }
- return default_assemble_integer (x, size, aligned_p);
-}
-\f
-/* Generate the assembly code for function entry. FILE is a stdio
- stream to output the code to. SIZE is an int: how many units of
- temporary storage to allocate.
-
- Refer to the array `regs_ever_live' to determine which registers to
- save; `regs_ever_live[I]' is nonzero if register number I is ever
- used in the function. This function is responsible for knowing
- which registers should not be saved even if used. */
-
-static void
-elxsi_output_function_prologue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- register int regno;
- register int cnt = 0;
-
- /* the below two lines are a HACK, and should be deleted, but
- for now are very much needed (1.35) */
- if (frame_pointer_needed)
- regs_ever_live[14] = 1, call_used_regs[14] = 0;
-
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
- if (regs_ever_live[regno] && !call_used_regs[regno])
- cnt += 8;
-
- if (size + cnt)
- fprintf (file, "\tadd.64\t.sp,=%d\n", -size - cnt);
-
- cnt = 0;
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
- if (regs_ever_live[regno] && !call_used_regs[regno])
- fprintf (file, "\tst.64\t.r%d,[.sp]%d\n", regno, (cnt += 8) - 12);
-
- if (frame_pointer_needed)
- fprintf (file, "\tadd.64\t.r14,.sp,=%d\n", size + cnt);
-}
-
-/* This function generates the assembly code for function exit.
- Args are as for output_function_prologue ().
-
- The function epilogue should not depend on the current stack
- pointer! It should use the frame pointer only. This is mandatory
- because of alloca; we also take advantage of it to omit stack
- adjustments before returning. */
-
-static void
-elxsi_output_function_epilogue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- register int regno;
- register int cnt = 0;
-
- /* this conditional is ONLY here because there is a BUG;
- EXIT_IGNORE_STACK is ignored itself when the first part of
- the condition is true! (at least in version 1.35) */
- /* the 8*10 is for 64 bits of .r5 - .r14 */
- if (current_function_calls_alloca || size >= (256 - 8 * 10))
- {
- /* use .r4 as a temporary! Ok for now.... */
- fprintf (file, "\tld.64\t.r4,.r14\n");
-
- for (regno = FIRST_PSEUDO_REGISTER-1; regno >= 0; --regno)
- if (regs_ever_live[regno] && !call_used_regs[regno])
- cnt += 8;
-
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)
- if (regs_ever_live[regno] && !call_used_regs[regno])
- fprintf (file, "\tld.64\t.r%d,[.r14]%d\n", regno,
- -((cnt -= 8) + 8) - 4 - size);
-
- fprintf (file, "\tld.64\t.sp,.r4\n\texit\t0\n");
- }
- else
- {
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)
- if (regs_ever_live[regno] && !call_used_regs[regno])
- fprintf (file, "\tld.64\t.r%d,[.sp]%d\n", regno, (cnt += 8) - 12);
-
- fprintf (file, "\texit\t%d\n", size + cnt);
- }
-}
-
-/* type is the index into the above table */
-/* s is "" for signed, or "u" for unsigned */
-const char *
-cmp_jmp (s, type, where)
- const char *s;
- int type;
- rtx where;
-{
- rtx br_ops[3];
- char template[50];
- const char *f = "";
- const char *bits = "64";
- if (GET_MODE (cmp_op0) == SFmode) f = "f", bits = "32";
- if (GET_MODE (cmp_op0) == DFmode) f = "f";
- br_ops[0] = where;
- br_ops[1] = cmp_op0;
- br_ops[2] = cmp_op1;
- if (cmp_op1)
- sprintf(template, "%scmp%s.br.%s\t%%1,%%2:j%s\t%%l0",
- f, s, bits, cmp_tab[type]);
- else if (*f)
- sprintf(template, "fcmp.br.%s\t%%1,=0:j%s\t%%l0",
- bits, cmp_tab[type]);
- else if (*s) /* can turn the below in to a jmp ... */
- sprintf(template, "cmpu.br.64\t%%1,=0:j%s\t%%l0", s);
- else
- sprintf(template, "jmp.%s\t%%1,%%l0", cmp_tab[type+1]);
- output_asm_insn(template, br_ops);
- return "";
-}
-
-const char *
-cmp_set (s, type, reg)
- const char *s, *type;
- rtx reg;
-{
- rtx br_ops[3];
- char template[50];
- const char *f = "";
- const char *bits = "64";
- if (GET_MODE (cmp_op0) == SFmode) f = "f", bits = "32";
- else if (GET_MODE (cmp_op0) == DFmode) f = "f";
- else if (GET_MODE (cmp_op0) == SImode) bits = "32";
- else if (GET_MODE (cmp_op0) == HImode) bits = "16";
- else if (GET_MODE (cmp_op0) == QImode) bits = "8";
- br_ops[0] = reg;
- br_ops[1] = cmp_op0;
- br_ops[2] = cmp_op1;
- if (cmp_op1)
- sprintf(template, "%scmp%s.%s\t%%0,%%1,%%2:%s",
- f, s, bits, type);
- else
- sprintf(template, "%scmp%s.%s\t%%0,%%1,=0:%s",
- f, s, bits, type);
- output_asm_insn(template, br_ops);
- return "";
-}
-
-void
-print_operand_address (file, addr)
- FILE *file;
- register rtx addr;
-{
- register rtx reg1, reg2, breg, ireg;
- rtx offset;
-
- switch (GET_CODE (addr))
- {
-
- case MEM:
- if (GET_CODE (XEXP (addr, 0)) == REG)
- fprintf (file, "%s", reg_names[REGNO (addr)]);
- else abort();
- break;
-
- case REG:
- fprintf (file, "[%s]", reg_names[REGNO (addr)]);
- break;
-
- case PLUS:
- reg1 = 0; reg2 = 0;
- ireg = 0; breg = 0;
- offset = 0;
- if (GET_CODE (XEXP (addr, 0)) == REG)
- {
- offset = XEXP (addr, 1);
- addr = XEXP (addr, 0);
- }
- else if (GET_CODE (XEXP (addr, 1)) == REG)
- {
- offset = XEXP (addr, 0);
- addr = XEXP (addr, 1);
- }
- fprintf (file, "[%s]", reg_names[REGNO (addr)]);
- output_address (offset);
- break;
-
- default:
- output_addr_const (file, addr);
- }
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Elxsi version.
- Copyright (C) 1987, 1988, 1992, 1995, 1996, 1998, 1999, 2000, 2001, 2002
- Free Software Foundation, Inc.
- Contributed by Mike Stump <mrs@cygnus.com> in 1988. This is the first
- 64 bit port of GNU CC.
- Based upon the VAX port.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Delxsi -Dunix -Asystem=unix -Acpu=elxsi -Amachine=elxsi"
-
-/* Print subsidiary information on the compiler version in use. */
-
-#define TARGET_VERSION fprintf (stderr, " (elxsi)");
-
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags. */
-
-/* Nonzero if compiling code that Unix assembler can assemble. */
-#define TARGET_UNIX_ASM (target_flags & 1)
-
-
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
- { {"unix", 1, N_("Generate code the unix assembler can handle")}, \
- {"embos", -1, N_("Generate code an embedded assembler can handle")},\
- { "", TARGET_DEFAULT, NULL}}
-
-/* Default target_flags if no switches specified. */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-#endif
-\f
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields.
- This is not true on the VAX. */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is numbered. */
-#define WORDS_BIG_ENDIAN 1
-
-#define INT_TYPE_SIZE 32
-
-#define LONG_TYPE_SIZE 32
-
-#define LONG_LONG_TYPE_SIZE 64
-
-#define FLOAT_TYPE_SIZE 32
-
-#define DOUBLE_TYPE_SIZE 64
-
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 8
-
-/* Width in bits of a pointer.
- See also the macro `Pmode' defined below. */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing pointers in memory. */
-#define POINTER_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 8
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 8
-
-/* Every structure's size must be a multiple of this. */
-#define STRUCTURE_SIZE_BOUNDARY 32
-
-/* A bitfield declared as `int' forces `int' alignment for the struct. */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this. */
-#define BIGGEST_ALIGNMENT 32
-
-/* Define this if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 0
-\f
-/* Standard register usage. */
-
-/* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
- On the elxsi, these is the .r15 (aka .sp). */
-#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like. */
-#define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers.
- On the VAX, all registers are one word long. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) 1
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED 0
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
-{ int regno; \
- int offset = 0; \
- for( regno=0; regno < FIRST_PSEUDO_REGISTER; regno++ ) \
- if( regs_ever_live[regno] && !call_used_regs[regno] ) \
- offset += 8; \
- (DEPTH) = (offset + ((get_frame_size() + 3) & ~3) ); \
- (DEPTH) = 0; \
-}
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 14
-
-/* Register in which static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM 0
-
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM 1
-\f
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
-/* The VAX has only one kind of registers, so NO_REGS and ALL_REGS
- are the only classes. */
-
-enum reg_class { NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file. */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. */
-
-#define REG_CLASS_CONTENTS {{0}, {0x07fff}, {0xffff}}
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-#define REGNO_REG_CLASS(REGNO) (REGNO == 15 ? ALL_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) NO_REGS
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C. */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? (VALUE) >=-16 && (VALUE) <=15 : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS. */
-/* On the VAX, this is always the size of MODE in words,
- since all registers are the same size. */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-\f
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- that is, each additional local variable allocated
- goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated. */
-#define STARTING_FRAME_OFFSET -4
-
-/* Offset of first parameter from the argument pointer register value. */
-#define FIRST_PARM_OFFSET(FNDECL) 4
-
-/* Value is 1 if returning from a function call automatically
- pops the arguments described by the number-of-args field in the call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
-
- On the VAX, the RET insn always pops all the args for any function. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-/* On the VAX the return value is in R0 regardless. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-/* On the VAX the return value is in R0 regardless. */
-
-#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
-
-/* Define this if PCC uses the nonreentrant convention for returning
- structure and union values. */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for a function value.
- On the VAX, R0 is the only register thus used. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* 1 if N is a possible register number for function argument passing.
- On the VAX, no registers are used in this way. */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-\f
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go.
-
- On the VAX, this is a single integer, which is a number of bytes
- of arguments scanned so far. */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0.
-
- On the VAX, the offset starts at 0. */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,x,INDIRECT) \
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.) */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- ((CUM) += ((MODE) != BLKmode \
- ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
- : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis). */
-
-/* On the VAX all args are pushed. */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tld.64\t.r0,.LP%d\n\tcall\tmcount\n", (LABELNO));
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 0
-
-/* If the memory address ADDR is relative to the frame pointer,
- correct it to be relative to the stack pointer instead.
- This is for when we don't use a frame pointer.
- ADDR should be a variable name. */
-
-#define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
-{ int offset = -1; \
- rtx regs = stack_pointer_rtx; \
- if (ADDR == frame_pointer_rtx) \
- offset = 0; \
- else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx \
- && GET_CODE (XEXP (ADDR, 0)) == CONST_INT) \
- offset = INTVAL (XEXP (ADDR, 0)); \
- else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
- && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
- offset = INTVAL (XEXP (ADDR, 1)); \
- else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
- { rtx other_reg = XEXP (ADDR, 1); \
- offset = 0; \
- regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
- else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
- { rtx other_reg = XEXP (ADDR, 0); \
- offset = 0; \
- regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
- if (offset >= 0) \
- { int regno; \
- extern char call_used_regs[]; \
- offset += 4; /* I don't know why??? */ \
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
- if (regs_ever_live[regno] && ! call_used_regs[regno]) \
- offset += 8; \
- ADDR = plus_constant (regs, offset + (DEPTH)); } }
-
-\f
-/* Addressing modes, and classification of registers for them. */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
-
-#define REGNO_OK_FOR_INDEX_P(regno) \
-((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-#define REGNO_OK_FOR_BASE_P(regno) \
-((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-\f
-/* Maximum number of registers that can appear in a valid memory address. */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* 1 if X is an rtx for a constant that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-
-#define LEGITIMATE_CONSTANT_P(X) \
- (GET_CODE (X) != CONST_DOUBLE)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) 1
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) 1
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- CONSTANT_ADDRESS_P is actually machine-independent. */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ \
- if (GET_CODE (X) == REG) goto ADDR; \
- if (CONSTANT_ADDRESS_P (X)) goto ADDR; \
- if (GET_CODE (X) == PLUS) \
- { \
- /* Handle [index]<address> represented with index-sum outermost */\
- if (GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
- && GET_CODE (XEXP (X, 1)) == CONST_INT) \
- goto ADDR; \
- if (GET_CODE (XEXP (X, 1)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
- && GET_CODE (XEXP (X, 0)) == CONST_INT) \
- goto ADDR; \
- } \
- }
-
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output.
-
- For the VAX, nothing needs to be done. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for. */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-\f
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this as 1 if `char' should by default be signed; else as 0. */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
- also convert validly to an unsigned one. */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
- in one reasonably fast instruction. */
-#define MOVE_MAX 8
-
-/* Nonzero if access to memory by bytes is slow and undesirable. */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
- which implies one can omit a sign-extension or zero-extension
- of a shift count. */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
- After generation of rtl, the compiler makes no further distinction
- between pointers and any other objects of this machine mode. */
-#define Pmode SImode
-
-/* A function address in a call instruction
- is a byte address (for indexing purposes)
- so give the MEM rtx a byte's mode. */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST_INT: \
- /* Constant zero is super cheap due to clr instruction. */ \
- if (RTX == const0_rtx) return 0; \
- if ((unsigned) INTVAL (RTX) < 077) return 1; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 3; \
- case CONST_DOUBLE: \
- return 5;
-
-/*
- * We can use the BSD C library routines for the gnulib calls that are
- * still generated, since that's what they boil down to anyways.
- */
-
-/* #define UDIVSI3_LIBCALL "*udiv" */
-/* #define UMODSI3_LIBCALL "*urem" */
-\f
-/* Tell final.c how to eliminate redundant test instructions. */
-
-/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). No extra ones are needed for the VAX. */
-
-/* Store in cc_status the expressions
- that the condition codes will describe
- after execution of an instruction whose pattern is EXP.
- Do not alter them if the instruction would not alter the cc's. */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
- CC_STATUS_INIT;
-
-\f
-/* Control the assembler format that we output. */
-
-/* Output the name of the file we are compiling. */
-#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
- do { fprintf (STREAM, "\t.file\t"); \
- output_quoted_string (STREAM, NAME); \
- fprintf (STREAM, "\n"); \
- } while (0)
-
-/* Output at beginning of assembler file. */
-#define ASM_FILE_START(FILE) fputs ("", (FILE));
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#define ASM_APP_OFF ""
-
-/* Output before read-only data. */
-
-#define TEXT_SECTION_ASM_OP "\t.inst"
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP "\t.var"
-
-/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
-
-#define REGISTER_NAMES \
-{".r0", ".r1", ".r2", ".r3", ".r4", ".r5", ".r6", ".r7", ".r8", \
- ".r9", ".r10", ".r11", ".r12", ".r13", ".r14", ".sp"}
-
-/* This is BSD, so it wants DBX format. */
-
-/* #define DBX_DEBUGGING_INFO */
-
-/* Do not break .stabs pseudos into continuations. */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
- continuation back on). */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't use the `xsfoo;' construct in DBX output; this system
- doesn't support it. */
-
-#define DBX_NO_XREFS
-
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
- do { fputs ("\t.extdef\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, ".%s%d", PREFIX, NUM)
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tsubi.64\t4,.sp\n\tst.32\t%s,[.sp]\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tld.32\t%s,[.sp]\n\taddi.64\t4,.sp\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.
- (The VAX does not use such vectors,
- but we must define this macro anyway.) */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- fprintf (FILE, "\t.data .L%d{32}\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative. */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\t.data .L%d-.L%d{32}\n", VALUE, REL)
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- do { if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); } while (0)
-
-/* This is how to output an assembler line
- that says to advance the location counter by SIZE bytes. */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (ROUNDED)))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".bss ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d,%d\n", (SIZE),(ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Print an instruction operand X on file FILE.
- CODE is the code from the %-spec that requested printing this operand;
- if `%z3' was used to print operand 3, then CODE is 'z'. */
-
-#define PRINT_OPERAND(FILE, X, CODE) \
-{ \
- if (CODE == 'r' && GET_CODE (X) == MEM && GET_CODE (XEXP (X, 0)) == REG) \
- fprintf (FILE, "%s", reg_names[REGNO (XEXP (X, 0))]); \
- else if (GET_CODE (X) == REG) \
- fprintf (FILE, "%s", reg_names[REGNO (X)]); \
- else if (GET_CODE (X) == MEM) \
- output_address (XEXP (X, 0)); \
- else \
- { \
- /*debug_rtx(X);*/ \
- putc ('=', FILE); \
- output_addr_const (FILE, X); } \
- }
-
-/* Print a memory operand whose address is X, on file FILE.
- This uses a function in output-vax.c. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
- print_operand_address (FILE, ADDR)
-
-/* These are stubs, and have yet to bee written. */
-
-#define TRAMPOLINE_SIZE 26
-#define TRAMPOLINE_TEMPLATE(FILE)
-#define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT)
+++ /dev/null
-;;- Machine description for GNU compiler, Elxsi Version
-;; Copyright (C) 1987, 1988, 1992, 1994, 2000 Free Software Foundation, Inc.
-;; Contributed by Mike Stump <mrs@cygnus.com> in 1988, and is the first
-;; 64 bit port of GNU CC.
-;; Based upon the VAX port.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- Instruction patterns. When multiple patterns apply,
-;;- the first one in the file is chosen.
-;;-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-
-(define_insn ""
- [(set (reg:SI 15)
- (plus:SI (reg:SI 15)
- (match_operand:SI 0 "general_operand" "g")))]
- ""
- "add.64\\t.sp,%0")
-
-(define_insn ""
- [(set (reg:SI 15)
- (plus:SI (match_operand:SI 0 "general_operand" "g")
- (reg:SI 15)))]
- ""
- "add.64\\t.sp,%0")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI (reg:SI 15)
- (match_operand:SI 1 "general_operand" "g")))]
- ""
- "ld.32\\t%0,.sp\;add.64\\t%0,%1")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI (match_operand:SI 1 "general_operand" "g")
- (reg:SI 15)))]
- ""
- "ld.32\\t%0,.sp\;add.64\\t%0,%1")
-
-(define_insn ""
- [(set (reg:SI 15)
- (minus:SI (reg:SI 15)
- (match_operand:SI 0 "general_operand" "g")))]
- ""
- "sub.64\\t.sp,%0")
-
-(define_insn ""
- [(set (reg:SI 15)
- (match_operand:SI 0 "general_operand" "rm"))]
- ""
- "ld.32\\t.sp,%0")
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=m,r")
- (reg:SI 15))]
- ""
- "@
- st.32\\t.sp,%0
- ld.32\\t%0,.sp")
-
-; tstdi is first test insn so that it is the one to match
-; a constant argument.
-
-(define_insn "tstdi"
- [(set (cc0)
- (match_operand:DI 0 "register_operand" "r"))]
- ""
- "*
- extern rtx cmp_op0, cmp_op1;
- cmp_op0=operands[0]; cmp_op1=0;
- return \";\\ttstdi\\t%0\";
-")
-
-(define_insn "tstdf"
- [(set (cc0)
- (match_operand:DF 0 "register_operand" "r"))]
- ""
- "*
- extern rtx cmp_op0, cmp_op1;
- cmp_op0=operands[0]; cmp_op1=0;
- return \";\\ttstdf\\t%0\";
-")
-
-(define_insn "tstsf"
- [(set (cc0)
- (match_operand:SF 0 "register_operand" "r"))]
- ""
- "*
- extern rtx cmp_op0, cmp_op1;
- cmp_op0=operands[0]; cmp_op1=0;
- return \";\\ttstsf\\t%0\";
-")
-
-(define_insn "cmpdi"
- [(set (cc0)
- (compare (match_operand:DI 0 "register_operand" "r")
- (match_operand:DI 1 "general_operand" "rm")))]
- ""
- "*
- extern rtx cmp_op0, cmp_op1;
- cmp_op0=operands[0]; cmp_op1=operands[1];
- return \";\\tcmpdi\\t%0,%1\";
-")
-
-(define_insn "cmpdf"
- [(set (cc0)
- (compare (match_operand:DF 0 "register_operand" "r")
- (match_operand:DF 1 "general_operand" "rm")))]
- ""
- "*
- extern rtx cmp_op0, cmp_op1;
- cmp_op0=operands[0]; cmp_op1=operands[1];
- return \";\\tcmpdf\\t%0,%1\";
-")
-
-(define_insn "cmpsf"
- [(set (cc0)
- (compare (match_operand:SF 0 "register_operand" "r")
- (match_operand:SF 1 "general_operand" "rm")))]
- ""
- "*
- extern rtx cmp_op0, cmp_op1;
- cmp_op0=operands[0]; cmp_op1=operands[1];
- return \";\\tcmpsf\\t%0,%1\";
-")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (eq (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmp.64\\t%0,%1,%2:eq")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ne (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmp.64\\t%0,%1,%2:ne")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (le (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmp.64\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (leu (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmpu.64\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (lt (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmp.64\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ltu (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmpu.64\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ge (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmp.64\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (geu (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmpu.64\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (gt (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmp.64\\t%0,%1,%2:gt")
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (gtu (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "general_operand" "g")))]
- ""
- "cmpu.64\\t%0,%1,%2:gt")
-
-(define_insn "seq"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (eq (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"\", \"eq\", operands[0]); ")
-
-(define_insn "sne"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ne (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"\", \"ne\", operands[0]); ")
-
-(define_insn "sle"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (le (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"\", \"le\", operands[0]); ")
-
-(define_insn "sleu"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (leu (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"u\", \"le\", operands[0]); ")
-
-(define_insn "slt"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (lt (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"\", \"lt\", operands[0]); ")
-
-(define_insn "sltu"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ltu (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"u\", \"lt\", operands[0]); ")
-
-(define_insn "sge"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ge (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"\", \"ge\", operands[0]); ")
-
-(define_insn "sgeu"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (geu (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"u\", \"ge\", operands[0]); ")
-
-(define_insn "sgt"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (gt (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"\", \"gt\", operands[0]); ")
-
-(define_insn "sgtu"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (gtu (cc0) (const_int 0)))]
- ""
- "* return cmp_set(\"u\", \"gt\", operands[0]); ")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (eq (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmp.32\\t%0,%1,%2:eq")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ne (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmp.32\\t%0,%1,%2:ne")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (le (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmp.32\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (leu (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmpu.32\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (lt (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmp.32\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ltu (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmpu.32\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ge (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmp.32\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (geu (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmpu.32\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (gt (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmp.32\\t%0,%1,%2:gt")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (gtu (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "m")))]
- ""
- "cmpu.32\\t%0,%1,%2:gt")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (eq (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmp.16\\t%0,%1,%2:eq")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ne (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmp.16\\t%0,%1,%2:ne")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (le (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmp.16\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (leu (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmpu.16\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (lt (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmp.16\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ltu (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmpu.16\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ge (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmp.16\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (geu (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmpu.16\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (gt (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmp.16\\t%0,%1,%2:gt")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (gtu (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "general_operand" "m")))]
- ""
- "cmpu.16\\t%0,%1,%2:gt")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (eq (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmp.8\\t%0,%1,%2:eq")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ne (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmp.8\\t%0,%1,%2:ne")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (le (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmp.8\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (leu (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmpu.8\\t%0,%1,%2:le")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (lt (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmp.8\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ltu (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmpu.8\\t%0,%1,%2:lt")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ge (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmp.8\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (geu (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmpu.8\\t%0,%1,%2:ge")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (gt (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmp.8\\t%0,%1,%2:gt")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (gtu (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "general_operand" "m")))]
- ""
- "cmpu.8\\t%0,%1,%2:gt")
-
-\f
-
-(define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=r,m")
- (match_operand:DF 1 "general_operand" "rm,r"))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.64\\t%0,%1\";
- return \"st.64\\t%1,%0\";
-}")
-
-(define_insn "movsf"
- [(set (match_operand:SF 0 "general_operand" "=r,m")
- (match_operand:SF 1 "general_operand" "rm,r"))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.32\\t%0,%1\";
- return \"st.32\\t%1,%0\";
-}")
-
-(define_insn "movdi"
- [(set (match_operand:DI 0 "general_operand" "=r,m,rm")
- (match_operand:DI 1 "general_operand" "g,r,I"))]
- ""
- "*
- if (which_alternative == 0)
- return \"ld.64\\t%0,%1\";
- else if (which_alternative == 1)
- return \"st.64\\t%1,%0\";
- else
- if (GET_CODE(operands[1])==CONST_INT) {
- if (INTVAL(operands[1]) >= 0)
- return \"sti.64\\t%c1,%0\";
- else
- return \"stin.64\\t%n1,%0\";
- }
- else
- abort();
-")
-
-(define_insn "movsi"
- [(set (match_operand:SI 0 "general_operand" "=r,m,r")
- (match_operand:SI 1 "general_operand" "rm,rI,i"))]
- ""
- "*
- if (which_alternative == 0)
- return \"ld.32\\t%0,%1\";
- else if (which_alternative == 1) {
- if (GET_CODE(operands[1])==CONST_INT) {
- if (INTVAL(operands[1]) >= 0)
- return \"sti.32\\t%c1,%0\";
- else
- return \"stin.32\\t%n1,%0\";
- }
- return \"st.32\\t%1,%0\";
- } else
- return \"ld.64\\t%0,%1 ; I only want 32\";
-")
-
-(define_insn "movhi"
- [(set (match_operand:HI 0 "general_operand" "=r,m,r")
- (match_operand:HI 1 "general_operand" "m,rI,ri"))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.16\\t%0,%1\";
- if (which_alternative == 2)
- return \"ld.64\\t%0,%1\\t; I only want 16\";
- if (GET_CODE(operands[1])==CONST_INT) {
- if (INTVAL(operands[1]) >= 0)
- return \"sti.16\\t%c1,%0\";
- else
- return \"stin.16\\t%n1,%0\";
- }
- return \"st.16\\t%1,%0\";
-}")
-
-(define_insn "movqi"
- [(set (match_operand:QI 0 "general_operand" "=r,m,r")
- (match_operand:QI 1 "general_operand" "m,rI,ri"))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.8\\t%0,%1\";
- if (which_alternative == 2)
- return \"ld.64\\t%0,%1\\t; I only want 8\";
- if (GET_CODE(operands[1])==CONST_INT) {
- if (INTVAL(operands[1]) >= 0)
- return \"sti.8\\t%c1,%0\";
- else
- return \"stin.8\\t%n1,%0\";
- }
- return \"st.8\\t%1,%0\";
-}")
-\f
-;; Extension and truncation insns.
-;; Those for integer source operand
-;; are ordered widest source type first.
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (truncate:SF (match_operand:DF 1 "general_operand" "rm")))]
- ""
- "cvt.ds\\t%0,%1")
-
-(define_insn "truncdiqi2"
- [(set (match_operand:QI 0 "general_operand" "=r,m,r")
- (truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.8\\t%0,%1\";
- else if (which_alternative == 1)
- return \"st.8\\t%1,%0\";
- return \"\";
-}")
-
-(define_insn "truncdihi2"
- [(set (match_operand:HI 0 "general_operand" "=r,m,r")
- (truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.16\\t%0,%1\";
- if (which_alternative == 1)
- return \"st.16\\t%1,%0\";
- return \"\";
-}")
-
-(define_insn "truncdisi2"
- [(set (match_operand:SI 0 "general_operand" "=r,m")
- (truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.32\\t%0,%1\";
- return \"st.32\\t%1,%0\";
-}")
-
-(define_insn "truncsiqi2"
- [(set (match_operand:QI 0 "general_operand" "=r,m,r")
- (truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.8\\t%0,%1\";
- if (which_alternative == 1)
- return \"st.8\\t%1,%0\";
- return \"\";
-}")
-
-(define_insn "truncsihi2"
- [(set (match_operand:HI 0 "general_operand" "=r,m,r")
- (truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.16\\t%0,%1\";
- if (which_alternative == 1)
- return \"st.16\\t%1,%0\";
- return \"\";
-}")
-
-(define_insn "trunchiqi2"
- [(set (match_operand:QI 0 "general_operand" "=r,m,r")
- (truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))]
- ""
- "*
-{
- if (which_alternative == 0)
- return \"ld.8\\t%0,%1\";
- if (which_alternative == 1)
- return \"st.8\\t%1,%0\";
- return \"\";
-}")
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))]
- ""
- "cvt.sd\\t%0,%1")
-
-(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
- ""
- "ld.32\\t%0,%1")
-
-(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ld.16\\t%0,%1\";
- return \"extract\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ld.16\\t%0,%1\";
- return \"extract\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ld.8\\t%0,%1\";
- return \"extract\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ld.8\\t%0,%1\";
- return \"extract\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ld.8\\t%0,%1\";
- return \"extract\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "zero_extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
- ""
- "ldz.32\\t%0,%1")
-
-
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ldz.16\\t%0,%1\";
- return \"extractz\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ldz.16\\t%0,%1\";
- return \"extractz\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ldz.8\\t%0,%1\";
- return \"extractz\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ldz.8\\t%0,%1\";
- return \"extractz\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative==0)
- return \"ldz.8\\t%0,%1\";
- return \"extractz\\t%0,%1:bit 56,8\";
-")
-
-\f
-(define_insn "ashrdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "rn")))]
- ""
- "sra\\t%0,%1,%2")
-
-(define_insn "lshrdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "rn")))]
- ""
- "srl\\t%0,%1,%2")
-
-(define_insn "ashldi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ashift:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:SI 2 "general_operand" "rn")))]
- ""
- "sla\\t%0,%1,%2")
-
-(define_insn "anddi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (and:DI (match_operand:DI 1 "general_operand" "%0,r")
- (match_operand:DI 2 "general_operand" "g,g")))]
- "1 /*which_alternative == 0 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"and\\t%0,%2\";
- return \"and\\t%0,%1,%2\";
-")
-
-(define_insn "iordi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (ior:DI (match_operand:DI 1 "general_operand" "%0,r")
- (match_operand:DI 2 "general_operand" "g,g")))]
- "1 /*which_alternative == 0 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"or\\t%0,%2\";
- return \"or\\t%0,%1,%2\";
-")
-
-(define_insn "xordi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (xor:DI (match_operand:DI 1 "general_operand" "%0,r")
- (match_operand:DI 2 "general_operand" "g,g")))]
- "1 /*which_alternative == 0 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"xor\\t%0,%2\";
- return \"xor\\t%0,%1,%2\";
-")
-
-(define_insn "one_cmpldi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (not:DI (match_operand:DI 1 "general_operand" "rm")))]
- ""
- "not\\t%0,%1")
-
-;; gcc 2.1 does not widen ~si into ~di.
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (not:SI (match_operand:SI 1 "register_operand" "r")))]
- ""
- "not\\t%0,%1")
-
-(define_insn "negdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (neg:DI (match_operand:DI 1 "general_operand" "rm")))]
- ""
- "neg.64\\t%0,%1")
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (neg:SI (match_operand:SI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative == 0)
- return \"neg.32\\t%0,%1\";
- return \"neg.64\\t%0,%1 ; I only want 32\";
-")
-
-(define_insn "neghi2"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (neg:HI (match_operand:HI 1 "general_operand" "m,r")))]
- ""
- "*
- if (which_alternative == 0)
- return \"neg.16\\t%0,%1\";
- return \"neg.64\\t%0,%1 ; I only want 16\";
-")
-
-(define_insn "adddf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (plus:DF (match_operand:DF 1 "general_operand" "%0")
- (match_operand:DF 2 "general_operand" "rm")))]
- ""
- "fadd.64\\t%0,%2")
-
-(define_insn "addsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (plus:SF (match_operand:SF 1 "general_operand" "%0")
- (match_operand:SF 2 "general_operand" "rm")))]
- ""
- "fadd.32\\t%0,%2")
-
-;; There is also an addi.64 4,.r0'' optimization
-(define_insn "adddi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (plus:DI (match_operand:DI 1 "general_operand" "%0,r")
- (match_operand:DI 2 "general_operand" "g,g")))]
- "1 /*which_alternative == 0 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"add.64\\t%0,%2\";
- return \"add.64\\t%0,%1,%2\";
-")
-
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (plus:SI (match_operand:SI 1 "general_operand" "%0,r,0")
- (match_operand:SI 2 "general_operand" "m,m,g")))]
- "1 /*which_alternative != 1 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"add.32\\t%0,%2\";
- if (which_alternative == 1)
- return \"add.32\\t%0,%1,%2\";
- return \"add.64\\t%0,%2 ; I only want 32\";
-")
-
-(define_insn "addhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r")
- (plus:HI (match_operand:HI 1 "general_operand" "%0,r,0")
- (match_operand:HI 2 "general_operand" "m,m,g")))]
- "1 /*which_alternative != 1 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"add.16\\t%0,%2\";
- if (which_alternative == 1)
- return \"add.16\\t%0,%1,%2\";
- return \"add.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "subdf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (match_operand:DF 1 "general_operand" "0")
- (match_operand:DF 2 "general_operand" "rm")))]
- ""
- "fsub.64\\t%0,%2")
-
-(define_insn "subsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (minus:SF (match_operand:SF 1 "general_operand" "0")
- (match_operand:SF 2 "general_operand" "rm")))]
- ""
- "fsub.32\\t%0,%2")
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (minus:DI (match_operand:DI 1 "general_operand" "0,g,r")
- (match_operand:DI 2 "general_operand" "g,r,g")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
- if (which_alternative == 0)
- return \"sub.64\\t%0,%2\";
- else if (which_alternative == 1)
- return \"subr.64\\t%0,%2,%1\";
- else
- return \"sub.64\\t%0,%1,%2\";
-")
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
- (minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
- (match_operand:SI 2 "general_operand" "m,r,m,g")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
- if (which_alternative == 0)
- return \"sub.32\\t%0,%2\";
- else if (which_alternative == 1)
- return \"subr.32\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"sub.32\\t%0,%1,%2\";
- else
- return \"sub.64\\t%0,%2 ; I only want 32\";
-")
-
-(define_insn "subhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
- (minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0")
- (match_operand:HI 2 "general_operand" "m,r,m,g")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
- if (which_alternative == 0)
- return \"sub.16\\t%0,%2\";
- else if (which_alternative == 1)
- return \"subr.16\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"sub.16\\t%0,%1,%2\";
- else
- return \"sub.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (match_operand:DF 1 "general_operand" "%0")
- (match_operand:DF 2 "general_operand" "rm")))]
- ""
- "fmul.64\\t%0,%2")
-
-(define_insn "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (mult:SF (match_operand:SF 1 "general_operand" "%0")
- (match_operand:SF 2 "general_operand" "rm")))]
- ""
- "fmul.32\\t%0,%2")
-
-(define_insn "muldi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (mult:DI (match_operand:DI 1 "general_operand" "%0,r")
- (match_operand:DI 2 "general_operand" "g,g")))]
- "1 /*which_alternative == 0 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"mul.64\\t%0,%2\";
- return \"mul.64\\t%0,%1,%2\";
-")
-
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (mult:SI (match_operand:SI 1 "general_operand" "%0,r,0")
- (match_operand:SI 2 "general_operand" "m,m,g")))]
- "1 /*which_alternative == 0 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"mul.32\\t%0,%2\";
- else if (which_alternative == 1)
- return \"mul.32\\t%0,%1,%2\";
- else
- return \"mul.64\\t%0,%2 ; I only want 32\";
-")
-
-(define_insn "mulhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r")
- (mult:HI (match_operand:HI 1 "general_operand" "%0,r,0")
- (match_operand:HI 2 "general_operand" "m,m,g")))]
- "1 /*which_alternative == 0 || check356(operands[2])*/"
- "*
- if (which_alternative == 0)
- return \"mul.16\\t%0,%2\";
- else if (which_alternative == 1)
- return \"mul.16\\t%0,%1,%2\";
- else
- return \"mul.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (div:DF (match_operand:DF 1 "general_operand" "0")
- (match_operand:DF 2 "general_operand" "rm")))]
- ""
- "fdiv.64\\t%0,%2")
-
-(define_insn "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (div:SF (match_operand:SF 1 "general_operand" "0")
- (match_operand:SF 2 "general_operand" "rm")))]
- ""
- "fdiv.32\\t%0,%2")
-
-(define_insn "divdi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (div:DI (match_operand:DI 1 "general_operand" "0,g,r")
- (match_operand:DI 2 "general_operand" "g,r,g")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
- if (which_alternative == 0)
- return \"div.64\\t%0,%2\";
- else if (which_alternative == 1)
- return \"divr.64\\t%0,%2,%1\";
- else
- return \"div.64\\t%0,%1,%2\";
-")
-
-(define_insn "divsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
- (div:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
- (match_operand:SI 2 "general_operand" "m,r,m,g")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
-/* We don't ignore high bits. */
-if (0) {
- if (which_alternative == 0)
- return \"div.32\\t%0,%2\";
- else if (which_alternative == 1)
- return \"divr.32\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"div.32\\t%0,%1,%2\";
- else
- return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
-} else {
- if (which_alternative == 0)
- return \"ld.32\\t%0,%0\;div.32\\t%0,%2\";
- else if (which_alternative == 1)
- return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\";
- else
- return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
-}
-")
-
-(define_insn "divhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
- (div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
- (match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
- if (which_alternative == 0)
- return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\";
- else if (which_alternative == 1)
- return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\";
- else if (which_alternative == 3)
- return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
- else
- return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "modhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
- (mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
- (match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
- if (which_alternative == 0)
- return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\";
- else if (which_alternative == 1)
- return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\";
- else if (which_alternative == 3)
- return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
- else
- return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "moddi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (mod:DI (match_operand:DI 1 "general_operand" "0,g,r")
- (match_operand:DI 2 "general_operand" "g,r,g")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
- if (which_alternative == 0)
- return \"rem.64\\t%0,%2\";
- else if (which_alternative == 1)
- return \"remr.64\\t%0,%2,%1\";
- else
- return \"rem.64\\t%0,%1,%2\";
-")
-
-(define_insn "modsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
- (mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
- (match_operand:SI 2 "general_operand" "m,r,m,g")))]
- "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
- "*
-/* There is a micro code bug with the below... */
-if (0) {
- if (which_alternative == 0)
- return \"rem.32\\t%0,%2\";
- else if (which_alternative == 1)
- return \"remr.32\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"rem.32\\t%0,%1,%2\";
- else
- return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
-} else {
- if (which_alternative == 0)
- return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\";
- else if (which_alternative == 1)
- return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\";
- else if (which_alternative == 2)
- return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\";
- else
- return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
-}
-")
-
-\f
-(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
- ""
- "jmp\\t%l0")
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
- ""
-;; Maybe %l0 is better, maybe we can relax register only.
- "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0")
-
-(define_insn "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"\", 2, operands[0]); ")
-
-(define_insn "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"\", 8, operands[0]); ")
-
-(define_insn "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"\", 0, operands[0]); ")
-
-(define_insn "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"u\", 0, operands[0]); ")
-
-(define_insn "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"\", 6, operands[0]); ")
-
-(define_insn "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"u\", 6, operands[0]); ")
-
-(define_insn "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"\", 4, operands[0]); ")
-
-(define_insn "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"u\", 4, operands[0]); ")
-
-(define_insn "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"\", 10, operands[0]); ")
-
-(define_insn "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "* return cmp_jmp(\"u\", 10, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"\", 8, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"\", 2, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"\", 10, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"u\", 10, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"\", 4, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"u\", 4, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"\", 6, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"u\", 6, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"\", 0, operands[0]); ")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "* return cmp_jmp(\"u\", 0, operands[0]); ")
-
-;; Note that operand 1 is total size of args, in bytes,
-;; and what the call insn wants is the number of words.
-(define_insn "call"
- [(call (match_operand:QI 0 "general_operand" "m")
- (match_operand:QI 1 "general_operand" "g"))]
- ""
- "*
- if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG)
- if (REGNO (XEXP (operands[0], 0)) != 0)
- return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
- else
- return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
- else
- return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
- ")
-
-(define_insn "call_value"
- [(set (match_operand 0 "" "")
- (call (match_operand:QI 1 "general_operand" "m")
- (match_operand:QI 2 "general_operand" "g")))]
- ""
- "*
- if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG)
- if (REGNO (XEXP (operands[1], 0)) != 0)
- return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
- else
- return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
- else
- return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
- ")
-
-(define_insn "tablejump"
- [(set (pc) (match_operand:SI 0 "register_operand" "r"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
- "br.reg\\t%0")
-
-(define_insn "nop"
- [(const_int 0)]
- ""
- "nop")
+++ /dev/null
-/* Configuration for an i386 running 386BSD as the target machine. */
-
-#define TARGET_VERSION fprintf (stderr, " (80386, BSD syntax)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -D____386BSD____ -D__386BSD__ -DBSD_NET2 -Asystem=unix -Asystem=bsd"
-
-/* Like the default, except no -lg. */
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-/* Redefine this to use %eax instead of %edx. */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-{ \
- if (flag_pic) \
- { \
- fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n", \
- LPREFIX, (LABELNO)); \
- fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \
- } \
- else \
- { \
- fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO)); \
- fprintf (FILE, "\tcall mcount\n"); \
- } \
-}
-
-#undef ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
- we want to retain compatibility with older gcc versions. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
+++ /dev/null
-/* Definitions for IBM PS2 running AIX/386 with gas.
- From: Minh Tran-Le <TRANLE@intellicorp.com>
- Copyright (C) 1988, 2000 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/*
- * This configuration file is for gcc with gas-2.x and gnu ld 2.x
- * with aix ps/2 1.3.x.
- */
-
-/* Define USE_GAS if you have the new version of gas that can handle
- * multiple segments and .section pseudo op. This will allow gcc to
- * use the .init section for g++ ctor/dtor.
- *
- * If you don't have gas then undefined USE_GAS. You will also have
- * to use collect if you want to use g++
- */
-#define USE_GAS
-
-#include "i386/aix386ng.h"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.
- And add crtbegin.o and crtend.o for ctors and dtors */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s"
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
- "crtend.o%s crtn.o%s"
-
-/* Removed the -K flags because the gnu ld does not handle it */
-#undef LINK_SPEC
-#define LINK_SPEC "%{T*} %{z:-lm}"
-
-/* Define a few machine-specific details of the implementation of
- constructors. */
-
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP "\t.section .init,\"x\""
-
-#define CTOR_LIST_BEGIN \
- asm (INIT_SECTION_ASM_OP); \
- asm ("pushl $0")
-#define CTOR_LIST_END CTOR_LIST_BEGIN
-
-#undef TARGET_ASM_CONSTRUCTOR
-#define TARGET_ASM_CONSTRUCTOR ix86_svr3_asm_out_constructor
+++ /dev/null
-/* Definitions for IBM PS2 running AIX/386.
- Copyright (C) 1988, 1996, 1998, 2002 Free Software Foundation, Inc.
- Contributed by Minh Tran-Le <TRANLE@intellicorp.com>.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define TARGET_VERSION fprintf (stderr, " (80386, AIX)");
-
-/* Use crt1.o as a startup file and crtn.o as a closing file. */
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-#define ENDFILE_SPEC "crtn.o%s"
-
-#define LIB_SPEC "%{shlib:-lc_s} -lc"
-
-/* Special flags for the linker. I don't know what they do. */
-
-#define LINK_SPEC "%{K} %{!K:-K} %{T*} %{z:-lm}"
-
-/* Specify predefined symbols in preprocessor. */
-
-#define CPP_PREDEFINES "-Dps2 -Dunix -Asystem=aix"
-
-#define CPP_SPEC "%(cpp_cpu) \
- %{posix:-D_POSIX_SOURCE}%{!posix:-DAIX} -D_I386 -D_AIX -D_MBCS"
-
-/* special flags for the aix assembler to generate the short form for all
- qualifying forward reference */
-/* The buggy /bin/as of aix ps/2 1.2.x cannot always handle it. */
-#if 0
-#define ASM_SPEC "-s2"
-#endif /* 0 */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
- do { output_file_directive (FILE, main_input_filename); \
- if (optimize) \
- ASM_FILE_START_1 (FILE); \
- else \
- fprintf (FILE, "\t.noopt\n"); \
- } while (0)
-
-/* This was suggested, but it shouldn't be right for DBX output. -- RMS
- #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */
-
-/* Writing `int' for a bitfield forces int alignment for the structure. */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-#ifndef USE_GAS
-/* Don't write a `.optim' pseudo; this assembler
- is said to have a bug when .optim is used. */
-
-#undef ASM_FILE_START_1
-#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.noopt\n")
-#endif
-\f
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tleal %sP%d,%%eax\n\tcall mcount\n", LPREFIX, (LABELNO));
-
-/* Note that using bss_section here caused errors
- in building shared libraries on system V.3.
- but AIX 1.2 does not have yet shareable libraries on PS2 */
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
- (bss_section (), \
- ASM_OUTPUT_LABEL ((FILE), (NAME)), \
- fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)))
-
-
-/* Undef all the .init and .fini section stuff if we are not using gas and
- * gnu ld so that we can use collect because the standard /bin/as and /bin/ld
- * cannot handle those.
- */
-#ifndef USE_GAS
-# undef READONLY_DATA_SECTION_ASM_OP
-# undef INIT_SECTION_ASM_OP
-# undef FINI_SECTION_ASM_OP
-# undef CTORS_SECTION_ASM_OP
-# undef DTORS_SECTION_ASM_OP
-# undef TARGET_ASM_CONSTRUCTOR
-# undef TARGET_ASM_DESTRUCTOR
-# undef DO_GLOBAL_CTORS_BODY
-
-# undef CTOR_LIST_BEGIN
-# define CTOR_LIST_BEGIN
-# undef CTOR_LIST_END
-# define CTOR_LIST_END
-# undef DTOR_LIST_BEGIN
-# define DTOR_LIST_BEGIN
-# undef DTOR_LIST_END
-# define DTOR_LIST_END
-
-/* for collect2 */
-# define OBJECT_FORMAT_COFF
-# define MY_ISCOFF(magic) \
- ((magic) == I386MAGIC || (magic) == I386SVMAGIC)
-
-#endif /* !USE_GAS */
+++ /dev/null
-/* Configuration for an i386 running BSDI's BSD/OS (formerly known as BSD/386)
- as the target machine. */
-
-/* We exist mostly to add -Dbsdi and such to the predefines. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dbsdi -D____386BSD____ -D__386BSD__\
- -DBSD_NET2 -Asystem=unix -Asystem=bsd"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-/* This is suitable for BSD/OS 3.0; we don't know about earlier releases. */
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START " #"
-
-/* Until they use ELF or something that handles dwarf2 unwinds
- and initialization stuff better. */
-#define DWARF2_UNWIND_INFO 0
-
-/* BSD/OS still uses old binutils that don't insert nops by default
- when the .align directive demands to insert extra space in the text
- segment. */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG)!=0) fprintf ((FILE), "\t.align %d,0x90\n", (LOG))
+++ /dev/null
-/* Target definitions for GNU compiler for Intel 80x86 running DG/ux
- Copyright (C) 1993, 1995, 1996, 1997, 1998, 2000, 2001, 2002
- Free Software Foundation, Inc.
- Currently maintained by gcc@dg-rtp.dg.com.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* for now, we are just like the sysv4 version with a
- few hacks
-*/
-
-#ifndef VERSION_INFO2
-#define VERSION_INFO2 "$Revision: 1.18 $"
-#endif
-
-#ifndef VERSION_STRING
-#define VERSION_STRING version_string
-#endif
-
-/* Identify the compiler. */
-/* TARGET_VERSION used by toplev.c VERSION_STRING used by -midentify-revision */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (%s%s, %s)", \
- VERSION_INFO1, VERSION_INFO2, __DATE__)
-#undef VERSION_INFO1
-#define VERSION_INFO1 "ix86 DG/ux, "
-
-/* Augment TARGET_SWITCHES with the MXDB options. */
-#define MASK_STANDARD 0x40000000 /* Retain standard information */
-#define MASK_NOLEGEND 0x20000000 /* Discard legend information */
-#define MASK_EXTERNAL_LEGEND 0x10000000 /* Make external legends */
-#define MASK_IDENTIFY_REVISION 0x08000000 /* Emit 'ident' to .s */
-#define MASK_WARN_PASS_STRUCT 0x04000000 /* Warn when structures are passed */
-
-#define TARGET_STANDARD (target_flags & MASK_STANDARD)
-#define TARGET_NOLEGEND (target_flags & MASK_NOLEGEND)
-#define TARGET_EXTERNAL_LEGEND (target_flags & MASK_EXTERNAL_LEGEND)
-#define TARGET_IDENTIFY_REVISION (target_flags & MASK_IDENTIFY_REVISION)
-#define TARGET_WARN_PASS_STRUCT (target_flags & MASK_WARN_PASS_STRUCT)
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- { "standard", MASK_STANDARD, \
- N_("Retain standard MXDB information") }, \
- { "legend", -MASK_NOLEGEND, \
- N_("Retain legend information") }, \
- { "no-legend", MASK_NOLEGEND, "" }, \
- { "external-legend", MASK_EXTERNAL_LEGEND, \
- N_("Generate external legend information") }, \
- { "identify-revision", MASK_IDENTIFY_REVISION, \
- N_("Emit identifying info in .s file") }, \
- { "warn-passed-structs", MASK_WARN_PASS_STRUCT, \
- N_("Warn when a function arg is a structure") },
-
-#undef DWARF_DEBUGGING_INFO
-#define DWARF_DEBUGGING_INFO
-
-/*
- allow -gstabs so that those who have gnu-as installed
- can debug c++ programs.
-*/
-#undef DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
-
-/* Override svr[34].h. Switch to the data section so that the coffsem
- symbol isn't in the text section. */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
- do { \
- output_file_directive (FILE, main_input_filename); \
- fprintf (FILE, "\t.version\t\"01.01\"\n"); \
- data_section (); \
- } while (0)
-
-/* ix86 abi specified type for wchar_t */
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-
-/* Some machines may desire to change what optimizations are performed for
- various optimization levels. This macro, if defined, is executed once
- just after the optimization level is determined and before the remainder
- of the command options have been parsed. Values set in this macro are
- used as the default values for the other command line options.
-
- LEVEL is the optimization level specified; 2 if -O2 is specified,
- 1 if -O is specified, and 0 if neither is specified. */
-
-/* This macro used to store 0 in flag_signed_bitfields.
- Not only is that misuse of this macro; the whole idea is wrong.
-
- The GNU C dialect makes bitfields signed by default,
- regardless of machine type. Making any machine inconsistent in this
- regard is bad for portability.
-
- I chose to make bitfields signed by default because this is consistent
- with the way ordinary variables are handled: `int' equals `signed int'.
- If there is a good reason to prefer making bitfields unsigned by default,
- it cannot have anything to do with the choice of machine.
- If the reason is good enough, we should change the convention for all machines.
-
- -- rms, 20 July 1991. */
-
-/*
- this really should go into dgux-local.h
-*/
-
-#undef OPTIMIZATION_OPTIONS
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
- do { \
- extern int flag_signed_bitfields; \
- flag_signed_bitfields = 0; \
- optimization_options (LEVEL,SIZE); \
- } while (0)
-
-
-/* The normal location of the `ld' and `as' programs */
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/bin/"
-
-/* The normal location of the various *crt*.o files is the */
-
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/lib/"
-
-/* Macros to be automatically defined.
- __CLASSIFY_TYPE__ is used in the <varargs.h> and <stdarg.h> header
- files with DG/UX revision 5.40 and later. This allows GNU CC to
- operate without installing the header files. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ix86 -Dunix -DDGUX -D__CLASSIFY_TYPE__=2\
- -Asystem=unix -Asystem=svr4"
-
- /*
- If not -ansi, or restricting include files to one
- specific source target, specify full DG/UX features.
- */
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{!ansi:-D__OPEN_NAMESPACE__}"
-
-/* Assembler support (legends for mxdb). */
-#undef ASM_SPEC
-#define ASM_SPEC "\
-%{mno-legend:%{mstandard:-Wc,off}}\
-%{g:%{!mno-legend:-Wc,-fix-bb,-s\"%i\",-lansi-c\
-%{mstandard:,-keep-std}\
-%{mexternal-legend:,-external}}}"
-
-/* Override svr4.h. */
-
-/* hassey 3/12/94 keep svr4 ASM_FINAL_SPEC allows -pipe to work */
-
-/* Linker and library spec's.
- -static, -shared, -symbolic, -h* and -z* access AT&T V.4 link options.
- -svr4 instructs gcc to place /usr/lib/values-X[cat].o on link the line.
- The absence of -msvr4 indicates linking done in a COFF environment and
- adds the link script to the link line. In all environments, the first
- and last objects are crtbegin.o and crtend.o.
- When the -G link option is used (-shared and -symbolic) a final link is
- not being done. */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-"%{!shared:%{!symbolic:-lc}}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{z*} %{h*} %{v:-V} \
- %{static:-dn -Bstatic} \
- %{shared:-G -dy} \
- %{symbolic:-Bsymbolic -G -dy} \
- %{pg:-L/usr/lib/libp}%{p:-L/usr/lib/libp}"
-
-#ifdef CROSS_COMPILE
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:%{!symbolic:%{pg:gcrt1.o%s} \
- %{!pg:%{p:mcrt1.o%s} \
- %{!p:crt1.o%s}}}} \
- %{pg:gcrti.o%s}%{!pg:crti.o%s} \
- crtbegin.o%s \
- %{ansi:values-Xc.o%s} \
- %{!ansi:values-Xa.o%s}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s %{pg:gcrtn.o}%{!pg:crtn.o%s}"
-
-#else
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:%{!symbolic:%{pg:gcrt1.o%s} \
- %{!pg:%{p:/lib/mcrt1.o%s} \
- %{!p:/lib/crt1.o%s}}}} \
- %{pg:gcrti.o%s}%{!pg:/lib/crti.o%s} \
- crtbegin.o%s \
- %{ansi:/lib/values-Xc.o%s} \
- %{!ansi:/lib/values-Xa.o%s}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s %{pg:gcrtn.o}%{!pg:/lib/crtn.o}"
-
-#endif /* CROSS_COMPILE */
-
-/* The maximum alignment which the object file format can support.
- page alignment would seem to be enough */
-#undef MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 0x1000
-
-/* This supplements FUNCTION_ARG's definition in i386.h to check
- TARGET_WARN_PASS_STRUCT */
-
-#undef FUNCTION_ARG
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((((MODE) == BLKmode && TARGET_WARN_PASS_STRUCT) ? \
- warning ("argument is a structure"),0 : 0), \
- (function_arg (&CUM, MODE, TYPE, NAMED)))
-
-/* Add .align 1 to avoid .backalign bug in assembler */
-#undef READONLY_DATA_SECTION_ASM_OP
-#define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata\n\t.align 1"
+++ /dev/null
-/* Configuration for an i386 running RTEMS on top of MS-DOS with
- DJGPP v2.x.
-
- Copyright (C) 1996, 1999, 2002 Free Software Foundation, Inc.
- Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Specify predefined symbols in preprocessor. */
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-#define CPP_PREDEFINES "-Dunix -DGO32 -DDJGPP=2 -DMSDOS -D__rtems__ \
- -Asystem=unix -Asystem=msdos -Asystem=rtems"
-
-/* Generate calls to memcpy, memcmp and memset. */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
+++ /dev/null
-/* Assembler-independent definitions for an Intel 386 running
- Interactive Unix System V. Specifically, this is for recent versions
- that support POSIX;
- for version 2.0.2, use configuration option i386-sysv instead.
- (But set TARGET_DEFAULT to (MASK_80307 | MASK_FLOAT_RETURNS)
- if you do that, if you don't have a real 80387.) */
-
-/* Mostly it's like AT&T Unix System V. */
-
-/* Use crt1.o, not crt0.o, as a startup file, and crtn.o as a closing file. */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
- %{Xp:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
- %{!posix:%{!Xp:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\
- %{p:-L/lib/libp} %{pg:-L/lib/libp}}}}\
- %{shlib:%{Xp:crtp1.o%s}%{posix:crtp1.o%s}%{!posix:%{!Xp:crt1.o%s}}}\
- crtbegin.o%s"
-
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-/* Library spec */
-#undef LIB_SPEC
-#define LIB_SPEC "%{shlib:-lc_s} %{posix:-lcposix} %{Xp:-lcposix} -lc -lg"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE} %{Xp:-D_POSIX_SOURCE}"
-
-/* ISC 2.2 uses `char' for `wchar_t'. */
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "char"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_UNIT
-
-#if 0
-/* This is apparently not true: ISC versions up to 3.0, at least, use
- the standard calling sequence in which the called function pops the
- extra arg. */
-/* caller has to pop the extra argument passed to functions that return
- structures. */
-
-#undef RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
- ((FUNDECL) && TREE_CODE (FUNDECL) == IDENTIFIER_NODE ? 0 \
- : (TARGET_RTD \
- && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
- || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
- == void_type_node))) ? (SIZE) \
- : 0)
-/* On other 386 systems, the last line looks like this:
- : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) */
-#endif
-
-/* Handle #pragma pack and #pragma weak. */
-#define HANDLE_SYSV_PRAGMA
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
- and returns float values in the 387, ie,
- (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387)
-
- ISC's software emulation of a 387 fails to handle the `fucomp'
- opcode. fucomp is only used when generating IEEE compliant code.
- So don't make TARGET_IEEE_FP default for ISC. */
-
-#undef TARGET_SUBTARGET_DEFAULT
-#define TARGET_SUBTARGET_DEFAULT (MASK_80387 | MASK_FLOAT_RETURNS)
-
-/* The ISC 2.0.2 software FPU emulator apparently can't handle
- 80-bit XFmode insns, so don't generate them. */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* The ISC assembler does not like a .file directive with a name
- longer than 14 characters. Truncating it will not permit
- debugging to work properly, but at least we won't get an error
- message. */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
- do { \
- const int len = strlen (main_input_filename); \
- const char *na = main_input_filename + len; \
- char shorter[15]; \
- /* NA gets MAIN_INPUT_FILENAME sans directory names. */\
- while (na > main_input_filename) \
- { \
- if (na[-1] == '/') \
- break; \
- na--; \
- } \
- strncpy (shorter, na, 14); \
- shorter[14] = 0; \
- fprintf (FILE, "\t.file\t"); \
- output_quoted_string (FILE, shorter); \
- fprintf (FILE, "\n"); \
- } while (0)
-
-/* Work around assembler forward label references generated in exception
- handling code. */
-#define DWARF2_UNWIND_INFO 0
+++ /dev/null
-/* Definitions for Intel 386 running Interactive Unix System V,
- using dbx-in-coff encapsulation.
- Specifically, this is for recent versions that support POSIX.
- Copyright (C) 1992, 1995, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Mostly it's like AT&T Unix System V with dbx-in-coff. */
-
-/* But with a few changes. */
-#undef ENDFILE_SPEC
-#include "i386/isc.h"
-
-/* Overridden defines for ifile usage. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\
- %{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
- %{Xp:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
- %{!posix:%{!Xp:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}\
- %{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp}}\
- %{shlib:%{posix:crtp1.o%s}%{Xp:crtp1.o%s}%{!posix:%{!Xp:crt1.o%s}}}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtn.o%s"
+++ /dev/null
-/* Definitions for Intel 386 running Linux-based GNU systems with pre-BFD
- a.out linkers.
- Copyright (C) 1995, 1997, 1998, 2002 Free Software Foundation, Inc.
- Contributed by Michael Meissner (meissner@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "#"
-
-/* Specify predefined symbols in preprocessor. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -D__gnu_linux__ -Dlinux -Asystem=posix"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler,
- and we want to retain compatibility with older gcc versions. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-#undef LIB_SPEC
-
-#if 1
-/* We no longer link with libc_p.a or libg.a by default. If you
- want to profile or debug the GNU/Linux C library, please add
- lc_p or -ggdb to LDFLAGS at the link time, respectively. */
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}"
-#else
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
- %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}"
-#endif
-
-\f
-#undef LINK_SPEC
-#define LINK_SPEC ""
+++ /dev/null
-/* Target definitions for GNU compiler for Intel x86 CPU running NeXTSTEP
- Copyright (C) 1993, 1995, 1996, 1999, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* By default, target has a 80387, with IEEE FP. */
-
-#undef TARGET_SUBTARGET_DEFAULT
-#define TARGET_SUBTARGET_DEFAULT (MASK_80387 | MASK_IEEE_FP)
-
-/* Implicit library calls should use memcpy, not bcopy, etc. */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Machines that use the AT&T assembler syntax
- also return floating point values in an FP register.
- Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-#undef VALUE_REGNO
-#define VALUE_REGNO(MODE) \
- ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
- ? FIRST_FLOAT_REG : 0)
-
-/* A C statement or statements which output an assembler instruction
- opcode to the stdio stream STREAM. The macro-operand PTR is a
- variable of type `char *' which points to the opcode name in its
- "internal" form--the form that is written in the machine description.
-
- GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic.
- So use `repe' instead. */
-
-#undef ASM_OUTPUT_OPCODE
-#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
-{ \
- if ((PTR)[0] == 'r' \
- && (PTR)[1] == 'e' \
- && (PTR)[2] == 'p') \
- { \
- if ((PTR)[3] == 'z') \
- { \
- fprintf (STREAM, "repe"); \
- (PTR) += 4; \
- } \
- else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \
- { \
- fprintf (STREAM, "repne"); \
- (PTR) += 5; \
- } \
- } \
-}
-
-/* Define macro used to output shift-double opcodes when the shift
- count is in %cl. Some assemblers require %cl as an argument;
- some don't.
-
- GAS requires the %cl argument, so override unx386.h. */
-
-#undef SHIFT_DOUBLE_OMITS_COUNT
-#define SHIFT_DOUBLE_OMITS_COUNT 0
-
-/* Print opcodes the way that GAS expects them. */
-#define GAS_MNEMONICS 1
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-DNeXT -Dunix -D__MACH__ -D__LITTLE_ENDIAN__ \
- -D__ARCHITECTURE__=\"i386\" -Asystem=unix -Asystem=mach"
-
-/* This accounts for the return pc and saved fp on the i386. */
-
-#define OBJC_FORWARDING_STACK_OFFSET 8
-#define OBJC_FORWARDING_MIN_OFFSET 8
-
-/* We do not want a dot in internal labels. */
-
-#undef LPREFIX
-#define LPREFIX "L"
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \
- sprintf ((BUF), "*%s%ld", (PREFIX), (long)(NUMBER))
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#undef ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tpushl %se%s\n", "%", reg_names[REGNO])
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tpopl %se%s\n", "%", reg_names[REGNO])
-
-/* This is being overridden because the default i386 configuration
- generates calls to "_mcount". NeXT system libraries all use
- "mcount". */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-{ \
- if (flag_pic) \
- { \
- fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \
- LPREFIX, (LABELNO)); \
- fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \
- } \
- else \
- { \
- fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
- fprintf (FILE, "\tcall mcount\n"); \
- } \
-}
-
-/* BEGIN Calling Convention CHANGES */
-
-/* These changes violate the Intel/Unix ABI. Specifically, they
- change the way that space for a block return value is passed to a
- function. The ABI says that the pointer is passed on the stack.
- We change to pass the pointer in %ebx. This makes the NeXT
- Objective-C forwarding mechanism possible to implement on an i386. */
-
-/* Do NOT pass address of structure values on the stack. */
-
-#undef STRUCT_VALUE_INCOMING
-#undef STRUCT_VALUE
-
-/* Pass them in %ebx. */
-
-#undef STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE_REGNUM 3
-
-/* Because we are passing the pointer in a register, we don't need to
- rely on the callee to pop it. */
-
-#undef RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
- ((FUNDECL) && TREE_CODE (FUNDECL) == IDENTIFIER_NODE \
- ? 0 \
- : (TARGET_RTD \
- && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
- || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
- == void_type_node))) ? (SIZE) : 0)
-
-/* END Calling Convention CHANGES */
-
-/* NeXT still uses old binutils that don't insert nops by default
- when the .align directive demands to insert extra space in the text
- segment. */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG)!=0) fprintf ((FILE), "\t.align %d,0x90\n", (LOG))
+++ /dev/null
-! crti.s for OSF/1, x86; derived from sol2-ci.asm.
-
-! Copyright (C) 1993, 1998 Free Software Foundation, Inc.
-! Written By Fred Fish, Nov 1992
-!
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-!
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file. (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-!
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-! General Public License for more details.
-!
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING. If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-!
-! As a special exception, if you link this library with files
-! compiled with GCC to produce an executable, this does not cause
-! the resulting executable to be covered by the GNU General Public License.
-! This exception does not however invalidate any other reasons why
-! the executable file might be covered by the GNU General Public License.
-!
-
-! This file just supplies labeled starting points for the .init and .fini
-! sections. It is linked in before the values-Xx.o files and also before
-! crtbegin.o.
-
- .file "crti.s"
- .ident "GNU C crti.s"
-
- .section .init
- .globl _init
- .type _init,@function
-_init:
-
- .section .fini
- .globl _fini
- .type _fini,@function
-_fini:
-
-.globl _init_init_routine
-.data
- .align 4
- .type _init_init_routine,@object
- .size _init_init_routine,4
-_init_init_routine:
- .long _init
-.globl _init_fini_routine
- .align 4
- .type _init_fini_routine,@object
- .size _init_fini_routine,4
-_init_fini_routine:
- .long _fini
+++ /dev/null
-! crtn.s for OSF/1, x86; derived from sol2-cn.asm.
-
-! Copyright (C) 1993, 1998 Free Software Foundation, Inc.
-! Written By Fred Fish, Nov 1992
-!
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-!
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file. (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-!
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-! General Public License for more details.
-!
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING. If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-!
-! As a special exception, if you link this library with files
-! compiled with GCC to produce an executable, this does not cause
-! the resulting executable to be covered by the GNU General Public License.
-! This exception does not however invalidate any other reasons why
-! the executable file might be covered by the GNU General Public License.
-!
-
-! This file just supplies returns for the .init and .fini sections. It is
-! linked in after all other files.
-
- .file "crtn.o"
- .ident "GNU C crtn.o"
-
- .section .init
- ret $0x0
-
- .section .fini
- ret $0x0
+++ /dev/null
-/* OSF/1 1.3 now is compitable with SVR4, so include sysv4.h, and
- put difference here.
- Copyright (C) 2000 Free Software Foundation, Inc. */
-
-#include <stdio.h>
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 OSF/1)");
-
-#define TARGET_OSF1ELF
-
-/* WORD_SWITCH_TAKES_ARG defined in svr4 is not correct. We also
- need an extra -soname */
-#undef WORD_SWITCH_TAKES_ARG
-#define WORD_SWITCH_TAKES_ARG(STR) \
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
- || !strcmp (STR, "Tdata") || !strcmp (STR, "Ttext") \
- || !strcmp (STR, "Tbss") || !strcmp (STR, "soname"))
-
-/* Note, -fpic and -fPIC are equivalent */
-#undef CPP_SPEC
-#define CPP_SPEC "\
-%(cpp_cpu) \
-%{fpic: -D__SHARED__} %{fPIC: %{!fpic: -D__SHARED__}} \
-%{.S: %{!ansi:%{!traditional-cpp: -traditional}}} \
-%{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.cc: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.C: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.m: -D__LANGUAGE_OBJECTIVE_C} \
-%{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}"
-
-/* -mmcount or -mno-mcount should be used with -pg or -p */
-#undef CC1_SPEC
-#define CC1_SPEC "%(cc1_cpu) %{p: %{!mmcount: %{!mno-mcount: -mno-mcount }}} \
-%{!p: %{pg: %{!mmcount: %{!mno-mcount: -mno-mcount }}}}"
-
-/* Note, -D__NO_UNDERSCORES__ -D__ELF__ are provided in the older version of
- OSF/1 gcc. We keep them here, so that old /usr/include/i386/asm.h works.
- */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-D__NO_UNDERSCORES__ -D__ELF__ -DOSF -DOSF1 -Dunix \
- -Asystem=unix -Asystem=xpg4 -Asystem=osf1"
-
-/* current OSF/1 doesn't provide separate crti.o and gcrti.o (and also, crtn.o
- and gcrtn.o) for profile. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
- %{!symbolic: \
- %{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}}\
- crti.o%s \
- crtbegin.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{v*: -v}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{v*: -v} \
- %{h*} %{z*} \
- %{dy:-call_shared} %{dn:-static} \
- %{static:-static} \
- %{shared:-shared} \
- %{call_shared:-call_shared} \
- %{symbolic:-Bsymbolic -shared -call_shared} \
- %{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \
- %{noshrlib: -static } \
- %{!noshrlib: -call_shared}}}}}}"
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/ccs/gcc/"
-
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-
-/* Define this macro meaning that gcc should find the library 'libgcc.a'
- by hand, rather than passing the argument '-lgcc' to tell the linker
- to do the search */
-#define LINK_LIBGCC_SPECIAL
-
-/* This goes with LINK_LIBGCC_SPECIAL, we need tell libgcc.a differently */
-#undef LIBGCC_SPEC
-#define LIBGCC_SPEC "%{!shared:%{!symbolic:libgcc.a%s}}"
-
-/* Specify size_t, ptrdiff_t, and wchar_t types. */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-#define SIZE_TYPE "long unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_TYPE "unsigned int"
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Turn off long double being 96 bits. */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Work with OSF/1 profile */
-#define MASK_NO_MCOUNT 000200000000 /* profiling uses mcount_ptr */
-
-#define TARGET_MCOUNT ((target_flags & MASK_NO_MCOUNT) == 0)
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- { "mcount", -MASK_NO_MCOUNT, \
- N_("Profiling uses mcount") }, \
- { "no-mcount", MASK_NO_MCOUNT, "" },
-
-/* This macro generates the assembly code for function entry.
- FILE is a stdio stream to output the code to.
- SIZE is an int: how many units of temporary storage to allocate.
- Refer to the array `regs_ever_live' to determine which registers
- to save; `regs_ever_live[I]' is nonzero if register number I
- is ever used in the function. This macro is responsible for
- knowing which registers should not be saved even if used.
-
- We override it here to allow for the new profiling code to go before
- the prologue and the old mcount code to go after the prologue (and
- after %ebx has been set up for ELF shared library support). */
-#if 0
-#define OSF_PROFILE_BEFORE_PROLOGUE \
- (!TARGET_MCOUNT \
- && !current_function_needs_context \
- && (!flag_pic \
- || !frame_pointer_needed \
- || (!current_function_uses_pic_offset_table \
- && !current_function_uses_const_pool)))
-#else
-#define OSF_PROFILE_BEFORE_PROLOGUE 0
-#endif
-
-/* A C statement or compound statement to output to FILE some assembler code to
- call the profiling subroutine `mcount'. Before calling, the assembler code
- must load the address of a counter variable into a register where `mcount'
- expects to find the address. The name of this variable is `LP' followed by
- the number LABELNO, so you would generate the name using `LP%d' in a
- `fprintf'.
-
- The details of how the address should be passed to `mcount' are determined
- by your operating system environment, not by GNU CC. To figure them out,
- compile a small program for profiling using the system's installed C
- compiler and look at the assembler code that results. */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-do \
- { \
- if (!OSF_PROFILE_BEFORE_PROLOGUE) \
- { \
- const char *const prefix = ""; \
- const char *const lprefix = LPREFIX; \
- int labelno = LABELNO; \
- \
- /* Note that OSF/rose blew it in terms of calling mcount, \
- since OSF/rose prepends a leading underscore, but mcount's \
- doesn't. At present, we keep this kludge for ELF as well \
- to allow old kernels to build profiling. */ \
- \
- if (flag_pic \
- && !current_function_uses_pic_offset_table \
- && !current_function_uses_const_pool) \
- abort (); \
- \
- if (TARGET_MCOUNT && flag_pic) \
- { \
- fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \
- lprefix, labelno); \
- fprintf (FILE, "\tcall *%smcount@GOT(%%ebx)\n", prefix); \
- } \
- \
- else if (TARGET_MCOUNT) \
- { \
- fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \
- fprintf (FILE, "\tcall %smcount\n", prefix); \
- } \
- \
- else if (flag_pic && frame_pointer_needed) \
- { \
- fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \
- fprintf (FILE, "\tpushl %%ecx\n"); \
- fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \
- lprefix, labelno); \
- fprintf (FILE, "\tmovl _mcount_ptr@GOT(%%ebx),%%eax\n"); \
- fprintf (FILE, "\tcall *(%%eax)\n"); \
- fprintf (FILE, "\tpopl %%eax\n"); \
- } \
- \
- else if (frame_pointer_needed) \
- { \
- fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \
- fprintf (FILE, "\tpushl %%ecx\n"); \
- fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \
- fprintf (FILE, "\tcall *_mcount_ptr\n"); \
- fprintf (FILE, "\tpopl %%eax\n"); \
- } \
- \
- else \
- abort (); \
- } \
- } \
-while (0)
+++ /dev/null
-/* Target definitions for GNU compiler for Intel 80386 running OSF/1 1.3+
- with gas and gdb. */
-
-/* Use stabs instead of DWARF debug format. */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Intel 386 (OSF/1 with ELF) version.
- Copyright (C) 1993, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Asystem=xpg4"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-%{mrose: -D__ROSE__ %{!pic-none: -D__SHARED__}} \
-%{!mrose: -D__ELF__ %{fpic: -D__SHARED__}} \
-%{mno-underscores: -D__NO_UNDERSCORES__} \
-%{!mrose: %{!munderscores: -D__NO_UNDERSCORES__}} \
-%{.S: %{!ansi:%{!traditional-cpp: -traditional}}} \
-%{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.cc: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.C: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.m: -D__LANGUAGE_OBJECTIVE_C} \
-%{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}"
-
-/* Turn on -pic-extern by default for OSF/rose, -fpic for ELF. */
-#undef CC1_SPEC
-#define CC1_SPEC "%(cc1_cpu) \
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{!melf: %{!mrose: -melf }} \
-%{!mrose: %{!munderscores: %{!mno-underscores: -mno-underscores }} \
- %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount-ptr }}}} \
-%{mrose: %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount }}} \
- %{pic-extern: -mhalf-pic } %{pic-lib: -mhalf-pic } \
- %{!pic-extern: %{!pic-lib: %{pic-none: -mno-half-pic} %{!pic-none: -mhalf-pic}}} \
- %{pic-calls: } %{pic-names*: }}"
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{v*: -v}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{v*: -v} \
-%{mrose: %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \
- %{nostdlib} %{noshrlib} %{glue}} \
-%{!mrose: %{dy} %{dn} %{glue: } \
- %{h*} %{z*} \
- %{static:-dn -Bstatic} \
- %{shared:-G -dy} \
- %{symbolic:-Bsymbolic -G -dy} \
- %{G:-G} \
- %{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \
- %{noshrlib: -dn } %{pic-none: -dn } \
- %{!noshrlib: %{!pic-none: -dy}}}}}}}}"
-
-#undef TARGET_VERSION_INTERNAL
-
-#undef I386_VERSION
-#define I386_VERSION " 80386, ELF objects"
-
-#define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM)
-#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
-
-#undef OBJECT_FORMAT_ROSE
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Intel 386 (OSF/1 with OSF/rose) version.
- Copyright (C) 1991, 1992, 1993, 1996, 1998, 1999, 2000, 2002
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define OSF_OS
-
-#undef WORD_SWITCH_TAKES_ARG
-#define WORD_SWITCH_TAKES_ARG(STR) \
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names"))
-
-/* This defines which switch letters take arguments. On svr4, most of
- the normal cases (defined in gcc.c) apply, and we also have -h* and
- -z* options (for the linker). */
-
-#define SWITCH_TAKES_ARG(CHAR) \
- (DEFAULT_SWITCH_TAKES_ARG(CHAR) \
- || (CHAR) == 'h' \
- || (CHAR) == 'z')
-
-#define MASK_HALF_PIC 010000000000 /* Mask for half-pic code */
-#define MASK_HALF_PIC_DEBUG 004000000000 /* Debug flag */
-#define MASK_ELF 002000000000 /* ELF not rose */
-#define MASK_NO_UNDERSCORES 000400000000 /* suppress leading _ */
-#define MASK_LARGE_ALIGN 000200000000 /* align to >word boundaries */
-#define MASK_NO_MCOUNT 000100000000 /* profiling uses mcount_ptr */
-
-#define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
-#define TARGET_DEBUG (target_flags & MASK_HALF_PIC_DEBUG)
-#define HALF_PIC_DEBUG TARGET_DEBUG
-#define TARGET_ELF (target_flags & MASK_ELF)
-#define TARGET_ROSE ((target_flags & MASK_ELF) == 0)
-#define TARGET_UNDERSCORES ((target_flags & MASK_NO_UNDERSCORES) == 0)
-#define TARGET_LARGE_ALIGN (target_flags & MASK_LARGE_ALIGN)
-#define TARGET_MCOUNT ((target_flags & MASK_NO_MCOUNT) == 0)
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- { "half-pic", MASK_HALF_PIC, \
- N_("Emit half-PIC code") }, \
- { "no-half-pic", -MASK_HALF_PIC, "" }, \
- { "debug-half-pic", MASK_HALF_PIC_DEBUG, \
- 0 /* intentionally undoc */ }, \
- { "debugb", MASK_HALF_PIC_DEBUG, \
- 0 /* intentionally undoc */ }, \
- { "elf", MASK_ELF, \
- N_("Emit ELF object code") }, \
- { "rose", -MASK_ELF, \
- N_("Emit ROSE object code") }, \
- { "underscores", -MASK_NO_UNDERSCORES, \
- N_("Symbols have a leading underscore") }, \
- { "no-underscores", MASK_NO_UNDERSCORES, "" }, \
- { "large-align", MASK_LARGE_ALIGN, \
- N_("Align to >word boundaries") }, \
- { "no-large-align", -MASK_LARGE_ALIGN, "" }, \
- { "mcount", -MASK_NO_MCOUNT, \
- N_("Use mcount for profiling") }, \
- { "mcount-ptr", MASK_NO_MCOUNT, \
- N_("Use mcount_ptr for profiling") }, \
- { "no-mcount", MASK_NO_MCOUNT, "" },
-
-/* OSF/rose uses stabs, not dwarf. */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#ifndef DWARF_DEBUGGING_INFO
-#define DWARF_DEBUGGING_INFO /* enable dwarf debugging for testing */
-#endif
-
-/* Handle #pragma weak and #pragma pack. */
-
-#define HANDLE_SYSV_PRAGMA
-#define SUPPORTS_WEAK TARGET_ELF
-
-/* Change default predefines. */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Asystem=xpg4"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-%{!melf: -D__ROSE__ %{!pic-none: -D__SHARED__}} \
-%{melf: -D__ELF__ %{fpic: -D__SHARED__}} \
-%{mno-underscores: -D__NO_UNDERSCORES__} \
-%{melf: %{!munderscores: -D__NO_UNDERSCORES__}} \
-%{.S: %{!ansi:%{!traditional-cpp: -traditional}}} \
-%{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.cc: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.C: -D__LANGUAGE_C_PLUS_PLUS} \
-%{.m: -D__LANGUAGE_OBJECTIVE_C} \
-%{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}"
-
-/* Turn on -pic-extern by default for OSF/rose, -fpic for ELF. */
-#undef CC1_SPEC
-#define CC1_SPEC "%(cc1_cpu) \
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{!melf: %{!mrose: -mrose }} \
-%{melf: %{!munderscores: %{!mno-underscores: -mno-underscores }} \
- %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount-ptr }}}} \
-%{!melf: %{!munderscores: %{!mno-underscores: -munderscores }} \
- %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount }}} \
- %{pic-extern: -mhalf-pic } %{pic-lib: -mhalf-pic } \
- %{!pic-extern: %{!pic-lib: %{pic-none: -mno-half-pic} %{!pic-none: -mhalf-pic}}} \
- %{pic-calls: } %{pic-names*: }}"
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{v*: -v}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{v*: -v} \
-%{!melf: %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \
- %{nostdlib} %{noshrlib} %{glue}} \
-%{melf: %{dy} %{dn} %{glue: } \
- %{h*} %{z*} \
- %{static:-dn -Bstatic} \
- %{shared:-G -dy} \
- %{symbolic:-Bsymbolic -G -dy} \
- %{G:-G} \
- %{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \
- %{noshrlib: -dn } %{pic-none: -dn } \
- %{!noshrlib: %{!pic-none: -dy}}}}}}}}"
-
-#undef LIB_SPEC
-#define LIB_SPEC "-lc"
-
-#undef LIBG_SPEC
-#define LIBG_SPEC ""
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#undef TARGET_VERSION_INTERNAL
-
-#define I386_VERSION " 80386, OSF/rose objects"
-
-#define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM)
-#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/ccs/gcc/"
-
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-
-/* Specify size_t, ptrdiff_t, and wchar_t types. */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-#define SIZE_TYPE "long unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_TYPE "unsigned int"
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Define this macro if the system header files support C++ as well
- as C. This macro inhibits the usual method of using system header
- files in C++, which is to pretend that the file's contents are
- enclosed in `extern "C" {...}'. */
-#define NO_IMPLICIT_EXTERN_C
-
-/* Turn off long double being 96 bits. */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-#define OSF_PROFILE_BEFORE_PROLOGUE \
- (!TARGET_MCOUNT \
- && !current_function_needs_context \
- && (!flag_pic \
- || !frame_pointer_needed \
- || (!current_function_uses_pic_offset_table \
- && !current_function_uses_const_pool)))
-
-/* A C statement or compound statement to output to FILE some assembler code to
- call the profiling subroutine `mcount'. Before calling, the assembler code
- must load the address of a counter variable into a register where `mcount'
- expects to find the address. The name of this variable is `LP' followed by
- the number LABELNO, so you would generate the name using `LP%d' in a
- `fprintf'.
-
- The details of how the address should be passed to `mcount' are determined
- by your operating system environment, not by GNU CC. To figure them out,
- compile a small program for profiling using the system's installed C
- compiler and look at the assembler code that results. */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-do \
- { \
- if (!OSF_PROFILE_BEFORE_PROLOGUE) \
- { \
- const char *const prefix = (TARGET_UNDERSCORES) ? "_" : ""; \
- const char *const lprefix = LPREFIX; \
- int labelno = LABELNO; \
- \
- /* Note that OSF/rose blew it in terms of calling mcount, \
- since OSF/rose prepends a leading underscore, but mcount's \
- doesn't. At present, we keep this kludge for ELF as well \
- to allow old kernels to build profiling. */ \
- \
- if (flag_pic \
- && !current_function_uses_pic_offset_table \
- && !current_function_uses_const_pool) \
- abort (); \
- \
- if (TARGET_MCOUNT && flag_pic) \
- { \
- fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \
- lprefix, labelno); \
- fprintf (FILE, "\tcall *%smcount@GOT(%%ebx)\n", prefix); \
- } \
- \
- else if (TARGET_MCOUNT && HALF_PIC_P ()) \
- { \
- rtx symdef; \
- \
- HALF_PIC_EXTERNAL ("mcount"); \
- symdef = HALF_PIC_PTR (gen_rtx_SYMBOL_REF (Pmode, "mcount")); \
- fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \
- fprintf (FILE, "\tcall *%s%s\n", prefix, XSTR (symdef, 0)); \
- } \
- \
- else if (TARGET_MCOUNT) \
- { \
- fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \
- fprintf (FILE, "\tcall %smcount\n", prefix); \
- } \
- \
- else if (flag_pic && frame_pointer_needed) \
- { \
- fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \
- fprintf (FILE, "\tpushl %%ecx\n"); \
- fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \
- lprefix, labelno); \
- fprintf (FILE, "\tmovl _mcount_ptr@GOT(%%ebx),%%eax\n"); \
- fprintf (FILE, "\tcall *(%%eax)\n"); \
- fprintf (FILE, "\tpopl %%eax\n"); \
- } \
- \
- else if (frame_pointer_needed) \
- { \
- fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \
- fprintf (FILE, "\tpushl %%ecx\n"); \
- fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \
- fprintf (FILE, "\tcall *_mcount_ptr\n"); \
- fprintf (FILE, "\tpopl %%eax\n"); \
- } \
- \
- else \
- abort (); \
- } \
- } \
-while (0)
-
-/* A C function or functions which are needed in the library to
- support block profiling. When support goes into libc, undo
- the #if 0. */
-
-#if 0
-#undef BLOCK_PROFILING_CODE
-#define BLOCK_PROFILING_CODE
-#endif
-
-/* Prefix for internally generated assembler labels. If we aren't using
- underscores, we are using prefix `.'s to identify labels that should
- be ignored, as in `i386/gas.h' --karl@cs.umb.edu */
-#undef LPREFIX
-#define LPREFIX ((TARGET_UNDERSCORES) ? "L" : ".L")
-
-/* This is how to store into the string BUF
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \
- sprintf ((BUF), "*%s%s%ld", (TARGET_UNDERSCORES) ? "" : ".", \
- (PREFIX), (long)(NUMBER))
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, "%s%s%d:\n", (TARGET_UNDERSCORES) ? "" : ".", \
- PREFIX, NUM)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-/* target_flags is not accessible by the preprocessor */
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output a reference to a user-level label named NAME. */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE,NAME) \
- fprintf (FILE, "%s%s", (TARGET_UNDERSCORES) ? "_" : "", NAME)
-
-/* This is how to output an element of a case-vector that is relative.
- This is only used for PIC code. See comments by the `casesi' insn in
- i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Output a definition */
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
-do \
-{ \
- fprintf ((FILE), "%s", SET_ASM_OP); \
- assemble_name (FILE, LABEL1); \
- fprintf (FILE, ","); \
- assemble_name (FILE, LABEL2); \
- fprintf (FILE, "\n"); \
- } \
-while (0)
-
-/* A C expression to output text to align the location counter in the
- way that is desirable at a point in the code that is reached only
- by jumping.
-
- This macro need not be defined if you don't want any special
- alignment to be done at such a time. Most machine descriptions do
- not currently define the macro. */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
- ((!TARGET_LARGE_ALIGN && i386_align_jumps > 2) ? 2 : i386_align_jumps)
-
-/* A C expression to output text to align the location counter in the
- way that is desirable at the beginning of a loop.
-
- This macro need not be defined if you don't want any special
- alignment to be done at such a time. Most machine descriptions do
- not currently define the macro. */
-
-#undef LOOP_ALIGN
-#define LOOP_ALIGN(LABEL) (i386_align_loops)
-
-/* A C statement to output to the stdio stream STREAM an assembler
- command to advance the location counter to a multiple of 2 to the
- POWER bytes. POWER will be a C expression of type `int'. */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
- fprintf (STREAM, "\t.align\t%d\n", \
- (!TARGET_LARGE_ALIGN && (POWER) > 2) ? 2 : (POWER))
-
-/* A C expression that is 1 if the RTX X is a constant which is a
- valid address. On most machines, this can be defined as
- `CONSTANT_P (X)', but a few machines are more restrictive in
- which constant addresses are supported.
-
- `CONSTANT_P' accepts integer-values expressions whose values are
- not explicitly known, such as `symbol_ref', `label_ref', and
- `high' expressions and `const' arithmetic expressions, in
- addition to `const_int' and `const_double' expressions. */
-
-#define CONSTANT_ADDRESS_P_ORIG(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
-
-#undef CONSTANT_ADDRESS_P
-#define CONSTANT_ADDRESS_P(X) \
- ((CONSTANT_ADDRESS_P_ORIG (X)) && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-
-#undef LEGITIMATE_CONSTANT_P
-#define LEGITIMATE_CONSTANT_P(X) \
- (!HALF_PIC_P () \
- || GET_CODE (X) == CONST_DOUBLE \
- || GET_CODE (X) == CONST_INT \
- || !HALF_PIC_ADDRESS_P (X))
-
-/* Sometimes certain combinations of command options do not make sense
- on a particular target machine. You can define a macro
- `OVERRIDE_OPTIONS' to take account of this. This macro, if
- defined, is executed once just after all the command options have
- been parsed. */
-
-#undef SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS \
-{ \
- /* \
- if (TARGET_ELF && TARGET_HALF_PIC) \
- { \
- target_flags &= ~MASK_HALF_PIC; \
- flag_pic = 1; \
- } \
- */ \
- \
- if (TARGET_ROSE && flag_pic) \
- { \
- target_flags |= MASK_HALF_PIC; \
- flag_pic = 0; \
- } \
- \
- if (TARGET_HALF_PIC) \
- half_pic_init (); \
-}
-
-/* Define this macro if references to a symbol must be treated
- differently depending on something about the variable or
- function named by the symbol (such as what section it is in).
-
- The macro definition, if any, is executed immediately after the
- rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
- The value of the rtl will be a `mem' whose address is a
- `symbol_ref'.
-
- The usual thing for this macro to do is to a flag in the
- `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
- name string in the `symbol_ref' (if one bit is not enough
- information).
-
- The best way to modify the name string is by adding text to the
- beginning, with suitable punctuation to prevent any ambiguity.
- Allocate the new name in `saveable_obstack'. You will have to
- modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
- and output the name accordingly.
-
- You can also check the information stored in the `symbol_ref' in
- the definition of `GO_IF_LEGITIMATE_ADDRESS' or
- `PRINT_OPERAND_ADDRESS'. */
-
-#undef ENCODE_SECTION_INFO
-#define ENCODE_SECTION_INFO(DECL, FIRST) \
-do \
- { \
- if (HALF_PIC_P ()) \
- { \
- if (FIRST) \
- HALF_PIC_ENCODE (DECL); \
- } \
- else if (flag_pic) \
- { \
- rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
- ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
- SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
- = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
- || ! TREE_PUBLIC (DECL)); \
- } \
- } \
-while (0)
-
-#undef SELECT_SECTION
-#define SELECT_SECTION(DECL, RELOC, ALIGN) \
-{ \
- if (RELOC && HALF_PIC_P ()) \
- data_section (); \
- \
- else if (TREE_CODE (DECL) == STRING_CST) \
- { \
- if (flag_writable_strings) \
- data_section (); \
- else \
- readonly_data_section (); \
- } \
- \
- else if (TREE_CODE (DECL) != VAR_DECL) \
- readonly_data_section (); \
- \
- else if (!TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \
- || !DECL_INITIAL (DECL) \
- || (DECL_INITIAL (DECL) != error_mark_node \
- && !TREE_CONSTANT (DECL_INITIAL (DECL)))) \
- data_section (); \
- \
- else \
- readonly_data_section (); \
-}
-
-
-/* Define the strings used for the special svr4 .type and .size directives.
- These strings generally do not vary from one system running svr4 to
- another, but if a given system (e.g. m88k running svr) needs to use
- different pseudo-op names for these, they may be overridden in the
- file which includes this one. */
-
-#define TYPE_ASM_OP "\t.type\t"
-#define SIZE_ASM_OP "\t.size\t"
-#define SET_ASM_OP "\t.set\t"
-
-/* This is how we tell the assembler that a symbol is weak. */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
- do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
- fputc ('\n', FILE); } while (0)
-
-/* The following macro defines the format used to output the second
- operand of the .type assembler directive. Different svr4 assemblers
- expect various different forms for this operand. The one given here
- is just a default. You may need to override it in your machine-
- specific tm.h file (depending upon the particulars of your assembler). */
-
-#define TYPE_OPERAND_FMT "@%s"
-
-/* A C statement (sans semicolon) to output to the stdio stream
- STREAM any text necessary for declaring the name NAME of an
- initialized variable which is being defined. This macro must
- output the label definition (perhaps using `ASM_OUTPUT_LABEL').
- The argument DECL is the `VAR_DECL' tree node representing the
- variable.
-
- If this macro is not defined, then the variable name is defined
- in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
-do \
- { \
- ASM_OUTPUT_LABEL(STREAM,NAME); \
- HALF_PIC_DECLARE (NAME); \
- if (TARGET_ELF) \
- { \
- fprintf (STREAM, "%s", TYPE_ASM_OP); \
- assemble_name (STREAM, NAME); \
- putc (',', STREAM); \
- fprintf (STREAM, TYPE_OPERAND_FMT, "object"); \
- putc ('\n', STREAM); \
- size_directive_output = 0; \
- if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \
- { \
- size_directive_output = 1; \
- fprintf (STREAM, "%s", SIZE_ASM_OP); \
- assemble_name (STREAM, NAME); \
- fprintf (STREAM, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \
- } \
- } \
- } \
-while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
- in the case where we did not do so before the initializer.
- Once we find the error_mark_node, we know that the value of
- size_directive_output was set
- by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
-do { \
- const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
- if (TARGET_ELF \
- && !flag_inhibit_size_directive && DECL_SIZE (DECL) \
- && ! AT_END && TOP_LEVEL \
- && DECL_INITIAL (DECL) == error_mark_node \
- && !size_directive_output) \
- { \
- fprintf (FILE, "%s", SIZE_ASM_OP); \
- assemble_name (FILE, name); \
- fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \
- } \
- } while (0)
-
-/* This is how to declare a function name. */
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
-do \
- { \
- ASM_OUTPUT_LABEL(STREAM,NAME); \
- HALF_PIC_DECLARE (NAME); \
- if (TARGET_ELF) \
- { \
- fprintf (STREAM, "%s", TYPE_ASM_OP); \
- assemble_name (STREAM, NAME); \
- putc (',', STREAM); \
- fprintf (STREAM, TYPE_OPERAND_FMT, "function"); \
- putc ('\n', STREAM); \
- ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL)); \
- } \
- } \
-while (0)
-
-/* Write the extra assembler code needed to declare a function's result.
- Most svr4 assemblers don't require any special declaration of the
- result value, but there are exceptions. */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* This is how to declare the size of a function. */
-
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
-do \
- { \
- if (TARGET_ELF && !flag_inhibit_size_directive) \
- { \
- char label[256]; \
- static int labelno; \
- labelno++; \
- ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \
- ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \
- fprintf (FILE, "%s", SIZE_ASM_OP); \
- assemble_name (FILE, (FNAME)); \
- fprintf (FILE, ","); \
- assemble_name (FILE, label); \
- fprintf (FILE, "-"); \
- assemble_name (FILE, (FNAME)); \
- putc ('\n', FILE); \
- } \
- } \
-while (0)
-
-#define IDENT_ASM_OP "\t.ident\t"
-
-/* Allow #sccs in preprocessor. */
-
-#define SCCS_DIRECTIVE
-
-/* This says what to print at the end of the assembly file */
-#undef ASM_FILE_END
-#define ASM_FILE_END(STREAM) \
-do \
- { \
- if (HALF_PIC_P ()) \
- HALF_PIC_FINISH (STREAM); \
- ix86_asm_file_end (STREAM); \
- } \
-while (0)
-
-/* Tell collect that the object format is OSF/rose. */
-#define OBJECT_FORMAT_ROSE
-
-/* Tell collect where the appropriate binaries are. */
-#define REAL_NM_FILE_NAME "/usr/ccs/gcc/bfd-nm"
-#define REAL_STRIP_FILE_NAME "/usr/ccs/bin/strip"
-
-/* Define this macro meaning that gcc should find the library 'libgcc.a'
- by hand, rather than passing the argument '-lgcc' to tell the linker
- to do the search */
-#define LINK_LIBGCC_SPECIAL
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
- we want to retain compatibility with older gcc versions. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Map i386 registers to the numbers dwarf expects. Of course this is
- different from what stabs expects. */
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) ((write_symbols == DWARF_DEBUG) \
- ? svr4_dbx_register_map[n] \
- : dbx_register_map[n])
+++ /dev/null
-/* Definitions for rtems targeting an Intel i386 using coff.
- Copyright (C) 1996, 1997, 2000, 2002 Free Software Foundation, Inc.
- Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Specify predefined symbols in preprocessor. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__rtems__ -Asystem=rtems"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (80386, RTEMS)");
+++ /dev/null
-/* Definitions for Sequent Intel 386 using GAS.
- Copyright (C) 1992, 2002 Free Software Foundation, Inc.
-
-/* Mostly it's like a Sequent 386 without GAS. */
-
-/* A C statement or statements which output an assembler instruction
- opcode to the stdio stream STREAM. The macro-operand PTR is a
- variable of type `char *' which points to the opcode name in its
- "internal" form--the form that is written in the machine description.
-
- GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic.
- So use `repe' instead. */
-
-#undef ASM_OUTPUT_OPCODE
-#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
-{ \
- if ((PTR)[0] == 'r' \
- && (PTR)[1] == 'e' \
- && (PTR)[2] == 'p') \
- { \
- if ((PTR)[3] == 'z') \
- { \
- fprintf (STREAM, "repe"); \
- (PTR) += 4; \
- } \
- else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \
- { \
- fprintf (STREAM, "repne"); \
- (PTR) += 5; \
- } \
- } \
-}
-
-/* Define macro used to output shift-double opcodes when the shift
- count is in %cl. Some assemblers require %cl as an argument;
- some don't.
-
- GAS requires the %cl argument, so override i386/unix.h. */
-
-#undef SHIFT_DOUBLE_OMITS_COUNT
-#define SHIFT_DOUBLE_OMITS_COUNT 0
-
-/* Print opcodes the way that GAS expects them. */
-#define GAS_MNEMONICS 1
+++ /dev/null
-/* Sequent DYNIX/ptx 1.x (SVr3) */
-
-#define TARGET_VERSION fprintf (stderr, " (80386, ATT syntax)");
-
-/* Sequent Symmetry SVr3 doesn't have crtn.o; crt1.o doesn't work
- but crt0.o does. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-"%{pg:gcrt0.o%s}\
- %{!pg:%{posix:%{p:mcrtp0.o%s}%{!p:crtp0.o%s}}\
- %{!posix:%{p:mcrt0.o%s}%{!p:crt0.o%s}}} crtbegin.o%s\
- %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}"
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-"%{posix:-lcposix}\
- %{shlib:-lc_s}\
- %{fshared-data:-lpps -lseq} -lc crtend.o%s"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE} -D_SEQUENT_=1"
-
-/* Although the .init section is used, it is not automatically invoked.
- This because the _start() function in /lib/crt0.o never calls anything
- from the .init section */
-#define INVOKE__main
-
-/* Assembler pseudo-op for initialized shared variables (.shdata). */
-#undef SHARED_SECTION_ASM_OP
-#define SHARED_SECTION_ASM_OP "\t.section .shdata, \"ws\""
-
-/* Assembler pseudo-op for uninitialized shared global variables (.shbss). */
-#undef ASM_OUTPUT_SHARED_COMMON
-#define ASM_OUTPUT_SHARED_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs(".comm ", (FILE)), \
- assemble_name((FILE), (NAME)), \
- fprintf((FILE), ",%u,-3\n", (SIZE)))
-
-/* Assembler pseudo-op for uninitialized shared local variables (.shbss). */
-#undef SHARED_BSS_SECTION_ASM_OP
-#define SHARED_BSS_SECTION_ASM_OP "\t.section .shbss, \"bs\""
-
-/* seq2-sysv3.h used to define HAVE_ATEXIT, so I assume ptx1 needs this... */
-#define NEED_ATEXIT
+++ /dev/null
-/* Sequent DYNIX/ptx 2.x (SVr3) */
-
-/* Use atexit for static destructors, instead of defining
- our own exit function. */
-#undef NEED_ATEXIT
+++ /dev/null
-/* Definitions for Sequent Intel 386 using BSD assembler syntax
- (actually AT&T syntax for insns and operands,
- adapted to BSD conventions for symbol names and debugging.)
- Copyright (C) 1988, 1994, 1996, 1999, 2000, 2002
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define TARGET_VERSION fprintf (stderr, " (80386, BSD syntax)");
-
-/* By default, don't use IEEE compatible arithmetic comparisons
- because the assembler can't handle the fucom insn.
- Return float values in the 387. */
-
-#undef TARGET_SUBTARGET_DEFAULT
-#define TARGET_SUBTARGET_DEFAULT (MASK_80387 | MASK_FLOAT_RETURNS)
-
-/* Specify predefined symbols in preprocessor. */
-
-#define CPP_PREDEFINES "-Dunix -Dsequent -Asystem=unix"
-
-/* Pass -Z and -ZO options to the linker. */
-
-#define LINK_SPEC "%{Z*}"
-
-#if 0 /* Dynix 3.1 is said to accept -L. */
-/* Dynix V3.0.12 doesn't accept -L at all. */
-
-#define LINK_LIBGCC_SPECIAL
-#endif
-
-/* Link with libg.a when debugging, for dbx's sake. */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* We don't want to output SDB debugging information. */
-
-#undef SDB_DEBUGGING_INFO
-
-/* We want to output DBX debugging information. */
-
-#define DBX_DEBUGGING_INFO
-
-/* Sequent Symmetry has size_t defined as int in /usr/include/sys/types.h */
-#define SIZE_TYPE "int"
-
-/* gcc order is ax, dx, cx, bx, si, di, bp, sp, st, st.
- * dbx order is ax, dx, cx, st(0), st(1), bx, si, di, st(2), st(3),
- * st(4), st(5), st(6), st(7), sp, bp */
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-((n) < 3 ? (n) : (n) < 6 ? (n) + 2 \
- : (n) == 6 ? 15 : (n) == 7 ? 14 : 3)
-
-/* malcolmp@hydra.maths.unsw.EDU.AU says these two definitions
- fix trouble in dbx. */
-#undef DBX_OUTPUT_LBRAC
-#define DBX_OUTPUT_LBRAC(file,name) \
- fprintf (asmfile, "%s%d,0,%d,", ASM_STABN_OP, N_LBRAC, depth); \
- assemble_name (asmfile, buf); \
- fprintf (asmfile, "\n");
-
-#undef DBX_OUTPUT_RBRAC
-#define DBX_OUTPUT_RBRAC(file,name) \
- fprintf (asmfile, "%s%d,0,%d,", ASM_STABN_OP, N_RBRAC, depth); \
- assemble_name (asmfile, buf); \
- fprintf (asmfile, "\n");
-
-/* Prevent anything from being allocated in the register pair cx/bx,
- since that would confuse GDB. */
-
-#undef HARD_REGNO_MODE_OK
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (((REGNO) < 2 ? 1 \
- : (REGNO) < 4 ? 1 \
- : FP_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_FLOAT \
- || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
- : (MODE) != QImode) \
- && ! (REGNO == 2 && GET_MODE_UNIT_SIZE (MODE) > 4))
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tmovl $.LP%d,%%eax\n\tcall mcount\n", (LABELNO));
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP "\t.shdata"
-
-/* A C statement or statements which output an assembler instruction
- opcode to the stdio stream STREAM. The macro-operand PTR is a
- variable of type `char *' which points to the opcode name in its
- "internal" form--the form that is written in the machine description.
-
- The Sequent assembler (identified as "Balance 8000 Assembler
- 07/17/85 3.90" by "as -v") does not understand the `movs[bwl]' string
- move mnemonics - it uses `smov[bwl]' instead. Change "movs" into
- "smov", carefully avoiding the sign-extend opcodes. */
-
-#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
-{ \
- if ((PTR)[0] == 'm' \
- && (PTR)[1] == 'o' \
- && (PTR)[2] == 'v' \
- && (PTR)[3] == 's' \
- && ((PTR)[4] == 'b' || (PTR)[4] == 'w' || (PTR)[4] == 'l') \
- && ((PTR)[5] == ' ' || (PTR)[5] == '\t'|| (PTR)[5] == '\0')) \
- { \
- fprintf (STREAM, "smov"); \
- (PTR) += 4; \
- } \
-}
-
-/* 10-Aug-92 pes Local labels are prefixed with ".L" */
-#undef LPREFIX
-#define LPREFIX ".L"
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)\
- sprintf ((BUF), "*.%s%ld", (PREFIX), (long)(NUMBER))
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)\
- fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* The native compiler passes the address of the returned structure in eax. */
-#undef STRUCT_VALUE
-#undef STRUCT_VALUE_INCOMING
-#define STRUCT_VALUE_REGNUM 0
+++ /dev/null
-/* Definitions for Intel 386 running SunOS 4.0.
- Copyright (C) 1988, 1995, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Use's the Sun assembler syntax. */
-
-/* Use crt0.o as a startup file. */
-
-#define STARTFILE_SPEC \
- "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{g:-lg} %{sun386:}"
-/* That last item is just to prevent a spurious error. */
-
-#undef LINK_SPEC
-#define LINK_SPEC \
- "%{!nostdlib:%{!r*:%{!e*:-e _start}}} -dc -dp %{static:-Bstatic}"
-
-/* Extra switches to give the assembler. */
-
-#define ASM_SPEC "%{R} -i386 %{keep-local-as-symbols:-L}"
-
-/* Specify predefined symbols in preprocessor. */
-
-#define CPP_PREDEFINES "-Dunix -Dsun386 -Dsun -Asystem=unix -Asystem=bsd"
-
-/* Allow #sccs in preprocessor. */
-
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident. */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* We don't want to output SDB debugging information. */
-
-#undef SDB_DEBUGGING_INFO
-
-/* We want to output DBX debugging information. */
-
-#define DBX_DEBUGGING_INFO
-
-/* Implicit library calls should use memcpy, not bcopy, etc. */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Force structure alignment to the type used for a bitfield. */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* This is partly guess. */
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
- ((n) == 0 ? 11 : (n) == 1 ? 9 : (n) == 2 ? 10 : (n) == 3 ? 8 \
- : (n) == 4 ? 5 : (n) == 5 ? 4 : (n) == 6 ? 6 : (n))
-
-/* Every debugger symbol must be in the text section.
- Otherwise the assembler or the linker screws up. */
-
-#define DEBUG_SYMS_TEXT
+++ /dev/null
-/* Definitions for Sun assembler syntax for the Intel 80386.
- Copyright (C) 1988, 1996, 2000, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-#define TARGET_VERSION fprintf (stderr, " (80386, Sun syntax)");
-
-/* Define the syntax of instructions and addresses. */
-
-/* Prefix for internally generated assembler labels. */
-#define LPREFIX ".L"
-
-/* Define the syntax of pseudo-ops, labels and comments. */
-
-/* Assembler pseudos to introduce constants of various size. */
-
-#define ASM_SHORT "\t.value\t"
-#define ASM_LONG "\t.long\t"
-#define ASM_QUAD "\t.quad\t" /* Should not be used for 32bit compilation. */
-
-
-/* How to output an ASCII string constant. */
-
-#define ASM_OUTPUT_ASCII(FILE, PTR, SIZE) \
-do \
-{ size_t i = 0, limit = (SIZE); \
- while (i < limit) \
- { if (i%10 == 0) { if (i!=0) fprintf ((FILE), "\n"); \
- fputs ("\t.byte\t", (FILE)); } \
- else fprintf ((FILE), ","); \
- fprintf ((FILE), "0x%x", ((PTR)[i++] & 0377)) ;} \
- fprintf ((FILE), "\n"); \
-} while (0)
-
-/* Output at beginning of assembler file. */
-/* The .file command should always begin the output. */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
- do { \
- { \
- const int len = strlen (main_input_filename); \
- const char *na = main_input_filename + len; \
- char shorter[15]; \
- /* NA gets MAIN_INPUT_FILENAME sans directory names. */\
- while (na > main_input_filename) \
- { \
- if (na[-1] == '/') \
- break; \
- na--; \
- } \
- strncpy (shorter, na, 14); \
- shorter[14] = 0; \
- fprintf (FILE, "\t.file\t"); \
- output_quoted_string (FILE, shorter); \
- fprintf (FILE, "\n"); \
- } \
- fprintf (FILE, "\t.version\t\"%s %s\"\n", \
- lang_hooks.name, version_string); \
- if (optimize) ASM_FILE_START_1 (FILE); \
- } while (0)
-
-#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.optim\n")
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG))
-
-/* This is how to output an assembler line
- that says to advance the location counter by SIZE bytes. */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE))
-
-/* Output before read-only data. */
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-/* Output before writable data. */
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* Define the syntax of labels and symbol definitions/declarations. */
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This is how to store into the string BUF
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \
- sprintf ((BUF), "*.%s%ld", (PREFIX), (long)(NUMBER))
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
+++ /dev/null
-#
-# target makefile for dgux
-#
-EXTRA_PARTS=crti.o crtbegin.o crtend.o
-
-crti.o: $(srcdir)/config/i386/sol2-ci.asm $(GCC_PASSES)
- sed -e '/^!/d' <$(srcdir)/config/i386/sol2-ci.asm >crti.s
- $(GCC_FOR_TARGET) -c -o crti.o crti.s
-
-# Don't run fixproto
-STMP_FIXPROTO =
+++ /dev/null
-# Specify other dirs of system header files to be fixed.
-OTHER_FIXINCLUDES_DIRS= /LocalDeveloper/Headers
-
-# <limits.h> is sometimes in /usr/include/ansi/limits.h.
-LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h -o -f $(SYSTEM_HEADER_DIR)/ansi/limits.h ]
-
-nextstep.o: $(srcdir)/config/nextstep.c $(CONFIG_H) flags.h tree.h
- $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/nextstep.c
+++ /dev/null
-# If compiling with the osf gcc, avoid sharing code.
-TCFLAGS = -pic-none
+++ /dev/null
-# Assemble startup files.
-crti.o: $(srcdir)/config/i386/osf1-ci.asm $(GCC_PASSES)
- sed -e '/^!/d' <$(srcdir)/config/i386/osf1-ci.asm >crti.s
- $(GCC_FOR_TARGET) -c -o crti.o crti.s
-crtn.o: $(srcdir)/config/i386/osf1-cn.asm $(GCC_PASSES)
- sed -e '/^!/d' <$(srcdir)/config/i386/osf1-cn.asm >crtn.s
- $(GCC_FOR_TARGET) -c -o crtn.o crtn.s
-
-# The pushl in CTOR initialization interferes with frame pointer elimination.
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c. This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-CRTSTUFF_T_CFLAGS = -fPIC -fno-omit-frame-pointer
-TARGET_LIBGCC2_CFLAGS = -fPIC
+++ /dev/null
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP "\t.ascii\t"
+++ /dev/null
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860, BSD)")
-
-/* BSD UN*X systems use BSD STABS debugging info. */
-
-#define DBX_DEBUGGING_INFO
-
-#define ASCII_DATA_ASM_OP "\t.byte\t"
-#define ASM_OUTPUT_ASCII(f, p, size) \
-do { register size_t i, limit = (size); \
- int inside; \
- inside = FALSE; \
- for (i = 0; i < limit; i++) { \
- if (i % 64 == 0) { \
- if (i != 0) { \
- if (inside) \
- putc('"', (f)); \
- putc('\n', (f)); \
- inside = FALSE; \
- } \
- fprintf((f), "%s", ASCII_DATA_ASM_OP); \
- } \
- if ((p)[i] < 32 || (p)[i] == '\\' || (p)[i] == '"' || (p)[i] >= 127) { \
- if (inside) { \
- putc('"', (f)); \
- inside = FALSE; \
- } \
- if (i % 64 != 0) \
- putc(',', (f)); \
- fprintf((f), "%d", (p)[i]); \
- } else { \
- if (!inside) { \
- if (i % 64 != 0) \
- putc(',', (f)); \
- putc('"', (f)); \
- inside = TRUE; \
- } \
- putc((p)[i], (f)); \
- } \
- } \
- if (inside) \
- putc('"', (f)); \
- putc('\n', (f)); \
-} while (0)
+++ /dev/null
-/* Target definitions for GNU compiler for Alliant FX/2800
- running Concentrix 2.2
- Copyright (C) 1991, 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
- Contributed by Howard Chu (hyc@hanauma.jpl.nasa.gov).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* The Alliant fx2800 running Concentrix 2.x is weird. This is basically
- a BSD 4.3 based operating system, but it uses svr4 ELF format object
- files and it somehow puts BSD stabs records into the ELF files for
- symbolic debug information. The assembler is "mostly an SVR4 assembler
- with some Alliant additions. We based it on the `Intel 80860 Assembly
- Language Specification' from AT&T." */
-
-/* This file consists of three sections. The first section establishes
- definitions unique to the Alliant FX/2800. The next section reconciles
- differences between Alliant and i860v4.h, and the last overrides the
- remaining differences with svr4.h */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 Alliant)");
-
-/* atexit is not present prior to Concentrix 2.2. Uncomment the following
- if you're on 2.1 or older. */
-
-/* #define NEED_ATEXIT */
-
-#define I860_STRICT_ABI_PROLOGUES
-
-/* There is no avoiding this; -L does not exist at all (in Concentrix 2.2). */
-#define LINK_LIBGCC_SPECIAL 1
-
-/* Most of the Alliant-specific definitions here are to get stab info that
- Alliant's dbx can understand. */
-
-#define DBX_DEBUGGING_INFO
-#define DEFAULT_GDB_EXTENSIONS 0
-#define DBX_NO_XREFS
-#define DBX_NO_EXTRA_TAGS
-
-/* Alliant dbx also needs to see the function stab before anything
- else in the function. */
-
-#define DBX_FUNCTION_FIRST
-#define DBX_LBRAC_FIRST
-
-/* Alliant dbx also needs to see the end of a function somewhere. */
-
-#define DBX_OUTPUT_FUNCTION_END(file,decl) \
- fprintf (file, ".stab \"\",.,0x%x,0,0\n", N_EFUN)
-
-/* Alliant dbx has predefined types, so they must be emitted with the
- proper type numbers. The defined types are:
-
- Type # C, Fortran, Pascal Types
- -- ------------------------
- 1 char, integer*1
- 2 short, integer*2
- 3 int, long, integer*4, integer
- 4 logical*1, byte
- 5 logical*2
- 6 logical*4, logical
- 7 float, real*4, real
- 8 double, real*8, double
- 9 single complex, complex*8, complex
- 10 double complex, doublecomplex
- 11 character
- 12 void
- 13 nil
- 14 boolean
- 15 unsigned char, ubyte
- 16 unsigned short, uword
- 17 unsigned, unsigned int, unsigned long, ulong
- 18 quad, logical*8
- 19 long long, integer*8
- 20 unsigned long long, uquad*8
- 21-100 reserved for future predefined types
- 100 long redefine same as 3
- 101 unsigned long same as 17
- -- --------------------
- 102 First user program type
-
- Since long and unsigned long are int references, they must be handled
- as special cases. The Alliant compiler doesn't use types 18-20, so it
- sets long & unsigned long in 18 & 19, not in 100 & 101 as shown above. */
-
-#define DBX_OUTPUT_STANDARD_TYPES(syms) \
-{ static const char *const dtyps[] = { \
- "", "char", "short int", "int", "logical*1", \
- "logical*2", "logical*4", "float", "double", "complex", \
- "doublecomplex", "character", "void", "nil", "boolean", \
- "unsigned char", "short unsigned int", "unsigned int", \
- "logical*8", "long long int", "long long unsigned int",""}; \
- \
- tree decl; \
- int i; \
- \
- for (i=1;*dtyps[i];i++) \
- for (decl = syms; decl; decl = TREE_CHAIN(decl)) \
- if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) && \
- !strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)), dtyps[i])) { \
- TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \
- typevec[i] = TYPE_DEFINED; \
- dbxout_symbol (decl, 0); \
- break; \
- } \
- \
- for (decl = syms; decl; decl = TREE_CHAIN(decl)) \
- if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) && \
- !strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)),"long int")) { \
- TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \
- typevec[i] = TYPE_DEFINED; \
- fprintf(asmfile,".stab \"long int:t%d=3\",0,0x%x,0,0\n", \
- i++,N_LSYM); \
- TREE_ASM_WRITTEN (decl) = 1; \
- break; \
- } \
- \
- for (decl = syms; decl; decl = TREE_CHAIN(decl)) \
- if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) && !strcmp( \
- IDENTIFIER_POINTER(DECL_NAME(decl)),"long unsigned int")) { \
- TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \
- typevec[i] = TYPE_DEFINED; \
- fprintf(asmfile,".stab \"long unsigned int:t%d=17\",0,0x%x,0,0\n",\
- i++,N_LSYM); \
- TREE_ASM_WRITTEN (decl) = 1; \
- break; \
- } \
- next_type_number = i; };
-
-/* Alliant dbx doesn't understand split names... */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* The syntax for stabs records is also different; there is only a single
- ".stab" directive instead of the 3 directives in BSD, and the order of
- arguments is slightly changed. */
-
-#define ASM_STABS_OP "\t.stab "
-#define ASM_STABN_OP "\t.stab "
-#define ASM_STABD_OP "\t.stab "
-
-#define DBX_MEMPARM_STABS_LETTER 'k'
-#define DBX_REGPARM_STABS_LETTER 'r'
-
-#undef ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file,num) \
- fprintf (file, "\t.stab \"\",.,0x%x,0,%d\n", \
- N_SLINE,num)
-
-#if 0 /* Alliant dbx only reads first N_SO, so it
- ignores the filename if dir is present. */
-#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name) \
- fprintf (file, ".stab \"%s/\",.Ltext0,0x%x,0,0\n", \
- name, N_SO)
-#else
-#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name)
-#endif
-
-#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(file,name) \
- fprintf (file, ".stab "); \
- output_quoted_string (file, name); \
- fprintf (file, ",.Ltext0,0x%x,0,0\n", N_SO); \
- text_section (); \
- ASM_OUTPUT_INTERNAL_LABEL (file, "Ltext", 0)
-
-#define DBX_OUTPUT_SOURCE_FILENAME(file,name) \
- do { fprintf (file, ".stab "); \
- output_quoted_string (file, name); \
- fprintf (file, ",.Ltext0,0x%x,0,0\n", N_SOL); \
- } while (0)
-
-#define DBX_OUTPUT_CONSTANT_SYMBOL(file,name,ival) \
- fprintf (file, ".stab \"%s:c=i%d\",0,0x%x,0,0\n", \
- name, ival, N_LSYM)
-
-#define DBX_FINISH_SYMBOL(decl) \
- int line = 0; \
- fprintf (asmfile, "\","); \
- if (current_sym_addr) \
- output_addr_const (asmfile, current_sym_addr); \
- else \
- fprintf (asmfile, "%d", current_sym_value); \
- if (decl != 0 && TREE_CODE(decl) == FUNCTION_DECL) \
- line=DECL_SOURCE_LINE (decl); \
- fprintf (asmfile, ",0x%x,%d,%d\n", current_sym_code, \
- line!=0?64:0,line)
-
-#define DBX_OUTPUT_CATCH(file,decl,name) \
- fprintf (file, ".stab \"%s:C1\",", \
- IDENTIFIER_POINTER (DECL_NAME (decl))); \
- assemble_name (file, name); \
- fprintf (file, ",0x%x,0,0\n", N_CATCH)
-
-#define DBX_OUTPUT_LBRAC(file,name) \
- if (depth > 1) { \
- fprintf (file, ".stab \"\","); \
- assemble_name (file, name); \
- fprintf (file, ",0x%x,0,%d\n", N_LBRAC, depth); }
-
-#define DBX_OUTPUT_RBRAC(file,name) \
- if (depth > 1) { \
- fprintf (file, ".stab \"\","); \
- assemble_name (file, name); \
- fprintf (file, ",0x%x,0,%d\n", N_RBRAC, depth); }
-
-#define DBX_OUTPUT_ENUM(file,type) \
- fprintf (file, "e3"); \
- CHARS(2); \
- for (tem = TYPE_VALUES (type); tem; tem = TREE_CHAIN (tem)) \
- { \
- fprintf (asmfile, "%s:%d,", \
- IDENTIFIER_POINTER (TREE_PURPOSE (tem)), \
- TREE_INT_CST_LOW (TREE_VALUE (tem))); \
- CHARS (11 + IDENTIFIER_LENGTH (TREE_PURPOSE (tem))); \
- if (TREE_CHAIN (tem) != 0) \
- CONTIN; \
- } \
- putc (';', asmfile); \
- CHARS (1);
-
-/* Undefine some things defined in i860.h because the native C compiler
- on the FX/2800 emits code to do these operations inline. For GCC,
- we will use the default implementation of these things... i.e.
- generating calls to libgcc routines. */
-
-#undef DIVSI3_LIBCALL
-#undef UDIVSI3_LIBCALL
-#undef REMSI3_LIBCALL
-#undef UREMSI3_LIBCALL
-
-/* Global pointer needs to be 8 byte aligned? Link error if not... */
-
-#define DATA_ALIGNMENT(dummy,align) \
- ((TREE_PUBLIC (decl) && \
- (POINTER_TYPE_P (TREE_TYPE (decl)))) ? 64: align)
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tcall __mcount_\n\tnop\n")
-
-/* Overrides for i860v4.h begin here */
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
- the i860 running Concentrix 2.x. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di860 -Dunix -DBSD4_3 -Dalliant -Asystem=unix -Asystem=bsd -Acpu=i860 -Amachine=i860"
-
-#undef I860_REG_PREFIX
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "//"
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)
-#undef ASM_OUTPUT_FUNCTION_PREFIX
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
- fputs("\tnop\n", (FILE)); \
- current_function_original_name = (NAME)
-#undef ASM_OUTPUT_PROLOGUE_SUFFIX
-
-/* Overrides for svr4.h begin here */
-
-#undef SWITCH_TAKES_ARG
-#undef WORD_SWITCH_TAKES_ARG
-
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#undef MD_STARTFILE_PREFIX
-#undef MD_EXEC_PREFIX
-
-/* Generate an error message if -p option is selected. Concentrix 2.x
- does not support prof format profiling, only gprof is supported. */
-
-#define CPP_SPEC "%{p:%e-p option not supported: use -pg instead}"
-
-/* Provide an appropriate LIB_SPEC. The crtend.o file provides part of the
- support for getting C++ file-scope static objects constructed before
- entering `main'. */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
- "%{g*:-lg} %{!pg:-lc}%{pg:-lc_p} crtend.o%s"
-
-/* Tell linker to strip local symbols, since assembler may not. */
-
-#undef LINK_SPEC
-#define LINK_SPEC "-X"
-
-/* Get the correct startup file for regular or profiled code. Also
- use the crtbegin.o file for C++ ... */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{!pg:crt0.o%s}%{pg:gcrt0.o%s} crtbegin.o%s"
-
-#undef SCCS_DIRECTIVE
-#undef NO_DOLLAR_IN_LABEL
-#undef TARGET_MEM_FUNCTIONS
-
-#undef DWARF_DEBUGGING_INFO
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-
-/* ??? Is this used anywhere? */
-#undef BSS_ASM_OP
-#define BSS_ASM_OP "\t.lcomm "
-
-#undef ASM_FILE_END
-#define ASM_FILE_END(FILE) \
-do { \
- if (current_function_original_name != NULL) { \
- const char *long_op = integer_asm_op (4, FALSE); \
- tdesc_section(); \
- fprintf ((FILE), "%s __ETEXT\n", long_op); \
- fprintf ((FILE), "%s 0\n", long_op); \
- fputs ("\t.long\t__ETEXT\n", (FILE)); \
- fputs ("\t.long\t0\n", (FILE)); \
- text_section(); \
- fputs("__ETEXT:\n", (FILE)); \
- } \
- if (!flag_no_ident) \
- fprintf ((FILE), "\t.ident\t\"GCC: (GNU) %s\"\n", \
- version_string); \
- } while (0)
+++ /dev/null
-/* Definitions of target machine for GNU compiler, for Intel 860.
- Copyright (C) 2000 Free Software Foundation, Inc.
- Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to
- the whims of the System V Release 4 assembler.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Declare things which are defined in i860.c but called from
- insn-output.c. */
-
-#ifdef RTX_CODE
-extern unsigned long sfmode_constant_to_ulong PARAMS ((rtx));
-extern const char *output_load PARAMS ((rtx *));
-extern const char *output_store PARAMS ((rtx *));
-extern const char *output_move_double PARAMS ((rtx *));
-extern const char *output_fp_move_double PARAMS ((rtx *));
-extern const char *output_block_move PARAMS ((rtx *));
-extern const char *output_delay_insn PARAMS ((rtx));
-#if 0
-extern const char *output_delayed_branch PARAMS ((const char *, rtx *, rtx));
-#endif
-extern void output_load_address PARAMS ((rtx *));
-extern int safe_insn_src_p PARAMS ((rtx, enum machine_mode));
-extern int operand_clobbered_before_used_after PARAMS ((rtx, rtx));
-extern int single_insn_src_p PARAMS ((rtx, enum machine_mode));
-extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode));
-extern int arith_operand PARAMS ((rtx, enum machine_mode));
-extern int logic_operand PARAMS ((rtx, enum machine_mode));
-extern int shift_operand PARAMS ((rtx, enum machine_mode));
-extern int compare_operand PARAMS ((rtx, enum machine_mode));
-extern int bte_operand PARAMS ((rtx, enum machine_mode));
-extern int indexed_operand PARAMS ((rtx, enum machine_mode));
-extern int load_operand PARAMS ((rtx, enum machine_mode));
-extern int small_int PARAMS ((rtx, enum machine_mode));
-extern int logic_int PARAMS ((rtx, enum machine_mode));
-extern int call_insn_operand PARAMS ((rtx, enum machine_mode));
-extern rtx i860_saveregs PARAMS ((void));
-#ifdef TREE_CODE
-extern void i860_va_start PARAMS ((int, tree, rtx));
-extern rtx i860_va_arg PARAMS ((tree, tree));
-#endif /* TREE_CODE */
-#endif /* RTX_CODE */
-
-#ifdef TREE_CODE
-extern tree i860_build_va_list PARAMS ((void));
-#endif /* TREE_CODE */
+++ /dev/null
-/* Subroutines for insn-output.c for Intel 860
- Copyright (C) 1989, 1991, 1997, 1998, 1999, 2000, 2001, 2002
- Free Software Foundation, Inc.
- Derived from sparc.c.
-
- Written by Richard Stallman (rms@ai.mit.edu).
-
- Hacked substantially by Ron Guilmette (rfg@netcom.com) to cater
- to the whims of the System V Release 4 assembler.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-#include "config.h"
-#include "system.h"
-#include "flags.h"
-#include "rtl.h"
-#include "tree.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "output.h"
-#include "recog.h"
-#include "insn-attr.h"
-#include "function.h"
-#include "expr.h"
-#include "tm_p.h"
-#include "target.h"
-#include "target-def.h"
-
-static rtx find_addr_reg PARAMS ((rtx));
-static int reg_clobbered_p PARAMS ((rtx, rtx));
-static const char *singlemove_string PARAMS ((rtx *));
-static const char *load_opcode PARAMS ((enum machine_mode, const char *, rtx));
-static const char *store_opcode PARAMS ((enum machine_mode, const char *, rtx));
-static void output_size_for_block_move PARAMS ((rtx, rtx, rtx));
-static void i860_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void i860_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-
-#ifndef I860_REG_PREFIX
-#define I860_REG_PREFIX ""
-#endif
-
-const char *i860_reg_prefix = I860_REG_PREFIX;
-
-/* Save information from a "cmpxx" operation until the branch is emitted. */
-
-rtx i860_compare_op0, i860_compare_op1;
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE i860_output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE i860_output_function_epilogue
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* Return non-zero if this pattern, can be evaluated safely, even if it
- was not asked for. */
-int
-safe_insn_src_p (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- /* Just experimenting. */
-
- /* No floating point src is safe if it contains an arithmetic
- operation, since that operation may trap. */
- switch (GET_CODE (op))
- {
- case CONST_INT:
- case LABEL_REF:
- case SYMBOL_REF:
- case CONST:
- return 1;
-
- case REG:
- return 1;
-
- case MEM:
- return CONSTANT_ADDRESS_P (XEXP (op, 0));
-
- /* We never need to negate or complement constants. */
- case NEG:
- return (mode != SFmode && mode != DFmode);
- case NOT:
- case ZERO_EXTEND:
- return 1;
-
- case EQ:
- case NE:
- case LT:
- case GT:
- case LE:
- case GE:
- case LTU:
- case GTU:
- case LEU:
- case GEU:
- case MINUS:
- case PLUS:
- return (mode != SFmode && mode != DFmode);
- case AND:
- case IOR:
- case XOR:
- case ASHIFT:
- case ASHIFTRT:
- case LSHIFTRT:
- if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0)))
- || (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1))))
- return 0;
- return 1;
-
- default:
- return 0;
- }
-}
-
-/* Return 1 if REG is clobbered in IN.
- Return 2 if REG is used in IN.
- Return 3 if REG is both used and clobbered in IN.
- Return 0 if neither. */
-
-static int
-reg_clobbered_p (reg, in)
- rtx reg;
- rtx in;
-{
- register enum rtx_code code;
-
- if (in == 0)
- return 0;
-
- code = GET_CODE (in);
-
- if (code == SET || code == CLOBBER)
- {
- rtx dest = SET_DEST (in);
- int set = 0;
- int used = 0;
-
- while (GET_CODE (dest) == STRICT_LOW_PART
- || GET_CODE (dest) == SUBREG
- || GET_CODE (dest) == SIGN_EXTRACT
- || GET_CODE (dest) == ZERO_EXTRACT)
- dest = XEXP (dest, 0);
-
- if (dest == reg)
- set = 1;
- else if (GET_CODE (dest) == REG
- && refers_to_regno_p (REGNO (reg),
- REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
- SET_DEST (in), 0))
- {
- set = 1;
- /* Anything that sets just part of the register
- is considered using as well as setting it.
- But note that a straight SUBREG of a single-word value
- clobbers the entire value. */
- if (dest != SET_DEST (in)
- && ! (GET_CODE (SET_DEST (in)) == SUBREG
- || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
- used = 1;
- }
-
- if (code == SET)
- {
- if (set)
- used = refers_to_regno_p (REGNO (reg),
- REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
- SET_SRC (in), 0);
- else
- used = refers_to_regno_p (REGNO (reg),
- REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
- in, 0);
- }
-
- return set + used * 2;
- }
-
- if (refers_to_regno_p (REGNO (reg),
- REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
- in, 0))
- return 2;
- return 0;
-}
-
-/* Return non-zero if OP can be written to without screwing up
- GCC's model of what's going on. It is assumed that this operand
- appears in the dest position of a SET insn in a conditional
- branch's delay slot. AFTER is the label to start looking from. */
-int
-operand_clobbered_before_used_after (op, after)
- rtx op;
- rtx after;
-{
- /* Just experimenting. */
- if (GET_CODE (op) == CC0)
- return 1;
- if (GET_CODE (op) == REG)
- {
- rtx insn;
-
- if (op == stack_pointer_rtx)
- return 0;
-
- /* Scan forward from the label, to see if the value of OP
- is clobbered before the first use. */
-
- for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn))
- {
- if (GET_CODE (insn) == NOTE)
- continue;
- if (GET_CODE (insn) == INSN
- || GET_CODE (insn) == JUMP_INSN
- || GET_CODE (insn) == CALL_INSN)
- {
- switch (reg_clobbered_p (op, PATTERN (insn)))
- {
- default:
- return 0;
- case 1:
- return 1;
- case 0:
- break;
- }
- }
- /* If we reach another label without clobbering OP,
- then we cannot safely write it here. */
- else if (GET_CODE (insn) == CODE_LABEL)
- return 0;
- if (GET_CODE (insn) == JUMP_INSN)
- {
- if (condjump_p (insn))
- return 0;
- /* This is a jump insn which has already
- been mangled. We can't tell what it does. */
- if (GET_CODE (PATTERN (insn)) == PARALLEL)
- return 0;
- if (! JUMP_LABEL (insn))
- return 0;
- /* Keep following jumps. */
- insn = JUMP_LABEL (insn);
- }
- }
- return 1;
- }
-
- /* In both of these cases, the first insn executed
- for this op will be a orh whatever%h,%?r0,%?r31,
- which is tolerable. */
- if (GET_CODE (op) == MEM)
- return (CONSTANT_ADDRESS_P (XEXP (op, 0)));
-
- return 0;
-}
-
-/* Return non-zero if this pattern, as a source to a "SET",
- is known to yield an instruction of unit size. */
-int
-single_insn_src_p (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- switch (GET_CODE (op))
- {
- case CONST_INT:
- /* This is not always a single insn src, technically,
- but output_delayed_branch knows how to deal with it. */
- return 1;
-
- case SYMBOL_REF:
- case CONST:
- /* This is not a single insn src, technically,
- but output_delayed_branch knows how to deal with it. */
- return 1;
-
- case REG:
- return 1;
-
- case MEM:
- return 1;
-
- /* We never need to negate or complement constants. */
- case NEG:
- return (mode != DFmode);
- case NOT:
- case ZERO_EXTEND:
- return 1;
-
- case PLUS:
- case MINUS:
- /* Detect cases that require multiple instructions. */
- if (CONSTANT_P (XEXP (op, 1))
- && !(GET_CODE (XEXP (op, 1)) == CONST_INT
- && SMALL_INT (XEXP (op, 1))))
- return 0;
- case EQ:
- case NE:
- case LT:
- case GT:
- case LE:
- case GE:
- case LTU:
- case GTU:
- case LEU:
- case GEU:
- /* Not doing floating point, since they probably
- take longer than the branch slot they might fill. */
- return (mode != SFmode && mode != DFmode);
-
- case AND:
- if (GET_CODE (XEXP (op, 1)) == NOT)
- {
- rtx arg = XEXP (XEXP (op, 1), 0);
- if (CONSTANT_P (arg)
- && !(GET_CODE (arg) == CONST_INT
- && (SMALL_INT (arg)
- || (INTVAL (arg) & 0xffff) == 0)))
- return 0;
- }
- case IOR:
- case XOR:
- /* Both small and round numbers take one instruction;
- others take two. */
- if (CONSTANT_P (XEXP (op, 1))
- && !(GET_CODE (XEXP (op, 1)) == CONST_INT
- && (SMALL_INT (XEXP (op, 1))
- || (INTVAL (XEXP (op, 1)) & 0xffff) == 0)))
- return 0;
-
- case ASHIFT:
- case ASHIFTRT:
- case LSHIFTRT:
- return 1;
-
- case SUBREG:
- if (SUBREG_BYTE (op) != 0)
- return 0;
- return single_insn_src_p (SUBREG_REG (op), mode);
-
- /* Not doing floating point, since they probably
- take longer than the branch slot they might fill. */
- case FLOAT_EXTEND:
- case FLOAT_TRUNCATE:
- case FLOAT:
- case FIX:
- case UNSIGNED_FLOAT:
- case UNSIGNED_FIX:
- return 0;
-
- default:
- return 0;
- }
-}
-\f
-/* Return non-zero only if OP is a register of mode MODE,
- or const0_rtx. */
-int
-reg_or_0_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (op == const0_rtx || register_operand (op, mode)
- || op == CONST0_RTX (mode));
-}
-
-/* Return truth value of whether OP can be used as an operands in a three
- address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
-
-int
-arith_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
-}
-
-/* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
-
-int
-logic_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT && LOGIC_INT (op)));
-}
-
-/* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
-
-int
-shift_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT));
-}
-
-/* Return 1 if OP is a valid first operand for either a logical insn
- or an add insn of mode MODE. */
-
-int
-compare_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT && SMALL_INT (op) && LOGIC_INT (op)));
-}
-
-/* Return truth value of whether OP can be used as the 5-bit immediate
- operand of a bte or btne insn. */
-
-int
-bte_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT
- && (unsigned) INTVAL (op) < 0x20));
-}
-
-/* Return 1 if OP is an indexed memory reference of mode MODE. */
-
-int
-indexed_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (GET_CODE (op) == MEM && GET_MODE (op) == mode
- && GET_CODE (XEXP (op, 0)) == PLUS
- && GET_MODE (XEXP (op, 0)) == SImode
- && register_operand (XEXP (XEXP (op, 0), 0), SImode)
- && register_operand (XEXP (XEXP (op, 0), 1), SImode));
-}
-
-/* Return 1 if OP is a suitable source operand for a load insn
- with mode MODE. */
-
-int
-load_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return (memory_operand (op, mode) || indexed_operand (op, mode));
-}
-
-/* Return truth value of whether OP is an integer which fits the
- range constraining immediate operands in add/subtract insns. */
-
-int
-small_int (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
-}
-
-/* Return truth value of whether OP is an integer which fits the
- range constraining immediate operands in logic insns. */
-
-int
-logic_int (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return (GET_CODE (op) == CONST_INT && LOGIC_INT (op));
-}
-
-/* Test for a valid operand for a call instruction.
- Don't allow the arg pointer register or virtual regs
- since they may change into reg + const, which the patterns
- can't handle yet. */
-
-int
-call_insn_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- if (GET_CODE (op) == MEM
- && (CONSTANT_ADDRESS_P (XEXP (op, 0))
- || (GET_CODE (XEXP (op, 0)) == REG
- && XEXP (op, 0) != arg_pointer_rtx
- && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
- && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
- return 1;
- return 0;
-}
-\f
-/* Return the best assembler insn template
- for moving operands[1] into operands[0] as a fullword. */
-
-static const char *
-singlemove_string (operands)
- rtx *operands;
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (GET_CODE (operands[1]) != MEM)
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && cc_prev_status.mdep == XEXP (operands[0], 0)))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h0,%?r0,%?r31", operands);
- }
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[0], 0);
- return "st.l %r1,%L0(%?r31)";
- }
- else
- return "st.l %r1,%0";
- else
- abort ();
-#if 0
- {
- rtx xoperands[2];
-
- cc_status.flags &= ~CC_F0_IS_0;
- xoperands[0] = gen_rtx_REG (SFmode, 32);
- xoperands[1] = operands[1];
- output_asm_insn (singlemove_string (xoperands), xoperands);
- xoperands[1] = xoperands[0];
- xoperands[0] = operands[0];
- output_asm_insn (singlemove_string (xoperands), xoperands);
- return "";
- }
-#endif
- }
- if (GET_CODE (operands[1]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && cc_prev_status.mdep == XEXP (operands[1], 0)))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h1,%?r0,%?r31", operands);
- }
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[1], 0);
- return "ld.l %L1(%?r31),%0";
- }
- return "ld.l %m1,%0";
- }
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- if (operands[1] == const0_rtx)
- return "mov %?r0,%0";
- if((INTVAL (operands[1]) & 0xffff0000) == 0)
- return "or %L1,%?r0,%0";
- if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000)
- return "adds %1,%?r0,%0";
- if((INTVAL (operands[1]) & 0x0000ffff) == 0)
- return "orh %H1,%?r0,%0";
-
- return "orh %H1,%?r0,%0\n\tor %L1,%0,%0";
- }
- return "mov %1,%0";
-}
-\f
-/* Output assembler code to perform a doubleword move insn
- with operands OPERANDS. */
-
-const char *
-output_move_double (operands)
- rtx *operands;
-{
- enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
- rtx latehalf[2];
- rtx addreg0 = 0, addreg1 = 0;
- int highest_first = 0;
- int no_addreg1_decrement = 0;
-
- /* First classify both operands. */
-
- if (REG_P (operands[0]))
- optype0 = REGOP;
- else if (offsettable_memref_p (operands[0]))
- optype0 = OFFSOP;
- else if (GET_CODE (operands[0]) == MEM)
- optype0 = MEMOP;
- else
- optype0 = RNDOP;
-
- if (REG_P (operands[1]))
- optype1 = REGOP;
- else if (CONSTANT_P (operands[1]))
- optype1 = CNSTOP;
- else if (offsettable_memref_p (operands[1]))
- optype1 = OFFSOP;
- else if (GET_CODE (operands[1]) == MEM)
- optype1 = MEMOP;
- else
- optype1 = RNDOP;
-
- /* Check for the cases that the operand constraints are not
- supposed to allow to happen. Abort if we get one,
- because generating code for these cases is painful. */
-
- if (optype0 == RNDOP || optype1 == RNDOP)
- abort ();
-
- /* If an operand is an unoffsettable memory ref, find a register
- we can increment temporarily to make it refer to the second word. */
-
- if (optype0 == MEMOP)
- addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
- if (optype1 == MEMOP)
- addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-/* ??? Perhaps in some cases move double words
- if there is a spare pair of floating regs. */
-
- /* Ok, we can do one word at a time.
- Normally we do the low-numbered word first,
- but if either operand is autodecrementing then we
- do the high-numbered word first.
-
- In either case, set up in LATEHALF the operands to use
- for the high-numbered word and in some cases alter the
- operands in OPERANDS to be suitable for the low-numbered word. */
-
- if (optype0 == REGOP)
- latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else if (optype0 == OFFSOP)
- latehalf[0] = adjust_address (operands[0], SImode, 4);
- else
- latehalf[0] = operands[0];
-
- if (optype1 == REGOP)
- latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- else if (optype1 == OFFSOP)
- latehalf[1] = adjust_address (operands[1], SImode, 4);
- else if (optype1 == CNSTOP)
- {
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- split_double (operands[1], &operands[1], &latehalf[1]);
- else if (CONSTANT_P (operands[1]))
- latehalf[1] = const0_rtx;
- }
- else
- latehalf[1] = operands[1];
-
- /* If the first move would clobber the source of the second one,
- do them in the other order.
-
- RMS says "This happens only for registers;
- such overlap can't happen in memory unless the user explicitly
- sets it up, and that is an undefined circumstance."
-
- but it happens on the sparc when loading parameter registers,
- so I am going to define that circumstance, and make it work
- as expected. */
-
- if (optype0 == REGOP && optype1 == REGOP
- && REGNO (operands[0]) == REGNO (latehalf[1]))
- {
- CC_STATUS_PARTIAL_INIT;
- /* Make any unoffsettable addresses point at high-numbered word. */
- if (addreg0)
- output_asm_insn ("adds 0x4,%0,%0", &addreg0);
- if (addreg1)
- output_asm_insn ("adds 0x4,%0,%0", &addreg1);
-
- /* Do that word. */
- output_asm_insn (singlemove_string (latehalf), latehalf);
-
- /* Undo the adds we just did. */
- if (addreg0)
- output_asm_insn ("adds -0x4,%0,%0", &addreg0);
- if (addreg1)
- output_asm_insn ("adds -0x4,%0,%0", &addreg1);
-
- /* Do low-numbered word. */
- return singlemove_string (operands);
- }
- else if (optype0 == REGOP && optype1 != REGOP
- && reg_overlap_mentioned_p (operands[0], operands[1]))
- {
- /* If both halves of dest are used in the src memory address,
- add the two regs and put them in the low reg (operands[0]).
- Then it works to load latehalf first. */
- if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
- && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
- {
- rtx xops[2];
- xops[0] = latehalf[0];
- xops[1] = operands[0];
- output_asm_insn ("adds %1,%0,%1", xops);
- operands[1] = gen_rtx_MEM (DImode, operands[0]);
- latehalf[1] = adjust_address (operands[1], SImode, 4);
- addreg1 = 0;
- highest_first = 1;
- }
- /* Only one register in the dest is used in the src memory address,
- and this is the first register of the dest, so we want to do
- the late half first here also. */
- else if (! reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
- highest_first = 1;
- /* Only one register in the dest is used in the src memory address,
- and this is the second register of the dest, so we want to do
- the late half last. If addreg1 is set, and addreg1 is the same
- register as latehalf, then we must suppress the trailing decrement,
- because it would clobber the value just loaded. */
- else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
- no_addreg1_decrement = 1;
- }
-
- /* Normal case: do the two words, low-numbered first.
- Overlap case (highest_first set): do high-numbered word first. */
-
- if (! highest_first)
- output_asm_insn (singlemove_string (operands), operands);
-
- CC_STATUS_PARTIAL_INIT;
- /* Make any unoffsettable addresses point at high-numbered word. */
- if (addreg0)
- output_asm_insn ("adds 0x4,%0,%0", &addreg0);
- if (addreg1)
- output_asm_insn ("adds 0x4,%0,%0", &addreg1);
-
- /* Do that word. */
- output_asm_insn (singlemove_string (latehalf), latehalf);
-
- /* Undo the adds we just did. */
- if (addreg0)
- output_asm_insn ("adds -0x4,%0,%0", &addreg0);
- if (addreg1 && !no_addreg1_decrement)
- output_asm_insn ("adds -0x4,%0,%0", &addreg1);
-
- if (highest_first)
- output_asm_insn (singlemove_string (operands), operands);
-
- return "";
-}
-\f
-const char *
-output_fp_move_double (operands)
- rtx *operands;
-{
- /* If the source operand is any sort of zero, use f0 instead. */
-
- if (operands[1] == CONST0_RTX (GET_MODE (operands[1])))
- operands[1] = gen_rtx_REG (DFmode, F0_REGNUM);
-
- if (FP_REG_P (operands[0]))
- {
- if (FP_REG_P (operands[1]))
- return "fmov.dd %1,%0";
- if (GET_CODE (operands[1]) == REG)
- {
- output_asm_insn ("ixfr %1,%0", operands);
- operands[0] = gen_rtx_REG (VOIDmode, REGNO (operands[0]) + 1);
- operands[1] = gen_rtx_REG (VOIDmode, REGNO (operands[1]) + 1);
- return "ixfr %1,%0";
- }
- if (operands[1] == CONST0_RTX (DFmode))
- return "fmov.dd f0,%0";
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && cc_prev_status.mdep == XEXP (operands[1], 0)))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h1,%?r0,%?r31", operands);
- }
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[1], 0);
- return "fld.d %L1(%?r31),%0";
- }
- return "fld.d %1,%0";
- }
- else if (FP_REG_P (operands[1]))
- {
- if (GET_CODE (operands[0]) == REG)
- {
- output_asm_insn ("fxfr %1,%0", operands);
- operands[0] = gen_rtx_REG (VOIDmode, REGNO (operands[0]) + 1);
- operands[1] = gen_rtx_REG (VOIDmode, REGNO (operands[1]) + 1);
- return "fxfr %1,%0";
- }
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && cc_prev_status.mdep == XEXP (operands[0], 0)))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h0,%?r0,%?r31", operands);
- }
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[0], 0);
- return "fst.d %1,%L0(%?r31)";
- }
- return "fst.d %1,%0";
- }
- else
- abort ();
- /* NOTREACHED */
- return NULL;
-}
-\f
-/* Return a REG that occurs in ADDR with coefficient 1.
- ADDR can be effectively incremented by incrementing REG. */
-
-static rtx
-find_addr_reg (addr)
- rtx addr;
-{
- while (GET_CODE (addr) == PLUS)
- {
- if (GET_CODE (XEXP (addr, 0)) == REG)
- addr = XEXP (addr, 0);
- else if (GET_CODE (XEXP (addr, 1)) == REG)
- addr = XEXP (addr, 1);
- else if (CONSTANT_P (XEXP (addr, 0)))
- addr = XEXP (addr, 1);
- else if (CONSTANT_P (XEXP (addr, 1)))
- addr = XEXP (addr, 0);
- else
- abort ();
- }
- if (GET_CODE (addr) == REG)
- return addr;
- abort ();
- /* NOTREACHED */
- return NULL;
-}
-
-/* Return a template for a load instruction with mode MODE and
- arguments from the string ARGS.
-
- This string is in static storage. */
-
-static const char *
-load_opcode (mode, args, reg)
- enum machine_mode mode;
- const char *args;
- rtx reg;
-{
- static char buf[30];
- const char *opcode;
-
- switch (mode)
- {
- case QImode:
- opcode = "ld.b";
- break;
-
- case HImode:
- opcode = "ld.s";
- break;
-
- case SImode:
- case SFmode:
- if (FP_REG_P (reg))
- opcode = "fld.l";
- else
- opcode = "ld.l";
- break;
-
- case DImode:
- if (!FP_REG_P (reg))
- abort ();
- case DFmode:
- opcode = "fld.d";
- break;
-
- default:
- abort ();
- }
-
- sprintf (buf, "%s %s", opcode, args);
- return buf;
-}
-
-/* Return a template for a store instruction with mode MODE and
- arguments from the string ARGS.
-
- This string is in static storage. */
-
-static const char *
-store_opcode (mode, args, reg)
- enum machine_mode mode;
- const char *args;
- rtx reg;
-{
- static char buf[30];
- const char *opcode;
-
- switch (mode)
- {
- case QImode:
- opcode = "st.b";
- break;
-
- case HImode:
- opcode = "st.s";
- break;
-
- case SImode:
- case SFmode:
- if (FP_REG_P (reg))
- opcode = "fst.l";
- else
- opcode = "st.l";
- break;
-
- case DImode:
- if (!FP_REG_P (reg))
- abort ();
- case DFmode:
- opcode = "fst.d";
- break;
-
- default:
- abort ();
- }
-
- sprintf (buf, "%s %s", opcode, args);
- return buf;
-}
-\f
-/* Output a store-in-memory whose operands are OPERANDS[0,1].
- OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
-
- This function returns a template for an insn.
- This is in static storage.
-
- It may also output some insns directly.
- It may alter the values of operands[0] and operands[1]. */
-
-const char *
-output_store (operands)
- rtx *operands;
-{
- enum machine_mode mode = GET_MODE (operands[0]);
- rtx address = XEXP (operands[0], 0);
-
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = address;
-
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && address == cc_prev_status.mdep))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h0,%?r0,%?r31", operands);
- cc_prev_status.mdep = address;
- }
-
- /* Store zero in two parts when appropriate. */
- if (mode == DFmode && operands[1] == CONST0_RTX (DFmode))
- return store_opcode (DFmode, "%r1,%L0(%?r31)", operands[1]);
-
- /* Code below isn't smart enough to move a doubleword in two parts,
- so use output_move_double to do that in the cases that require it. */
- if ((mode == DImode || mode == DFmode)
- && ! FP_REG_P (operands[1]))
- return output_move_double (operands);
-
- return store_opcode (mode, "%r1,%L0(%?r31)", operands[1]);
-}
-
-/* Output a load-from-memory whose operands are OPERANDS[0,1].
- OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
-
- This function returns a template for an insn.
- This is in static storage.
-
- It may also output some insns directly.
- It may alter the values of operands[0] and operands[1]. */
-
-const char *
-output_load (operands)
- rtx *operands;
-{
- enum machine_mode mode = GET_MODE (operands[0]);
- rtx address = XEXP (operands[1], 0);
-
- /* We don't bother trying to see if we know %hi(address).
- This is because we are doing a load, and if we know the
- %hi value, we probably also know that value in memory. */
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = address;
-
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && address == cc_prev_status.mdep
- && cc_prev_status.mdep == cc_status.mdep))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h1,%?r0,%?r31", operands);
- cc_prev_status.mdep = address;
- }
-
- /* Code below isn't smart enough to move a doubleword in two parts,
- so use output_move_double to do that in the cases that require it. */
- if ((mode == DImode || mode == DFmode)
- && ! FP_REG_P (operands[0]))
- return output_move_double (operands);
-
- return load_opcode (mode, "%L1(%?r31),%0", operands[0]);
-}
-\f
-#if 0
-/* Load the address specified by OPERANDS[3] into the register
- specified by OPERANDS[0].
-
- OPERANDS[3] may be the result of a sum, hence it could either be:
-
- (1) CONST
- (2) REG
- (2) REG + CONST_INT
- (3) REG + REG + CONST_INT
- (4) REG + REG (special case of 3).
-
- Note that (3) is not a legitimate address.
- All cases are handled here. */
-
-void
-output_load_address (operands)
- rtx *operands;
-{
- rtx base, offset;
-
- if (CONSTANT_P (operands[3]))
- {
- output_asm_insn ("mov %3,%0", operands);
- return;
- }
-
- if (REG_P (operands[3]))
- {
- if (REGNO (operands[0]) != REGNO (operands[3]))
- output_asm_insn ("shl %?r0,%3,%0", operands);
- return;
- }
-
- if (GET_CODE (operands[3]) != PLUS)
- abort ();
-
- base = XEXP (operands[3], 0);
- offset = XEXP (operands[3], 1);
-
- if (GET_CODE (base) == CONST_INT)
- {
- rtx tmp = base;
- base = offset;
- offset = tmp;
- }
-
- if (GET_CODE (offset) != CONST_INT)
- {
- /* Operand is (PLUS (REG) (REG)). */
- base = operands[3];
- offset = const0_rtx;
- }
-
- if (REG_P (base))
- {
- operands[6] = base;
- operands[7] = offset;
- CC_STATUS_PARTIAL_INIT;
- if (SMALL_INT (offset))
- output_asm_insn ("adds %7,%6,%0", operands);
- else
- output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands);
- }
- else if (GET_CODE (base) == PLUS)
- {
- operands[6] = XEXP (base, 0);
- operands[7] = XEXP (base, 1);
- operands[8] = offset;
-
- CC_STATUS_PARTIAL_INIT;
- if (SMALL_INT (offset))
- output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands);
- else
- output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands);
- }
- else
- abort ();
-}
-#endif
-
-/* Output code to place a size count SIZE in register REG.
- Because block moves are pipelined, we don't include the
- first element in the transfer of SIZE to REG.
- For this, we subtract ALIGN. (Actually, I think it is not
- right to subtract on this machine, so right now we don't.) */
-
-static void
-output_size_for_block_move (size, reg, align)
- rtx size, reg, align;
-{
- rtx xoperands[3];
-
- xoperands[0] = reg;
- xoperands[1] = size;
- xoperands[2] = align;
-
-#if 1
- cc_status.flags &= ~ CC_KNOW_HI_R31;
- output_asm_insn (singlemove_string (xoperands), xoperands);
-#else
- if (GET_CODE (size) == REG)
- output_asm_insn ("sub %2,%1,%0", xoperands);
- else
- {
- xoperands[1] = GEN_INT (INTVAL (size) - INTVAL (align));
- cc_status.flags &= ~ CC_KNOW_HI_R31;
- output_asm_insn ("mov %1,%0", xoperands);
- }
-#endif
-}
-
-/* Emit code to perform a block move.
-
- OPERANDS[0] is the destination.
- OPERANDS[1] is the source.
- OPERANDS[2] is the size.
- OPERANDS[3] is the known safe alignment.
- OPERANDS[4..6] are pseudos we can safely clobber as temps. */
-
-const char *
-output_block_move (operands)
- rtx *operands;
-{
- /* A vector for our computed operands. Note that load_output_address
- makes use of (and can clobber) up to the 8th element of this vector. */
- rtx xoperands[10];
-#if 0
- rtx zoperands[10];
-#endif
- static int movstrsi_label = 0;
- int i;
- rtx temp1 = operands[4];
- rtx alignrtx = operands[3];
- int align = INTVAL (alignrtx);
- int chunk_size;
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[1];
- xoperands[2] = temp1;
-
- /* We can't move more than four bytes at a time
- because we have only one register to move them through. */
- if (align > 4)
- {
- align = 4;
- alignrtx = GEN_INT (4);
- }
-
- /* Recognize special cases of block moves. These occur
- when GNU C++ is forced to treat something as BLKmode
- to keep it in memory, when its mode could be represented
- with something smaller.
-
- We cannot do this for global variables, since we don't know
- what pages they don't cross. Sigh. */
- if (GET_CODE (operands[2]) == CONST_INT
- && ! CONSTANT_ADDRESS_P (operands[0])
- && ! CONSTANT_ADDRESS_P (operands[1]))
- {
- int size = INTVAL (operands[2]);
- rtx op0 = xoperands[0];
- rtx op1 = xoperands[1];
-
- if ((align & 3) == 0 && (size & 3) == 0 && (size >> 2) <= 16)
- {
- if (memory_address_p (SImode, plus_constant (op0, size))
- && memory_address_p (SImode, plus_constant (op1, size)))
- {
- cc_status.flags &= ~CC_KNOW_HI_R31;
- for (i = (size>>2)-1; i >= 0; i--)
- {
- xoperands[0] = plus_constant (op0, i * 4);
- xoperands[1] = plus_constant (op1, i * 4);
- output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
- xoperands);
- }
- return "";
- }
- }
- else if ((align & 1) == 0 && (size & 1) == 0 && (size >> 1) <= 16)
- {
- if (memory_address_p (HImode, plus_constant (op0, size))
- && memory_address_p (HImode, plus_constant (op1, size)))
- {
- cc_status.flags &= ~CC_KNOW_HI_R31;
- for (i = (size>>1)-1; i >= 0; i--)
- {
- xoperands[0] = plus_constant (op0, i * 2);
- xoperands[1] = plus_constant (op1, i * 2);
- output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
- xoperands);
- }
- return "";
- }
- }
- else if (size <= 16)
- {
- if (memory_address_p (QImode, plus_constant (op0, size))
- && memory_address_p (QImode, plus_constant (op1, size)))
- {
- cc_status.flags &= ~CC_KNOW_HI_R31;
- for (i = size-1; i >= 0; i--)
- {
- xoperands[0] = plus_constant (op0, i);
- xoperands[1] = plus_constant (op1, i);
- output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
- xoperands);
- }
- return "";
- }
- }
- }
-
- /* Since we clobber untold things, nix the condition codes. */
- CC_STATUS_INIT;
-
- /* This is the size of the transfer.
- Either use the register which already contains the size,
- or use a free register (used by no operands). */
- output_size_for_block_move (operands[2], operands[4], alignrtx);
-
-#if 0
- /* Also emit code to decrement the size value by ALIGN. */
- zoperands[0] = operands[0];
- zoperands[3] = plus_constant (operands[0], align);
- output_load_address (zoperands);
-#endif
-
- /* Generate number for unique label. */
-
- xoperands[3] = GEN_INT (movstrsi_label++);
-
- /* Calculate the size of the chunks we will be trying to move first. */
-
-#if 0
- if ((align & 3) == 0)
- chunk_size = 4;
- else if ((align & 1) == 0)
- chunk_size = 2;
- else
-#endif
- chunk_size = 1;
-
- /* Copy the increment (negative) to a register for bla insn. */
-
- xoperands[4] = GEN_INT (- chunk_size);
- xoperands[5] = operands[5];
- output_asm_insn ("adds %4,%?r0,%5", xoperands);
-
- /* Predecrement the loop counter. This happens again also in the `bla'
- instruction which precedes the loop, but we need to have it done
- two times before we enter the loop because of the bizarre semantics
- of the bla instruction. */
-
- output_asm_insn ("adds %5,%2,%2", xoperands);
-
- /* Check for the case where the original count was less than or equal to
- zero. Avoid going through the loop at all if the original count was
- indeed less than or equal to zero. Note that we treat the count as
- if it were a signed 32-bit quantity here, rather than an unsigned one,
- even though we really shouldn't. We have to do this because of the
- semantics of the `ble' instruction, which assume that the count is
- a signed 32-bit value. Anyway, in practice it won't matter because
- nobody is going to try to do a memcpy() of more than half of the
- entire address space (i.e. 2 gigabytes) anyway. */
-
- output_asm_insn ("bc .Le%3", xoperands);
-
- /* Make available a register which is a temporary. */
-
- xoperands[6] = operands[6];
-
- /* Now the actual loop.
- In xoperands, elements 1 and 0 are the input and output vectors.
- Element 2 is the loop index. Element 5 is the increment. */
-
- output_asm_insn ("subs %1,%5,%1", xoperands);
- output_asm_insn ("bla %5,%2,.Lm%3", xoperands);
- output_asm_insn ("adds %0,%2,%6", xoperands);
- output_asm_insn ("\n.Lm%3:", xoperands); /* Label for bla above. */
- output_asm_insn ("\n.Ls%3:", xoperands); /* Loop start label. */
- output_asm_insn ("adds %5,%6,%6", xoperands);
-
- /* NOTE: The code here which is supposed to handle the cases where the
- sources and destinations are known to start on a 4 or 2 byte boundary
- are currently broken. They fail to do anything about the overflow
- bytes which might still need to be copied even after we have copied
- some number of words or halfwords. Thus, for now we use the lowest
- common denominator, i.e. the code which just copies some number of
- totally unaligned individual bytes. (See the calculation of
- chunk_size above. */
-
- if (chunk_size == 4)
- {
- output_asm_insn ("ld.l %2(%1),%?r31", xoperands);
- output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
- output_asm_insn ("st.l %?r31,8(%6)", xoperands);
- }
- else if (chunk_size == 2)
- {
- output_asm_insn ("ld.s %2(%1),%?r31", xoperands);
- output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
- output_asm_insn ("st.s %?r31,4(%6)", xoperands);
- }
- else /* chunk_size == 1 */
- {
- output_asm_insn ("ld.b %2(%1),%?r31", xoperands);
- output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
- output_asm_insn ("st.b %?r31,2(%6)", xoperands);
- }
- output_asm_insn ("\n.Le%3:", xoperands); /* Here if count <= 0. */
-
- return "";
-}
-\f
-#if 0
-/* Output a delayed branch insn with the delay insn in its
- branch slot. The delayed branch insn template is in TEMPLATE,
- with operands OPERANDS. The insn in its delay slot is INSN.
-
- As a special case, since we know that all memory transfers are via
- ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
- reference around the branch as
-
- orh ha%x,%?r0,%?r31
- b ...
- ld/st l%x(%?r31),...
-
- As another special case, we handle loading (SYMBOL_REF ...) and
- other large constants around branches as well:
-
- orh h%x,%?r0,%0
- b ...
- or l%x,%0,%1
-
- */
-/* ??? Disabled because this re-recognition is incomplete and causes
- constrain_operands to segfault. Anyone who cares should fix up
- the code to use the DBR pass. */
-
-const char *
-output_delayed_branch (template, operands, insn)
- const char *template;
- rtx *operands;
- rtx insn;
-{
- rtx src = XVECEXP (PATTERN (insn), 0, 1);
- rtx dest = XVECEXP (PATTERN (insn), 0, 0);
-
- /* See if we are doing some branch together with setting some register
- to some 32-bit value which does (or may) have some of the high-order
- 16 bits set. If so, we need to set the register in two stages. One
- stage must be done before the branch, and the other one can be done
- in the delay slot. */
-
- if ( (GET_CODE (src) == CONST_INT
- && ((unsigned) INTVAL (src) & (unsigned) 0xffff0000) != (unsigned) 0)
- || (GET_CODE (src) == SYMBOL_REF)
- || (GET_CODE (src) == LABEL_REF)
- || (GET_CODE (src) == CONST))
- {
- rtx xoperands[2];
- xoperands[0] = dest;
- xoperands[1] = src;
-
- CC_STATUS_PARTIAL_INIT;
- /* Output the `orh' insn. */
- output_asm_insn ("orh %H1,%?r0,%0", xoperands);
-
- /* Output the branch instruction next. */
- output_asm_insn (template, operands);
-
- /* Now output the `or' insn. */
- output_asm_insn ("or %L1,%0,%0", xoperands);
- }
- else if ((GET_CODE (src) == MEM
- && CONSTANT_ADDRESS_P (XEXP (src, 0)))
- || (GET_CODE (dest) == MEM
- && CONSTANT_ADDRESS_P (XEXP (dest, 0))))
- {
- rtx xoperands[2];
- const char *split_template;
- xoperands[0] = dest;
- xoperands[1] = src;
-
- /* Output the `orh' insn. */
- if (GET_CODE (src) == MEM)
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && cc_prev_status.mdep == XEXP (operands[1], 0)))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h1,%?r0,%?r31", xoperands);
- }
- split_template = load_opcode (GET_MODE (dest),
- "%L1(%?r31),%0", dest);
- }
- else
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && cc_prev_status.mdep == XEXP (operands[0], 0)))
- {
- CC_STATUS_INIT;
- output_asm_insn ("orh %h0,%?r0,%?r31", xoperands);
- }
- split_template = store_opcode (GET_MODE (dest),
- "%r1,%L0(%?r31)", src);
- }
-
- /* Output the branch instruction next. */
- output_asm_insn (template, operands);
-
- /* Now output the load or store.
- No need to do a CC_STATUS_INIT, because we are branching anyway. */
- output_asm_insn (split_template, xoperands);
- }
- else
- {
- int insn_code_number;
- rtx pat = gen_rtx_SET (VOIDmode, dest, src);
- rtx delay_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, pat, -1, 0, 0);
- int i;
-
- /* Output the branch instruction first. */
- output_asm_insn (template, operands);
-
- /* Now recognize the insn which we put in its delay slot.
- We must do this after outputting the branch insn,
- since operands may just be a pointer to `recog_data.operand'. */
- INSN_CODE (delay_insn) = insn_code_number
- = recog (pat, delay_insn, NULL);
- if (insn_code_number == -1)
- abort ();
-
- for (i = 0; i < insn_data[insn_code_number].n_operands; i++)
- {
- if (GET_CODE (recog_data.operand[i]) == SUBREG)
- alter_subreg (&recog_data.operand[i]);
- }
-
- insn_extract (delay_insn);
- if (! constrain_operands (1))
- fatal_insn_not_found (delay_insn);
-
- template = get_insn_template (insn_code_number, delay_insn);
- output_asm_insn (template, recog_data.operand);
- }
- CC_STATUS_INIT;
- return "";
-}
-
-/* Output a newly constructed insn DELAY_INSN. */
-const char *
-output_delay_insn (delay_insn)
- rtx delay_insn;
-{
- const char *template;
- int insn_code_number;
- int i;
-
- /* Now recognize the insn which we put in its delay slot.
- We must do this after outputting the branch insn,
- since operands may just be a pointer to `recog_data.operand'. */
- insn_code_number = recog_memoized (delay_insn);
- if (insn_code_number == -1)
- abort ();
-
- /* Extract the operands of this delay insn. */
- INSN_CODE (delay_insn) = insn_code_number;
- insn_extract (delay_insn);
-
- /* It is possible that this insn has not been properly scanned by final
- yet. If this insn's operands don't appear in the peephole's
- actual operands, then they won't be fixed up by final, so we
- make sure they get fixed up here. -- This is a kludge. */
- for (i = 0; i < insn_data[insn_code_number].n_operands; i++)
- {
- if (GET_CODE (recog_data.operand[i]) == SUBREG)
- alter_subreg (&recog_data.operand[i]);
- }
-
- if (! constrain_operands (1))
- abort ();
-
- cc_prev_status = cc_status;
-
- /* Update `cc_status' for this instruction.
- The instruction's output routine may change it further.
- If the output routine for a jump insn needs to depend
- on the cc status, it should look at cc_prev_status. */
-
- NOTICE_UPDATE_CC (PATTERN (delay_insn), delay_insn);
-
- /* Now get the template for what this insn would
- have been, without the branch. */
-
- template = get_insn_template (insn_code_number, delay_insn);
- output_asm_insn (template, recog_data.operand);
- return "";
-}
-#endif
-\f
-/* Special routine to convert an SFmode value represented as a
- CONST_DOUBLE into its equivalent unsigned long bit pattern.
- We convert the value from a double precision floating-point
- value to single precision first, and thence to a bit-wise
- equivalent unsigned long value. This routine is used when
- generating an immediate move of an SFmode value directly
- into a general register because the svr4 assembler doesn't
- grok floating literals in instruction operand contexts. */
-
-unsigned long
-sfmode_constant_to_ulong (x)
- rtx x;
-{
- REAL_VALUE_TYPE d;
- unsigned long l;
-
- if (GET_CODE (x) != CONST_DOUBLE || GET_MODE (x) != SFmode)
- abort ();
-
- REAL_VALUE_FROM_CONST_DOUBLE (d, x);
- REAL_VALUE_TO_TARGET_SINGLE (d, l);
- return l;
-}
-\f
-/* This function generates the assembly code for function entry.
-
- ASM_FILE is a stdio stream to output the code to.
- SIZE is an int: how many units of temporary storage to allocate.
-
- Refer to the array `regs_ever_live' to determine which registers
- to save; `regs_ever_live[I]' is nonzero if register number I
- is ever used in the function. This macro is responsible for
- knowing which registers should not be saved even if used.
-
- NOTE: `frame_lower_bytes' is the count of bytes which will lie
- between the new `fp' value and the new `sp' value after the
- prologue is done. `frame_upper_bytes' is the count of bytes
- that will lie between the new `fp' and the *old* `sp' value
- after the new `fp' is setup (in the prologue). The upper
- part of each frame always includes at least 2 words (8 bytes)
- to hold the saved frame pointer and the saved return address.
-
- The svr4 ABI for the i860 now requires that the values of the
- stack pointer and frame pointer registers be kept aligned to
- 16-byte boundaries at all times. We obey that restriction here.
-
- The svr4 ABI for the i860 is entirely vague when it comes to specifying
- exactly where the "preserved" registers should be saved. The native
- svr4 C compiler I now have doesn't help to clarify the requirements
- very much because it is plainly out-of-date and non-ABI-compliant
- (in at least one important way, i.e. how it generates function
- epilogues).
-
- The native svr4 C compiler saves the "preserved" registers (i.e.
- r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
- offsets from the frame pointer).
-
- Previous versions of GCC also saved the "preserved" registers in the
- "negative" part of the frame, but they saved them using positive
- offsets from the (adjusted) stack pointer (after it had been adjusted
- to allocate space for the new frame). That's just plain wrong
- because if the current function calls alloca(), the stack pointer
- will get moved, and it will be impossible to restore the registers
- properly again after that.
-
- Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
- by copying their values either into various "preserved" registers or
- into stack slots in the lower part of the current frame (as seemed
- appropriate, depending upon subsequent usage of these values).
-
- Here we want to save the preserved registers at some offset from the
- frame pointer register so as to avoid any possible problems arising
- from calls to alloca(). We can either save them at small positive
- offsets from the frame pointer, or at small negative offsets from
- the frame pointer. If we save them at small negative offsets from
- the frame pointer (i.e. in the lower part of the frame) then we
- must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
- many bytes of space we plan to use in the lower part of the frame
- for this purpose. Since other parts of the compiler reference the
- value of STARTING_FRAME_OFFSET long before final() calls this function,
- we would have to go ahead and assume the worst-case storage requirements
- for saving all of the "preserved" registers (and use that number, i.e.
- `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
- the lower part of the frame. That could potentially be very wasteful,
- and that wastefulness could really hamper people compiling for embedded
- i860 targets with very tight limits on stack space. Thus, we choose
- here to save the preserved registers in the upper part of the
- frame, so that we can decide at the very last minute how much (or how
- little) space we must allocate for this purpose.
-
- To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
- registers must always be saved so that the saved values of registers
- with higher numbers are at higher addresses. We obey that restriction
- here.
-
- There are two somewhat different ways that you can generate prologues
- here... i.e. pedantically ABI-compliant, and the "other" way. The
- "other" way is more consistent with what is currently generated by the
- "native" svr4 C compiler for the i860. That's important if you want
- to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
- The SVR4 SDB for the i860 insists on having function prologues be
- non-ABI-compliant!
-
- To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
- in the i860svr4.h file. (By default this is *not* defined).
-
- The differences between the ABI-compliant and non-ABI-compliant prologues
- are that (a) the ABI version seems to require the use of *signed*
- (rather than unsigned) adds and subtracts, and (b) the ordering of
- the various steps (e.g. saving preserved registers, saving the
- return address, setting up the new frame pointer value) is different.
-
- For strict ABI compliance, it seems to be the case that the very last
- thing that is supposed to happen in the prologue is getting the frame
- pointer set to its new value (but only after everything else has
- already been properly setup). We do that here, but only if the symbol
- I860_STRICT_ABI_PROLOGUES is defined.
-*/
-
-#ifndef STACK_ALIGNMENT
-#define STACK_ALIGNMENT 16
-#endif
-
-const char *current_function_original_name;
-
-static int must_preserve_r1;
-static unsigned must_preserve_bytes;
-
-static void
-i860_output_function_prologue (asm_file, local_bytes)
- register FILE *asm_file;
- register HOST_WIDE_INT local_bytes;
-{
- register HOST_WIDE_INT frame_lower_bytes;
- register HOST_WIDE_INT frame_upper_bytes;
- register HOST_WIDE_INT total_fsize;
- register unsigned preserved_reg_bytes = 0;
- register unsigned i;
- register unsigned preserved_so_far = 0;
-
- must_preserve_r1 = (optimize < 2 || ! leaf_function_p ());
- must_preserve_bytes = 4 + (must_preserve_r1 ? 4 : 0);
-
- /* Count registers that need preserving. Ignore r0. It never needs
- preserving. */
-
- for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
- {
- if (regs_ever_live[i] && ! call_used_regs[i])
- preserved_reg_bytes += 4;
- }
-
- /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
-
- frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
- /* The upper part of each frame will contain the saved fp,
- the saved r1, and stack slots for all of the other "preserved"
- registers that we find we will need to save & restore. */
-
- frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
-
- /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
-
- frame_upper_bytes
- = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
- total_fsize = frame_upper_bytes + frame_lower_bytes;
-
-#ifndef I860_STRICT_ABI_PROLOGUES
-
- /* There are two kinds of function prologues.
- You use the "small" version if the total frame size is
- small enough so that it can fit into an immediate 16-bit
- value in one instruction. Otherwise, you use the "large"
- version of the function prologue. */
-
- if (total_fsize > 0x7fff)
- {
- /* Adjust the stack pointer. The ABI sez to do this using `adds',
- but the native C compiler on svr4 uses `addu'. */
-
- fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
- frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
-
- /* Save the old frame pointer. */
-
- fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
- i860_reg_prefix, i860_reg_prefix);
-
- /* Setup the new frame pointer. The ABI sez to do this after
- preserving registers (using adds), but that's not what the
- native C compiler on svr4 does. */
-
- fprintf (asm_file, "\taddu 0,%ssp,%sfp\n",
- i860_reg_prefix, i860_reg_prefix);
-
- /* Get the value of frame_lower_bytes into r31. */
-
- fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
- frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
- fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
- frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
-
- /* Now re-adjust the stack pointer using the value in r31.
- The ABI sez to do this with `subs' but SDB may prefer `subu'. */
-
- fprintf (asm_file, "\tsubu %ssp,%sr31,%ssp\n",
- i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
- /* Preserve registers. The ABI sez to do this before setting
- up the new frame pointer, but that's not what the native
- C compiler on svr4 does. */
-
- for (i = 1; i < 32; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
- i860_reg_prefix, reg_names[i],
- must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- for (i = 32; i < 64; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
- i860_reg_prefix, reg_names[i],
- must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- /* Save the return address. */
-
- if (must_preserve_r1)
- fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
- i860_reg_prefix, i860_reg_prefix);
- }
- else
- {
- /* Adjust the stack pointer. The ABI sez to do this using `adds',
- but the native C compiler on svr4 uses `addu'. */
-
- fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
- total_fsize, i860_reg_prefix, i860_reg_prefix);
-
- /* Save the old frame pointer. */
-
- fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
- i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
-
- /* Setup the new frame pointer. The ABI sez to do this after
- preserving registers and after saving the return address,
- (and its saz to do this using adds), but that's not what the
- native C compiler on svr4 does. */
-
- fprintf (asm_file, "\taddu %d,%ssp,%sfp\n",
- frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
-
- /* Preserve registers. The ABI sez to do this before setting
- up the new frame pointer, but that's not what the native
- compiler on svr4 does. */
-
- for (i = 1; i < 32; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
- i860_reg_prefix, reg_names[i],
- must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- for (i = 32; i < 64; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
- i860_reg_prefix, reg_names[i],
- must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- /* Save the return address. The ABI sez to do this earlier,
- and also via an offset from %sp, but the native C compiler
- on svr4 does it later (i.e. now) and uses an offset from
- %fp. */
-
- if (must_preserve_r1)
- fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
- i860_reg_prefix, i860_reg_prefix);
- }
-
-#else /* defined(I860_STRICT_ABI_PROLOGUES) */
-
- /* There are two kinds of function prologues.
- You use the "small" version if the total frame size is
- small enough so that it can fit into an immediate 16-bit
- value in one instruction. Otherwise, you use the "large"
- version of the function prologue. */
-
- if (total_fsize > 0x7fff)
- {
- /* Adjust the stack pointer (thereby allocating a new frame). */
-
- fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
- frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
-
- /* Save the caller's frame pointer. */
-
- fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
- i860_reg_prefix, i860_reg_prefix);
-
- /* Save return address. */
-
- if (must_preserve_r1)
- fprintf (asm_file, "\tst.l %sr1,4(%ssp)\n",
- i860_reg_prefix, i860_reg_prefix);
-
- /* Get the value of frame_lower_bytes into r31 for later use. */
-
- fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
- frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
- fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
- frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
-
- /* Now re-adjust the stack pointer using the value in r31. */
-
- fprintf (asm_file, "\tsubs %ssp,%sr31,%ssp\n",
- i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
- /* Pre-compute value to be used as the new frame pointer. */
-
- fprintf (asm_file, "\tadds %ssp,%sr31,%sr31\n",
- i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
- /* Preserve registers. */
-
- for (i = 1; i < 32; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tst.l %s%s,%d(%sr31)\n",
- i860_reg_prefix, reg_names[i],
- must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- for (i = 32; i < 64; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tfst.l %s%s,%d(%sr31)\n",
- i860_reg_prefix, reg_names[i],
- must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- /* Actually set the new value of the frame pointer. */
-
- fprintf (asm_file, "\tmov %sr31,%sfp\n",
- i860_reg_prefix, i860_reg_prefix);
- }
- else
- {
- /* Adjust the stack pointer. */
-
- fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
- total_fsize, i860_reg_prefix, i860_reg_prefix);
-
- /* Save the caller's frame pointer. */
-
- fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
- i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
-
- /* Save the return address. */
-
- if (must_preserve_r1)
- fprintf (asm_file, "\tst.l %sr1,%d(%ssp)\n",
- i860_reg_prefix, frame_lower_bytes + 4, i860_reg_prefix);
-
- /* Preserve registers. */
-
- for (i = 1; i < 32; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tst.l %s%s,%d(%ssp)\n",
- i860_reg_prefix, reg_names[i],
- frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- for (i = 32; i < 64; i++)
- if (regs_ever_live[i] && ! call_used_regs[i])
- fprintf (asm_file, "\tfst.l %s%s,%d(%ssp)\n",
- i860_reg_prefix, reg_names[i],
- frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
- i860_reg_prefix);
-
- /* Setup the new frame pointer. */
-
- fprintf (asm_file, "\tadds %d,%ssp,%sfp\n",
- frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
- }
-#endif /* defined(I860_STRICT_ABI_PROLOGUES) */
-
-#ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
- ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file);
-#endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
-}
-\f
-/* This function generates the assembly code for function exit.
-
- ASM_FILE is a stdio stream to output the code to.
- SIZE is an int: how many units of temporary storage to allocate.
-
- The function epilogue should not depend on the current stack pointer!
- It should use the frame pointer only. This is mandatory because
- of alloca; we also take advantage of it to omit stack adjustments
- before returning.
-
- Note that when we go to restore the preserved register values we must
- not try to address their slots by using offsets from the stack pointer.
- That's because the stack pointer may have been moved during the function
- execution due to a call to alloca(). Rather, we must restore all
- preserved registers via offsets from the frame pointer value.
-
- Note also that when the current frame is being "popped" (by adjusting
- the value of the stack pointer) on function exit, we must (for the
- sake of alloca) set the new value of the stack pointer based upon
- the current value of the frame pointer. We can't just add what we
- believe to be the (static) frame size to the stack pointer because
- if we did that, and alloca() had been called during this function,
- we would end up returning *without* having fully deallocated all of
- the space grabbed by alloca. If that happened, and a function
- containing one or more alloca() calls was called over and over again,
- then the stack would grow without limit!
-
- Finally note that the epilogues generated here are completely ABI
- compliant. They go out of their way to insure that the value in
- the frame pointer register is never less than the value in the stack
- pointer register. It's not clear why this relationship needs to be
- maintained at all times, but maintaining it only costs one extra
- instruction, so what the hell.
-*/
-
-/* This corresponds to a version 4 TDESC structure. Lower numbered
- versions successively omit the last word of the structure. We
- don't try to handle version 5 here. */
-
-typedef struct TDESC_flags {
- int version:4;
- int reg_packing:1;
- int callable_block:1;
- int reserved:4;
- int fregs:6; /* fp regs 2-7 */
- int iregs:16; /* regs 0-15 */
-} TDESC_flags;
-
-typedef struct TDESC {
- TDESC_flags flags;
- int integer_reg_offset; /* same as must_preserve_bytes */
- int floating_point_reg_offset;
- unsigned int positive_frame_size; /* same as frame_upper_bytes */
- unsigned int negative_frame_size; /* same as frame_lower_bytes */
-} TDESC;
-
-static void
-i860_output_function_epilogue (asm_file, local_bytes)
- register FILE *asm_file;
- register HOST_WIDE_INT local_bytes;
-{
- register HOST_WIDE_INT frame_upper_bytes;
- register HOST_WIDE_INT frame_lower_bytes;
- register HOST_WIDE_INT preserved_reg_bytes = 0;
- register unsigned i;
- register unsigned restored_so_far = 0;
- register unsigned int_restored;
- register unsigned mask;
- unsigned intflags=0;
- register TDESC_flags *flags = (TDESC_flags *) &intflags;
-#ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
- const char *long_op = integer_asm_op (4, TRUE);
-#endif
-
- flags->version = 4;
- flags->reg_packing = 1;
- flags->iregs = 8; /* old fp always gets saved */
-
- /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
-
- frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
- /* Count the number of registers that were preserved in the prologue.
- Ignore r0. It is never preserved. */
-
- for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
- {
- if (regs_ever_live[i] && ! call_used_regs[i])
- preserved_reg_bytes += 4;
- }
-
- /* The upper part of each frame will contain only saved fp,
- the saved r1, and stack slots for all of the other "preserved"
- registers that we find we will need to save & restore. */
-
- frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
-
- /* Round-up frame_upper_bytes so that t is a multiple of 16. */
-
- frame_upper_bytes
- = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
- /* Restore all of the "preserved" registers that need restoring. */
-
- mask = 2;
-
- for (i = 1; i < 32; i++, mask<<=1)
- if (regs_ever_live[i] && ! call_used_regs[i]) {
- fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n",
- must_preserve_bytes + (4 * restored_so_far++),
- i860_reg_prefix, i860_reg_prefix, reg_names[i]);
- if (i > 3 && i < 16)
- flags->iregs |= mask;
- }
-
- int_restored = restored_so_far;
- mask = 1;
-
- for (i = 32; i < 64; i++) {
- if (regs_ever_live[i] && ! call_used_regs[i]) {
- fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n",
- must_preserve_bytes + (4 * restored_so_far++),
- i860_reg_prefix, i860_reg_prefix, reg_names[i]);
- if (i > 33 && i < 40)
- flags->fregs |= mask;
- }
- if (i > 33 && i < 40)
- mask<<=1;
- }
-
- /* Get the value we plan to use to restore the stack pointer into r31. */
-
- fprintf (asm_file, "\tadds %d,%sfp,%sr31\n",
- frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
-
- /* Restore the return address and the old frame pointer. */
-
- if (must_preserve_r1) {
- fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n",
- i860_reg_prefix, i860_reg_prefix);
- flags->iregs |= 2;
- }
-
- fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n",
- i860_reg_prefix, i860_reg_prefix);
-
- /* Return and restore the old stack pointer value. */
-
- fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n",
- i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
-#ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
- if (! frame_lower_bytes) {
- flags->version--;
- if (! frame_upper_bytes) {
- flags->version--;
- if (restored_so_far == int_restored) /* No FP saves */
- flags->version--;
- }
- }
- assemble_name(asm_file,current_function_original_name);
- fputs(".TDESC:\n", asm_file);
- fprintf(asm_file, "%s 0x%0x\n", long_op, intflags);
- fprintf(asm_file, "%s %d\n", long_op,
- int_restored ? must_preserve_bytes : 0);
- if (flags->version > 1) {
- fprintf(asm_file, "%s %d\n", long_op,
- (restored_so_far == int_restored) ? 0 : must_preserve_bytes +
- (4 * int_restored));
- if (flags->version > 2) {
- fprintf(asm_file, "%s %d\n", long_op, frame_upper_bytes);
- if (flags->version > 3)
- fprintf(asm_file, "%s %d\n", long_op, frame_lower_bytes);
- }
- }
- tdesc_section();
- fprintf(asm_file, "%s ", long_op);
- assemble_name(asm_file, current_function_original_name);
- fprintf(asm_file, "\n%s ", long_op);
- assemble_name(asm_file, current_function_original_name);
- fputs(".TDESC\n", asm_file);
- text_section();
-#endif
-}
-\f
-
-/* Expand a library call to __builtin_saveregs. */
-rtx
-i860_saveregs ()
-{
- rtx fn = gen_rtx_SYMBOL_REF (Pmode, "__builtin_saveregs");
- rtx save = gen_reg_rtx (Pmode);
- rtx valreg = LIBCALL_VALUE (Pmode);
- rtx ret;
-
- /* The return value register overlaps the first argument register.
- Save and restore it around the call. */
- emit_move_insn (save, valreg);
- ret = emit_library_call_value (fn, NULL_RTX, 1, Pmode, 0);
- if (GET_CODE (ret) != REG || REGNO (ret) < FIRST_PSEUDO_REGISTER)
- ret = copy_to_reg (ret);
- emit_move_insn (valreg, save);
-
- return ret;
-}
-
-tree
-i860_build_va_list ()
-{
- tree field_ireg_used, field_freg_used, field_reg_base, field_mem_ptr;
- tree record;
-
- record = make_node (RECORD_TYPE);
-
- field_ireg_used = build_decl (FIELD_DECL, get_identifier ("__ireg_used"),
- unsigned_type_node);
- field_freg_used = build_decl (FIELD_DECL, get_identifier ("__freg_used"),
- unsigned_type_node);
- field_reg_base = build_decl (FIELD_DECL, get_identifier ("__reg_base"),
- ptr_type_node);
- field_mem_ptr = build_decl (FIELD_DECL, get_identifier ("__mem_ptr"),
- ptr_type_node);
-
- DECL_FIELD_CONTEXT (field_ireg_used) = record;
- DECL_FIELD_CONTEXT (field_freg_used) = record;
- DECL_FIELD_CONTEXT (field_reg_base) = record;
- DECL_FIELD_CONTEXT (field_mem_ptr) = record;
-
-#ifdef I860_SVR4_VA_LIST
- TYPE_FIELDS (record) = field_ireg_used;
- TREE_CHAIN (field_ireg_used) = field_freg_used;
- TREE_CHAIN (field_freg_used) = field_reg_base;
- TREE_CHAIN (field_reg_base) = field_mem_ptr;
-#else
- TYPE_FIELDS (record) = field_reg_base;
- TREE_CHAIN (field_reg_base) = field_mem_ptr;
- TREE_CHAIN (field_mem_ptr) = field_ireg_used;
- TREE_CHAIN (field_ireg_used) = field_freg_used;
-#endif
-
- layout_type (record);
- return record;
-}
-
-void
-i860_va_start (stdarg_p, valist, nextarg)
- int stdarg_p;
- tree valist;
- rtx nextarg;
-{
- tree saveregs, t;
-
- saveregs = make_tree (build_pointer_type (va_list_type_node),
- expand_builtin_saveregs ());
- saveregs = build1 (INDIRECT_REF, va_list_type_node, saveregs);
-
- if (stdarg_p)
- {
- tree field_ireg_used, field_freg_used, field_reg_base, field_mem_ptr;
- tree ireg_used, freg_used, reg_base, mem_ptr;
-
-#ifdef I860_SVR4_VA_LIST
- field_ireg_used = TYPE_FIELDS (va_list_type_node);
- field_freg_used = TREE_CHAIN (field_ireg_used);
- field_reg_base = TREE_CHAIN (field_freg_used);
- field_mem_ptr = TREE_CHAIN (field_reg_base);
-#else
- field_reg_base = TYPE_FIELDS (va_list_type_node);
- field_mem_ptr = TREE_CHAIN (field_reg_base);
- field_ireg_used = TREE_CHAIN (field_mem_ptr);
- field_freg_used = TREE_CHAIN (field_ireg_used);
-#endif
-
- ireg_used = build (COMPONENT_REF, TREE_TYPE (field_ireg_used),
- valist, field_ireg_used);
- freg_used = build (COMPONENT_REF, TREE_TYPE (field_freg_used),
- valist, field_freg_used);
- reg_base = build (COMPONENT_REF, TREE_TYPE (field_reg_base),
- valist, field_reg_base);
- mem_ptr = build (COMPONENT_REF, TREE_TYPE (field_mem_ptr),
- valist, field_mem_ptr);
-
- t = build_int_2 (current_function_args_info.ints, 0);
- t = build (MODIFY_EXPR, TREE_TYPE (ireg_used), ireg_used, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- t = build_int_2 (ROUNDUP (current_function_args_info.floats, 8), 0);
- t = build (MODIFY_EXPR, TREE_TYPE (freg_used), freg_used, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- t = build (COMPONENT_REF, TREE_TYPE (field_reg_base),
- saveregs, field_reg_base);
- t = build (MODIFY_EXPR, TREE_TYPE (reg_base), reg_base, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- t = make_tree (ptr_type_node, nextarg);
- t = build (MODIFY_EXPR, TREE_TYPE (mem_ptr), mem_ptr, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- }
- else
- {
- t = build (MODIFY_EXPR, va_list_type_node, valist, saveregs);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- }
-}
-
-#define NUM_PARM_FREGS 8
-#define NUM_PARM_IREGS 12
-#ifdef I860_SVR4_VARARGS
-#define FREG_OFFSET 0
-#define IREG_OFFSET (NUM_PARM_FREGS * UNITS_PER_WORD)
-#else
-#define FREG_OFFSET (NUM_PARM_IREGS * UNITS_PER_WORD)
-#define IREG_OFFSET 0
-#endif
-
-rtx
-i860_va_arg (valist, type)
- tree valist, type;
-{
- tree field_ireg_used, field_freg_used, field_reg_base, field_mem_ptr;
- tree type_ptr_node, t;
- rtx lab_over = NULL_RTX;
- rtx ret, val;
- HOST_WIDE_INT align;
-
-#ifdef I860_SVR4_VA_LIST
- field_ireg_used = TYPE_FIELDS (va_list_type_node);
- field_freg_used = TREE_CHAIN (field_ireg_used);
- field_reg_base = TREE_CHAIN (field_freg_used);
- field_mem_ptr = TREE_CHAIN (field_reg_base);
-#else
- field_reg_base = TYPE_FIELDS (va_list_type_node);
- field_mem_ptr = TREE_CHAIN (field_reg_base);
- field_ireg_used = TREE_CHAIN (field_mem_ptr);
- field_freg_used = TREE_CHAIN (field_ireg_used);
-#endif
-
- field_ireg_used = build (COMPONENT_REF, TREE_TYPE (field_ireg_used),
- valist, field_ireg_used);
- field_freg_used = build (COMPONENT_REF, TREE_TYPE (field_freg_used),
- valist, field_freg_used);
- field_reg_base = build (COMPONENT_REF, TREE_TYPE (field_reg_base),
- valist, field_reg_base);
- field_mem_ptr = build (COMPONENT_REF, TREE_TYPE (field_mem_ptr),
- valist, field_mem_ptr);
-
- ret = gen_reg_rtx (Pmode);
- type_ptr_node = build_pointer_type (type);
-
- if (! AGGREGATE_TYPE_P (type))
- {
- int nparm, incr, ofs;
- tree field;
- rtx lab_false;
-
- if (FLOAT_TYPE_P (type))
- {
- field = field_freg_used;
- nparm = NUM_PARM_FREGS;
- incr = 2;
- ofs = FREG_OFFSET;
- }
- else
- {
- field = field_ireg_used;
- nparm = NUM_PARM_IREGS;
- incr = int_size_in_bytes (type) / UNITS_PER_WORD;
- ofs = IREG_OFFSET;
- }
-
- lab_false = gen_label_rtx ();
- lab_over = gen_label_rtx ();
-
- emit_cmp_and_jump_insns (expand_expr (field, NULL_RTX, 0, 0),
- GEN_INT (nparm - incr), GT, const0_rtx,
- TYPE_MODE (TREE_TYPE (field)),
- TREE_UNSIGNED (field), lab_false);
-
- t = fold (build (POSTINCREMENT_EXPR, TREE_TYPE (field), field,
- build_int_2 (incr, 0)));
- TREE_SIDE_EFFECTS (t) = 1;
-
- t = fold (build (MULT_EXPR, TREE_TYPE (field), field,
- build_int_2 (UNITS_PER_WORD, 0)));
- TREE_SIDE_EFFECTS (t) = 1;
-
- t = fold (build (PLUS_EXPR, ptr_type_node, field_reg_base,
- fold (build (PLUS_EXPR, TREE_TYPE (field), t,
- build_int_2 (ofs, 0)))));
- TREE_SIDE_EFFECTS (t) = 1;
-
- val = expand_expr (t, ret, VOIDmode, EXPAND_NORMAL);
- if (val != ret)
- emit_move_insn (ret, val);
-
- emit_jump_insn (gen_jump (lab_over));
- emit_barrier ();
- emit_label (lab_false);
- }
-
- align = TYPE_ALIGN (type);
- if (align < BITS_PER_WORD)
- align = BITS_PER_WORD;
- align /= BITS_PER_UNIT;
-
- t = build (PLUS_EXPR, ptr_type_node, field_mem_ptr,
- build_int_2 (align - 1, 0));
- t = build (BIT_AND_EXPR, ptr_type_node, t, build_int_2 (-align, -1));
-
- val = expand_expr (t, ret, VOIDmode, EXPAND_NORMAL);
- if (val != ret)
- emit_move_insn (ret, val);
-
- t = fold (build (PLUS_EXPR, ptr_type_node,
- make_tree (ptr_type_node, ret),
- build_int_2 (int_size_in_bytes (type), 0)));
- t = build (MODIFY_EXPR, ptr_type_node, field_mem_ptr, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- if (lab_over)
- emit_label (lab_over);
-
- return ret;
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler, for Intel 860.
- Copyright (C) 1989, 1991, 1993, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002 Free Software Foundation, Inc.
- Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to
- the whims of the System V Release 4 assembler.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Note that some other tm.h files include this one and then override
- many of the definitions that relate to assembler syntax. */
-
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Di860 -Dunix -Asystem=unix -Asystem=svr4 -Acpu=i860 -Amachine=i860"
-
-/* Print subsidiary information on the compiler version in use. */
-#define TARGET_VERSION fprintf (stderr, " (i860)");
-
-/* Run-time compilation parameters selecting different hardware subsets
- or supersets.
-
- On the i860, we have one: TARGET_XP. This option allows gcc to generate
- additional instructions available only on the newer i860 XP (but not on
- the older i860 XR).
-*/
-
-extern int target_flags;
-
-/* Nonzero if we should generate code to use the fpu. */
-#define TARGET_XP (target_flags & 1)
-
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
- { {"xp", 1, N_("Generate code which uses the FPU")}, \
- {"noxp", -1, N_("Do not generate code which uses the FPU")}, \
- {"xr", -1, N_("Do not generate code which uses the FPU")}, \
- { "", TARGET_DEFAULT, NULL}}
-
-#define TARGET_DEFAULT 0
-\f
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields.
- This is a moot question on the i860 due to the lack of bit-field insns. */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-/* That is not true on i860 in the mode we will use. */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is the lowest
- numbered. */
-/* For the i860 this goes with BYTES_BIG_ENDIAN. */
-/* NOTE: GCC probably cannot support a big-endian i860
- because GCC fundamentally assumes that the order of words
- in memory as the same as the order in registers.
- That's not true for the big-endian i860.
- The big-endian i860 isn't important enough to
- justify the trouble of changing this assumption. */
-#define WORDS_BIG_ENDIAN 0
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 4
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#define STACK_BOUNDARY 128
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 64
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this. */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* Minimum size in bits of the largest boundary to which any
- and all fundamental data types supported by the hardware
- might need to be aligned. No data type wants to be aligned
- rounder than this. The i860 supports 128-bit (long double)
- floating point quantities, and the System V Release 4 i860
- ABI requires these to be aligned to 16-byte (128-bit)
- boundaries. */
-#define BIGGEST_ALIGNMENT 128
-
-/* Set this nonzero if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 1
-
-/* If bit field type is int, don't let it cross an int,
- and give entire struct the alignment of an int. */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-\f
-/* Standard register usage. */
-
-/* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers.
-
- i860 has 32 fullword registers and 32 floating point registers. */
-
-#define FIRST_PSEUDO_REGISTER 64
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
- On the i860, this includes the always-0 registers
- and fp, sp, arg pointer, and the return address.
- Also r31, used for special purposes for constant addresses. */
-#define FIXED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 1, \
- 1, 1, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31. */
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 0, 0, 0, 0, 0, 0, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1}
-
-/* Try to get a non-preserved register before trying to get one we will
- have to preserve. Try to get an FP register only *after* trying to
- get a general register, because it is relatively expensive to move
- into or out of an FP register. */
-
-#define REG_ALLOC_ORDER \
- {31, 30, 29, 28, 27, 26, 25, 24, \
- 23, 22, 21, 20, 19, 18, 17, 16, \
- 15, 14, 13, 12, 11, 10, 9, 8, \
- 7, 6, 5, 4, 3, 2, 1, 0, \
- 63, 62, 61, 60, 59, 58, 57, 56, \
- 55, 54, 53, 52, 51, 50, 49, 48, \
- 47, 46, 45, 44, 43, 42, 41, 40, \
- 39, 38, 37, 36, 35, 34, 33, 32}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers.
-
- On the i860, all registers hold 32 bits worth. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-#define REGNO_MODE_ALIGNED(REGNO, MODE) \
- (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-
- On the i860, we allow anything to go into any registers, but we require
- any sort of value going into the FP registers to be properly aligned
- (based on its size) within the FP register set.
-*/
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (((REGNO) < 32) \
- || (MODE) == VOIDmode || (MODE) == BLKmode \
- || REGNO_MODE_ALIGNED (REGNO, MODE))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
-/* I think that is not always true; alignment restrictions for doubles
- should not prevent tying them with singles. So try allowing that.
- On the other hand, don't let fixed and floating be tied;
- this restriction is not necessary, but may make better code. */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
- ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
- || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
- == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
- || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-/* i860 pc isn't overloaded on a register that the compiler knows about. */
-/* #define PC_REGNUM */
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM 2
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 3
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 28
-
-/* Register in which static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM 29
-
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM 16
-
-/* Register to use when a source of a floating-point zero is needed. */
-#define F0_REGNUM 32
-\f
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
-/* The i860 has two kinds of registers, hence four classes. */
-
-enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file. */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. */
-
-#define REG_CLASS_CONTENTS \
- {{0, 0}, {0xffffffff, 0}, \
- {0, 0xffffffff}, {0xffffffff, 0xffffffff}}
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'f' ? FP_REGS : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- For the i860, `I' is used for the range of constants
- an add/subtract insn can actually contain.
- But not including -0x8000, since we need
- to negate the constant sometimes.
- `J' is used for the range which is just zero (since that is R0).
- `K' is used for the range allowed in bte.
- `L' is used for the range allowed in logical insns. */
-
-#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff)
-
-#define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000)
-
-#define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff)
-
-#define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff \
- : (C) == 'J' ? (VALUE) == 0 \
- : (C) == 'K' ? (unsigned) (VALUE) < 0x20 \
- : (C) == 'L' ? (unsigned) (VALUE) < 0x10000 \
- : 0)
-
-/* Return non-zero if the given VALUE is acceptable for the
- constraint letter C. For the i860, constraint letter 'G'
- permits only a floating-point zero value. */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0 \
- && CONST_DOUBLE_HIGH ((VALUE)) == 0)
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class.
-
- If we are trying to put an integer constant into some register, prefer an
- integer register to an FP register. If we are trying to put a
- non-zero floating-point constant into some register, use an integer
- register if the constant is SFmode and GENERAL_REGS is one of our options.
- Otherwise, put the constant into memory.
-
- When reloading something smaller than a word, use a general reg
- rather than an FP reg. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
- ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS \
- : ((GET_MODE (X) == HImode || GET_MODE (X) == QImode) \
- && (CLASS) == ALL_REGS) \
- ? GENERAL_REGS \
- : (GET_CODE (X) == CONST_DOUBLE \
- && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
- && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')) \
- ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS \
- : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS) \
- : NO_REGS) \
- : (CLASS))
-
-/* Return the register class of a scratch register needed to copy IN into
- a register in CLASS in MODE. If it can be done directly, NO_REGS is
- returned. */
-
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
- ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS)
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS. */
-/* On the i860, this is the size of MODE in words. */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-\f
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- that is, each additional local variable allocated
- goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated. */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by.
- On the i860, don't define this because there are no push insns. */
-/* #define PUSH_ROUNDING(BYTES) */
-
-/* Offset of first parameter from the argument pointer register value. */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
- popped when returning from a subroutine call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
- SIZE is the number of bytes of arguments passed on the stack. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-/* On the i860, the value register depends on the mode. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), \
- (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
- ? 40 : 16))
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG (MODE, \
- (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \
- ? 40 : 16))
-
-/* 1 if N is a possible register number for a function value
- as seen by the caller. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16)
-
-/* 1 if N is a possible register number for function argument passing.
- On the i860, these are r16-r27 and f8-f15. */
-
-#define FUNCTION_ARG_REGNO_P(N) \
- (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40))
-\f
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go.
-
- On the i860, we must count separately the number of general registers used
- and the number of float registers used. */
-
-struct cumulative_args { int ints, floats; };
-#define CUMULATIVE_ARGS struct cumulative_args
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0.
-
- On the i860, the general-reg offset normally starts at 0,
- but starts at 4 bytes
- when the function gets a structure-value-address as an
- invisible first argument. */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
- ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \
- ? 4 : 0), \
- (CUM).floats = 0)
-
-/* Machine-specific subroutines of the following macros. */
-#define CEILING(X,Y) (((X) + (Y) - 1) / (Y))
-#define ROUNDUP(X,Y) (CEILING ((X), (Y)) * (Y))
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.)
- Floats, and doubleword ints, are returned in f regs;
- other ints, in r regs.
- Aggregates, even short ones, are passed in memory. */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
- || TREE_CODE ((TYPE)) == UNION_TYPE) \
- ? 0 \
- : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
- ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) \
- + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
- : GET_MODE_CLASS ((MODE)) == MODE_INT \
- ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \
- + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
- : 0)
-
-/* Determine where to put an argument to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis). */
-
-/* On the i860, the first 12 words of integer arguments go in r16-r27,
- and the first 8 words of floating arguments go in f8-f15.
- DImode values are treated as floats. */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
- ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
- || TREE_CODE ((TYPE)) == UNION_TYPE) \
- ? 0 \
- : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
- ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \
- ? gen_rtx_REG ((MODE), \
- 40 + (ROUNDUP ((CUM).floats, \
- GET_MODE_SIZE ((MODE))) \
- / 4)) \
- : 0) \
- : GET_MODE_CLASS ((MODE)) == MODE_INT \
- ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \
- ? gen_rtx_REG ((MODE), \
- 16 + (ROUNDUP ((CUM).ints, \
- GET_MODE_SIZE ((MODE))) \
- / 4)) \
- : 0) \
- : 0)
-
-/* For an arg passed partly in registers and partly in memory,
- this is the number of registers used.
- For args passed entirely in registers or entirely in memory, zero. */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* If defined, a C expression that gives the alignment boundary, in
- bits, of an argument with the specified mode and type. If it is
- not defined, `PARM_BOUNDARY' is used for all arguments. */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
- (((TYPE) != 0) \
- ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
- ? PARM_BOUNDARY \
- : TYPE_ALIGN(TYPE)) \
- : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
- ? PARM_BOUNDARY \
- : GET_MODE_ALIGNMENT(MODE)))
-
-/* Output a no-op just before the beginning of the function,
- to ensure that there does not appear to be a delayed branch there.
- Such a thing would confuse interrupt recovery. */
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
- fprintf (FILE, "\tnop\n")
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- abort ();
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Generate necessary RTL for __builtin_saveregs(). */
-#define EXPAND_BUILTIN_SAVEREGS() \
- i860_saveregs()
-
-/* Define the `__builtin_va_list' type for the ABI. */
-#define BUILD_VA_LIST_TYPE(VALIST) \
- (VALIST) = i860_build_va_list ()
-
-/* Implement `va_start' for varargs and stdarg. */
-#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
- i860_va_start (stdarg, valist, nextarg)
-
-/* Implement `va_arg'. */
-#define EXPAND_BUILTIN_VA_ARG(valist, type) \
- i860_va_arg (valist, type)
-
-/* Store in the variable DEPTH the initial difference between the
- frame pointer reg contents and the stack pointer reg contents,
- as of the start of the function body. This depends on the layout
- of the fixed parts of the stack frame and on how registers are saved.
-
- On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this
- macro doesn't matter. But it must be defined. */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
- do { (DEPTH) = 0; } while (0)
-
-/* Output assembler code for a block containing the constant parts
- of a trampoline, leaving space for the variable parts. */
-
-/* On the i860, the trampoline contains five instructions:
- orh #TOP_OF_FUNCTION,r0,r31
- or #BOTTOM_OF_FUNCTION,r31,r31
- orh #TOP_OF_STATIC,r0,r29
- bri r31
- or #BOTTOM_OF_STATIC,r29,r29 */
-#define TRAMPOLINE_TEMPLATE(FILE) \
-{ \
- assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xec1f0000)); \
- assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xe7ff0000)); \
- assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xec1d0000)); \
- assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x4000f800)); \
- assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xe7bd0000)); \
-}
-
-/* Length in units of the trampoline for entering a nested function. */
-
-#define TRAMPOLINE_SIZE 20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function.
-
- Store hi function at +0, low function at +4,
- hi static at +8, low static at +16 */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- rtx cxt = force_reg (Pmode, CXT); \
- rtx fn = force_reg (Pmode, FNADDR); \
- rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, \
- size_int (16), 0, 0); \
- rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn, \
- size_int (16), 0, 0); \
- emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 16)), \
- gen_lowpart (HImode, cxt)); \
- emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 4)), \
- gen_lowpart (HImode, fn)); \
- emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 8)), \
- gen_lowpart (HImode, hi_cxt)); \
- emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 0)), \
- gen_lowpart (HImode, hi_fn)); \
-}
-\f
-/* Addressing modes, and classification of registers for them. */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-(((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)
-
-/* Now macros that check whether X is a register and also,
- strictly, whether it is in a specified class.
-
- These macros are specific to the i860, and may be used only
- in code for printing assembler insns and in conditions for
- define_optimization. */
-
-/* 1 if X is an fp register. */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-\f
-/* Maximum number of registers that can appear in a valid memory address. */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
-
- On the Sparc, this is anything but a CONST_DOUBLE.
- Let's try permitting CONST_DOUBLEs and see what happens. */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- On the i860, the actual addresses must be REG+REG or REG+SMALLINT.
- But we can treat a SYMBOL_REF as legitimate if it is part of this
- function's constant-pool, because such addresses can actually
- be output as REG+SMALLINT.
-
- The displacement in an address must be a multiple of the alignment.
-
- Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P)
- a legitimate address, regardless. Because the only insns which can use
- memory are load or store insns, the added hair in the machine description
- is not that bad. It should also speed up the compiler by halving the number
- of insns it must manage for each (MEM (SYMBOL_REF ...)) involved. */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ if (GET_CODE (X) == REG) \
- { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
- else if (GET_CODE (X) == PLUS) \
- { \
- if (GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
- { \
- if (GET_CODE (XEXP (X, 1)) == CONST_INT \
- && INTVAL (XEXP (X, 1)) >= -0x8000 \
- && INTVAL (XEXP (X, 1)) < 0x8000 \
- && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
- goto ADDR; \
- } \
- else if (GET_CODE (XEXP (X, 1)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
- { \
- if (GET_CODE (XEXP (X, 0)) == CONST_INT \
- && INTVAL (XEXP (X, 0)) >= -0x8000 \
- && INTVAL (XEXP (X, 0)) < 0x8000 \
- && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
- goto ADDR; \
- } \
- } \
- else if (CONSTANT_ADDRESS_P (X)) \
- goto ADDR; \
-}
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
-
-/* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT.
- Also change a symbolic constant to a REG,
- though that may not be necessary. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
-{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
- (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
- force_operand (XEXP (X, 0), 0)); \
- if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
- (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
- force_operand (XEXP (X, 1), 0)); \
- if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
- (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
- force_operand (XEXP (X, 0), 0)); \
- if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
- (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
- force_operand (XEXP (X, 1), 0)); \
- if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \
- && GET_CODE (XEXP (X, 0)) != CONST_INT) \
- (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
- copy_to_mode_reg (SImode, XEXP (X, 0))); \
- if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \
- && GET_CODE (XEXP (X, 1)) != CONST_INT) \
- (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
- copy_to_mode_reg (SImode, XEXP (X, 1))); \
- if (GET_CODE (x) == SYMBOL_REF) \
- (X) = copy_to_reg (X); \
- if (GET_CODE (x) == CONST) \
- (X) = copy_to_reg (X); \
- if (memory_address_p (MODE, X)) \
- goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for.
- On the i860 this is never true.
- There are some addresses that are invalid in wide modes
- but valid for narrower modes, but they shouldn't affect
- the places that use this macro. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-\f
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Must pass floats to libgcc functions as doubles. */
-#define LIBGCC_NEEDS_DOUBLE 1
-
-#define DIVSI3_LIBCALL "*.div"
-#define UDIVSI3_LIBCALL "*.udiv"
-#define REMSI3_LIBCALL "*.rem"
-#define UREMSI3_LIBCALL "*.urem"
-
-/* Define this as 1 if `char' should by default be signed; else as 0. */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
- in one reasonably fast instruction. */
-#define MOVE_MAX 16
-
-/* Nonzero if access to memory by bytes is slow and undesirable. */
-#define SLOW_BYTE_ACCESS 0
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Value is 1 if it generates better code to perform an unsigned comparison
- on the given literal integer value in the given mode when we are only
- looking for an equal/non-equal result. */
-/* For the i860, if the immediate value has its high-order 27 bits zero,
- then we want to engineer an unsigned comparison for EQ/NE because
- such values can fit in the 5-bit immediate field of a bte or btne
- instruction (which gets zero extended before comparing). For all
- other immediate values on the i860, we will use signed compares
- because that avoids the need for doing explicit xor's to zero_extend
- the non-constant operand in cases where it was (mem:QI ...) or a
- (mem:HI ...) which always gets automatically sign-extended by the
- hardware upon loading. */
-
-#define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode) \
- (((unsigned) (intval) & 0x1f) == (unsigned) (intval))
-
-/* Specify the machine mode that pointers have.
- After generation of rtl, the compiler makes no further distinction
- between pointers and any other objects of this machine mode. */
-#define Pmode SImode
-
-/* A function address in a call instruction
- is a byte address (for indexing purposes)
- so give the MEM rtx a byte's mode. */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
- shouldn't be put through pseudo regs where they can be cse'd.
- Desirable on machines where ordinary constants are expensive
- but a CALL with constant address is cheap. */
-#define NO_FUNCTION_CSE
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-#define CONST_COSTS(RTX,CODE, OUTER_CODE) \
- case CONST_INT: \
- if (INTVAL (RTX) == 0) \
- return 0; \
- if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 4; \
- case CONST_DOUBLE: \
- return 6;
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
- should be added to avoid a branch.
-
- Set this to 3 on the i860 since branches may often take three cycles. */
-
-#define BRANCH_COST 3
-\f
-/* Tell final.c how to eliminate redundant test instructions. */
-
-/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). */
-
-/* This holds the value sourcing h%r31. We keep this info
- around so that mem/mem ops, such as increment and decrement,
- etc, can be performed reasonably. */
-#define CC_STATUS_MDEP rtx
-
-#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
-
-#define CC_NEGATED 01000
-
-/* We use this macro in those places in the i860.md file where we would
- normally just do a CC_STATUS_INIT (for other machines). This macro
- differs from CC_STATUS_INIT in that it doesn't mess with the special
- bits or fields which describe what is currently in the special r31
- scratch register, but it does clear out everything that actually
- relates to the condition code bit of the i860. */
-
-#define CC_STATUS_PARTIAL_INIT \
- (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ), \
- cc_status.value1 = 0, \
- cc_status.value2 = 0)
-
-/* Nonzero if we know the value of h%r31. */
-#define CC_KNOW_HI_R31 0100000
-
-/* Nonzero if h%r31 is actually ha%something, rather than h%something. */
-#define CC_HI_R31_ADJ 0200000
-
-/* Store in cc_status the expressions
- that the condition codes will describe
- after execution of an instruction whose pattern is EXP.
- Do not alter them if the instruction would not alter the cc's. */
-
-/* On the i860, only compare insns set a useful condition code. */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ); \
- cc_status.value1 = 0; cc_status.value2 = 0; }
-\f
-/* Control the assembler format that we output. */
-
-/* Assembler pseudos to introduce constants of various size. */
-
-#define ASM_DOUBLE "\t.double"
-
-/* Output at beginning of assembler file. */
-/* The .file command should always begin the output. */
-
-#define ASM_FILE_START(FILE)
-#if 0
-#define ASM_FILE_START(FILE) \
- do { output_file_directive ((FILE), main_input_filename); \
- if (optimize) ASM_FILE_START_1 (FILE); \
- } while (0)
-#endif
-
-#define ASM_FILE_START_1(FILE)
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#define ASM_APP_OFF ""
-
-/* Output before read-only data. */
-
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9", \
- "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
- "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
- "r30", "r31", \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
- "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
- "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
- "f30", "f31" }
-
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
- do { fputs (".globl ", FILE); \
- assemble_name (FILE, NAME); \
- fputs ("\n", FILE); \
- } while (0)
-
-/* The prefix to add to user-visible assembler symbols.
-
- This definition is overridden in i860v4.h because under System V
- Release 4, user-level symbols are *not* prefixed with underscores in
- the generated assembly code. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to output an internal numbered label which
- labels a jump table. */
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
-do { ASM_OUTPUT_ALIGN ((FILE), 2); \
- ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM); \
- } while (0)
-
-/* Output at the end of a jump table. */
-
-#define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \
- fprintf (FILE, ".text\n")
-
-/* This is how to store into the string LABEL
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, "*.%s%d", PREFIX, NUM)
-
-/* This is how to output code to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n", \
- i860_reg_prefix, i860_reg_prefix, \
- ((REGNO) < 32 ? "" : "f"), \
- i860_reg_prefix, reg_names[REGNO], \
- i860_reg_prefix)
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n", \
- ((REGNO) < 32 ? "" : "f"), \
- i860_reg_prefix, \
- i860_reg_prefix, reg_names[REGNO], \
- i860_reg_prefix, i860_reg_prefix)
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- fprintf (FILE, "\t.long .L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
- (The i860 does not use such vectors,
- but we must define this macro anyway.) */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG) != 0) \
- fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\t.blkb %u\n", (SIZE))
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
- CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
- For `%' followed by punctuation, CODE is the punctuation and X is null.
-
- In the following comments, the term "constant address" is used frequently.
- For an exact definition of what constitutes a "constant address" see the
- output_addr_const routine in final.c
-
- On the i860, the following target-specific special codes are recognized:
-
- `r' The operand can be anything, but if it is an immediate zero
- value (either integer or floating point) then it will be
- represented as `r0' or as `f0' (respectively).
-
- `m' The operand is a memory ref (to a constant address) but print
- its address as a constant.
-
- `L' The operand is a numeric constant, a constant address, or
- a memory ref to a constant address. Print the correct
- notation to yield the low part of the given value or
- address or the low part of the address of the referred
- to memory object.
-
- `H' The operand is a numeric constant, a constant address, or
- a memory ref to a constant address. Print the correct
- notation to yield the high part of the given value or
- address or the high part of the address of the referred
- to memory object.
-
- `h' The operand is a numeric constant, a constant address, or
- a memory ref to a constant address. Either print the
- correct notation to yield the plain high part of the
- given value or address (or the plain high part of the
- address of the memory object) or else print the correct
- notation to yield the "adjusted" high part of the given
- address (or of the address of the referred to memory object).
-
- The choice of what to print depends upon whether the address
- in question is relocatable or not. If it is relocatable,
- print the notation to get the adjusted high part. Otherwise
- just print the notation to get the plain high part. Note
- that "adjusted" high parts are generally used *only* when
- the next following instruction uses the low part of the
- address as an offset, as in `offset(reg)'.
-
- `R' The operand is a floating-pointer register. Print the
- name of the next following (32-bit) floating-point register.
- (This is used when moving a value into just the most
- significant part of a floating-point register pair.)
-
- `?' (takes no operand) Substitute the value of i860_reg_prefix
- at this point. The value of i860_reg_prefix is typically
- a null string for most i860 targets, but for System V
- Release 4 the i860 assembler syntax requires that all
- names of registers be prefixed with a percent-sign, so
- for SVR4, the value of i860_reg_prefix is initialized to
- "%" in i860.c.
-*/
-
-extern const char *i860_reg_prefix;
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?')
-
-/* The following macro definition is overridden in i860v4.h
- because the svr4 i860 assembler required a different syntax
- for getting parts of constant/relocatable values. */
-
-#define PRINT_OPERAND_PART(FILE, X, PART_CODE) \
- do { fprintf (FILE, "%s%%", PART_CODE); \
- output_address (X); \
- } while (0)
-
-#define OPERAND_LOW_PART "l"
-#define OPERAND_HIGH_PART "h"
-/* NOTE: All documentation available for the i860 sez that you must
- use "ha" to get the relocated high part of a relocatable, but
- reality sez different. */
-#define OPERAND_HIGH_ADJ_PART "ha"
-
-#define PRINT_OPERAND(FILE, X, CODE) \
-{ if ((CODE) == '?') \
- fprintf (FILE, "%s", i860_reg_prefix); \
- else if (CODE == 'R') \
- fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]); \
- else if (GET_CODE (X) == REG) \
- fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]); \
- else if ((CODE) == 'm') \
- output_address (XEXP (X, 0)); \
- else if ((CODE) == 'L') \
- { \
- if (GET_CODE (X) == MEM) \
- PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \
- else \
- PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \
- } \
- else if ((CODE) == 'H') \
- { \
- if (GET_CODE (X) == MEM) \
- PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \
- else \
- PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \
- } \
- else if ((CODE) == 'h') \
- { \
- if (GET_CODE (X) == MEM) \
- PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART); \
- else \
- PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART); \
- } \
- else if (GET_CODE (X) == MEM) \
- output_address (XEXP (X, 0)); \
- else if ((CODE) == 'r' && (X) == const0_rtx) \
- fprintf (FILE, "%sr0", i860_reg_prefix); \
- else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \
- fprintf (FILE, "%sf0", i860_reg_prefix); \
- else if (GET_CODE (X) == CONST_DOUBLE) \
- fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (X)); \
- else \
- output_addr_const (FILE, X); }
-\f
-/* Print a memory address as an operand to reference that memory location. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-{ register rtx addr = ADDR; \
- if (GET_CODE (addr) == REG) \
- { \
- fprintf (FILE, "0(%s%s)", \
- i860_reg_prefix, reg_names[REGNO (addr)]); \
- } \
- else if (GET_CODE (addr) == CONST_DOUBLE \
- && GET_MODE (addr) == SFmode) \
- fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (addr)); \
- else if (GET_CODE (addr) == PLUS) \
- { \
- if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \
- && (GET_CODE (XEXP (addr, 1)) == REG)) \
- fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)), \
- i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
- else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT) \
- && (GET_CODE (XEXP (addr, 0)) == REG)) \
- fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)), \
- i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\
- else if ((GET_CODE (XEXP (addr, 0)) == REG) \
- && (GET_CODE (XEXP (addr, 1)) == REG)) \
- fprintf (FILE, "%s%s(%s%s)", \
- i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))], \
- i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
- else \
- output_addr_const (FILE, addr); \
- } \
- else \
- { \
- output_addr_const (FILE, addr); \
- } \
-}
-
-/* Optionally define this if you have added predicates to
- `MACHINE.c'. This macro is called within an initializer of an
- array of structures. The first field in the structure is the
- name of a predicate and the second field is an array of rtl
- codes. For each predicate, list all rtl codes that can be in
- expressions matched by the predicate. The list should have a
- trailing comma. Here is an example of two entries in the list
- for a typical RISC machine:
-
- #define PREDICATE_CODES \
- {"gen_reg_rtx_operand", {SUBREG, REG}}, \
- {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
-
- Defining this macro does not affect the generated code (however,
- incorrect definitions that omit an rtl code that may be matched
- by the predicate can cause the compiler to malfunction).
- Instead, it allows the table built by `genrecog' to be more
- compact and efficient, thus speeding up the compiler. The most
- important predicates to include in the list specified by this
- macro are thoses used in the most insn patterns. */
-
-#define PREDICATE_CODES \
- {"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \
- {"arith_operand", {REG, SUBREG, CONST_INT}}, \
- {"logic_operand", {REG, SUBREG, CONST_INT}}, \
- {"shift_operand", {REG, SUBREG, CONST_INT}}, \
- {"compare_operand", {REG, SUBREG, CONST_INT}}, \
- {"arith_const_operand", {CONST_INT}}, \
- {"logic_const_operand", {CONST_INT}}, \
- {"bte_operand", {REG, SUBREG, CONST_INT}}, \
- {"indexed_operand", {MEM}}, \
- {"load_operand", {MEM}}, \
- {"small_int", {CONST_INT}}, \
- {"logic_int", {CONST_INT}}, \
- {"call_insn_operand", {MEM}},
-
-/* Define the information needed to generate branch insns. This is stored
- from the compare operation. Note that we can't use "rtx" here since it
- hasn't been defined! */
-
-extern struct rtx_def *i860_compare_op0, *i860_compare_op1;
+++ /dev/null
-;;- Machine description for Intel 860 chip for GNU C compiler
-;; Copyright (C) 1989, 1990, 1997, 1998, 1999, 2000
-;; Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;- Operand classes for the register allocator:
-\f
-/* Bit-test instructions. */
-
-(define_insn ""
- [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "logic_operand" "rL"))
- (const_int 0)))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"and %1,%0,%?r0\";
-}")
-
-(define_insn ""
- [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "logic_operand" "rL"))
- (const_int 0)))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"and %1,%0,%?r0\";
-}")
-
-(define_insn ""
- [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "immediate_operand" "i"))
- (const_int 0)))]
- "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0"
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"andh %H1,%0,%?r0\";
-}")
-
-(define_insn ""
- [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "immediate_operand" "i"))
- (const_int 0)))]
- "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0"
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"andh %H1,%0,%?r0\";
-}")
-
-(define_insn ""
- [(set (cc0) (eq (ashiftrt:SI
- (sign_extend:SI
- (ashift:QI (match_operand:QI 0 "register_operand" "r")
- (match_operand:QI 1 "logic_int" "n")))
- (match_operand:SI 2 "logic_int" "n"))
- (const_int 0)))]
- ""
- "*
-{
- int width = 8 - INTVAL (operands[2]);
- int pos = 8 - width - INTVAL (operands[1]);
-
- CC_STATUS_PARTIAL_INIT;
- operands[2] = GEN_INT (~((-1) << width) << pos);
- return \"and %2,%0,%?r0\";
-}")
-\f
-;; -------------------------------------------------------------------------
-;; SImode signed integer comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpeqsi"
- [(set (cc0) (eq (match_operand:SI 0 "logic_operand" "r,rL")
- (match_operand:SI 1 "logic_operand" "L,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[0]))
- return \"xor %1,%0,%?r0\";
- else
- return \"xor %0,%1,%?r0\";
-}")
-
-(define_insn "cmpnesi"
- [(set (cc0) (ne (match_operand:SI 0 "logic_operand" "r,rL")
- (match_operand:SI 1 "logic_operand" "L,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- if (REG_P (operands[0]))
- return \"xor %1,%0,%?r0\";
- else
- return \"xor %0,%1,%?r0\";
-}")
-
-(define_insn "cmpltsi"
- [(set (cc0) (lt (match_operand:SI 0 "arith_operand" "r,rI")
- (match_operand:SI 1 "arith_operand" "I,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[1]))
- return \"subs %0,%1,%?r0\";
- else
- {
- cc_status.flags |= CC_REVERSED;
- operands[1] = GEN_INT (- INTVAL (operands[1]));
- return \"adds %1,%0,%?r0\";
- }
-}")
-
-(define_insn "cmpgtsi"
- [(set (cc0) (gt (match_operand:SI 0 "arith_operand" "r,rI")
- (match_operand:SI 1 "arith_operand" "I,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[0]))
- return \"subs %1,%0,%?r0\";
- else
- {
- cc_status.flags |= CC_REVERSED;
- operands[0] = GEN_INT (- INTVAL (operands[0]));
- return \"adds %0,%1,%?r0\";
- }
-}")
-
-(define_insn "cmplesi"
- [(set (cc0) (le (match_operand:SI 0 "arith_operand" "r,rI")
- (match_operand:SI 1 "arith_operand" "I,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- if (REG_P (operands[0]))
- return \"subs %1,%0,%?r0\";
- else
- {
- cc_status.flags |= CC_REVERSED;
- operands[0] = GEN_INT (- INTVAL (operands[0]));
- return \"adds %0,%1,%?r0\";
- }
-}")
-
-(define_insn "cmpgesi"
- [(set (cc0) (ge (match_operand:SI 0 "arith_operand" "r,rI")
- (match_operand:SI 1 "arith_operand" "I,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- if (REG_P (operands[1]))
- return \"subs %0,%1,%?r0\";
- else
- {
- cc_status.flags |= CC_REVERSED;
- operands[1] = GEN_INT (- INTVAL (operands[1]));
- return \"adds %1,%0,%?r0\";
- }
-}")
-
-;; -------------------------------------------------------------------------
-;; SImode unsigned integer comparisons
-;; -------------------------------------------------------------------------
-
-;; WARNING! There is a small i860 hardware limitation (bug?) which we
-;; may run up against (if we are not careful) when we are trying to do
-;; unsigned comparisons like (x >= 0), (x < 0), (0 <= x), and (0 > x).
-;; Specifically, we must avoid using an `addu' instruction to perform
-;; such comparisons because the result (in the CC bit register) will
-;; come out wrong. (This fact is documented in a footnote on page 7-10
-;; of the 1991 version of the i860 Microprocessor Family Programmer's
-;; Reference Manual). Note that unsigned comparisons of this sort are
-;; always redundant anyway, because an unsigned quantity can never be
-;; less than zero. When we see cases like this, we generate an
-;; `or K,%r0,%r0' instruction instead (where K is a constant 0 or -1)
-;; so as to get the CC bit register set properly for any subsequent
-;; conditional jump instruction.
-
-(define_insn "cmpgeusi"
- [(set (cc0) (geu (match_operand:SI 0 "arith_operand" "r,rI")
- (match_operand:SI 1 "arith_operand" "I,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[1]))
- return \"subu %0,%1,%?r0\";
- else
- {
- if (INTVAL (operands[1]) == 0)
- return \"or 0,%?r0,%?r0\";
- else
- {
- cc_status.flags |= CC_REVERSED;
- operands[1] = GEN_INT (- INTVAL (operands[1]));
- return \"addu %1,%0,%?r0\";
- }
- }
-}")
-
-(define_insn "cmpleusi"
- [(set (cc0) (leu (match_operand:SI 0 "arith_operand" "r,rI")
- (match_operand:SI 1 "arith_operand" "I,r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[0]))
- return \"subu %1,%0,%?r0\";
- else
- {
- if (INTVAL (operands[0]) == 0)
- return \"or 0,%?r0,%?r0\";
- else
- {
- cc_status.flags |= CC_REVERSED;
- operands[0] = GEN_INT (- INTVAL (operands[0]));
- return \"addu %0,%1,%?r0\";
- }
- }
-}")
-
-;; -------------------------------------------------------------------------
-;; SFmode floating-point comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpeqsf"
- [(set (cc0) (eq (match_operand:SF 0 "reg_or_0_operand" "fG")
- (match_operand:SF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"pfeq.ss %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpnesf"
- [(set (cc0) (ne (match_operand:SF 0 "reg_or_0_operand" "fG")
- (match_operand:SF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"pfeq.ss %r1,%r0,%?f0\";
-}")
-
-;; NOTE: The i860 Programmer's Reference Manual says that when we are
-;; doing (A < B) or (A > B) comparisons, we have to use pfgt for these
-;; in order to be IEEE compliant (in case a trap occurs during these
-;; operations). Conversely, for (A <= B) or (A >= B) comparisons, we
-;; must use pfle to be IEEE compliant.
-
-(define_insn "cmpltsf"
- [(set (cc0) (lt (match_operand:SF 0 "reg_or_0_operand" "fG")
- (match_operand:SF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"pfgt.ss %r1,%r0,%?f0\";
-}")
-
-(define_insn "cmpgtsf"
- [(set (cc0) (gt (match_operand:SF 0 "reg_or_0_operand" "fG")
- (match_operand:SF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"pfgt.ss %r0,%r1,%?f0\";
-}")
-
-;; NOTE: The pfle opcode doesn't do what you think it does. It is
-;; bass-ackwards. It *clears* the CC flag if the first operand is
-;; less than or equal to the second. Thus, we have to set CC_NEGATED
-;; for the following two patterns.
-
-(define_insn "cmplesf"
- [(set (cc0) (le (match_operand:SF 0 "reg_or_0_operand" "fG")
- (match_operand:SF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"pfle.ss %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpgesf"
- [(set (cc0) (ge (match_operand:SF 0 "reg_or_0_operand" "fG")
- (match_operand:SF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"pfle.ss %r1,%r0,%?f0\";
-}")
-
-;; -------------------------------------------------------------------------
-;; DFmode floating-point comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpeqdf"
- [(set (cc0) (eq (match_operand:DF 0 "reg_or_0_operand" "fG")
- (match_operand:DF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"pfeq.dd %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpnedf"
- [(set (cc0) (ne (match_operand:DF 0 "reg_or_0_operand" "fG")
- (match_operand:DF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"pfeq.dd %r1,%r0,%?f0\";
-}")
-
-;; NOTE: The i860 Programmer's Reference Manual says that when we are
-;; doing (A < B) or (A > B) comparisons, we have to use pfgt for these
-;; in order to be IEEE compliant (in case a trap occurs during these
-;; operations). Conversely, for (A <= B) or (A >= B) comparisons, we
-;; must use pfle to be IEEE compliant.
-
-(define_insn "cmpltdf"
- [(set (cc0) (lt (match_operand:DF 0 "reg_or_0_operand" "fG")
- (match_operand:DF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"pfgt.dd %r1,%r0,%?f0\";
-}")
-
-(define_insn "cmpgtdf"
- [(set (cc0) (gt (match_operand:DF 0 "reg_or_0_operand" "fG")
- (match_operand:DF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"pfgt.dd %r0,%r1,%?f0\";
-}")
-
-;; NOTE: The pfle opcode doesn't do what you think it does. It is
-;; bass-ackwards. It *clears* the CC flag if the first operand is
-;; less than or equal to the second. Thus, we have to set CC_NEGATED
-;; for the following two patterns.
-
-(define_insn "cmpledf"
- [(set (cc0) (le (match_operand:DF 0 "reg_or_0_operand" "fG")
- (match_operand:DF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"pfle.dd %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpgedf"
- [(set (cc0) (ge (match_operand:DF 0 "reg_or_0_operand" "fG")
- (match_operand:DF 1 "reg_or_0_operand" "fG")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- cc_status.flags |= CC_NEGATED;
- return \"pfle.dd %r1,%r0,%?f0\";
-}")
-
-;; ------------------------------------------------------------------------
-;; Integer EQ/NE comparisons against constant values which will fit in the
-;; 16-bit immediate field of an instruction. These are made by combining.
-;; ------------------------------------------------------------------------
-
-(define_insn ""
- [(set (cc0) (eq (zero_extend:SI (match_operand:HI 0 "load_operand" "m"))
- (match_operand:SI 1 "small_int" "I")))]
- "INTVAL (operands[1]) >= 0"
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"ld.s %0,%?r31\;xor %1,%?r31,%?r0\";
-}")
-
-(define_insn ""
- [(set (cc0) (eq (match_operand:SI 0 "small_int" "I")
- (zero_extend:SI (match_operand:HI 1 "load_operand" "m"))))]
- "INTVAL (operands[0]) >= 0"
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"ld.s %1,%?r31\;xor %0,%?r31,%?r0\";
-}")
-\f
-;; ------------------------------------------------------------------------
-;; Define the real conditional branch instructions.
-;; ------------------------------------------------------------------------
-
-(define_insn "cbranch"
- [(set (pc) (if_then_else (eq (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "*
-{
- if ((cc_prev_status.flags & CC_NEGATED) == 0)
- return \"bnc %l0\";
- else
- return \"bc %l0\";
-}")
-
-(define_insn "flipped_cbranch"
- [(set (pc) (if_then_else (ne (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "*
-{
- if ((cc_prev_status.flags & CC_NEGATED) == 0)
- return \"bnc %l0\";
- else
- return \"bc %l0\";
-}")
-
-(define_insn "inverse_cbranch"
- [(set (pc) (if_then_else (eq (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "*
-{
- if ((cc_prev_status.flags & CC_NEGATED) == 0)
- return \"bc %l0\";
- else
- return \"bnc %l0\";
-}")
-
-
-(define_insn "flipped_inverse_cbranch"
- [(set (pc) (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "*
-{
- if ((cc_prev_status.flags & CC_NEGATED) == 0)
- return \"bc %l0\";
- else
- return \"bnc %l0\";
-}")
-
-;; Simple BTE/BTNE compare-and-branch insns made by combining.
-;; Note that it is wrong to add similar patterns for QI or HImode
-;; because bte/btne always compare the whole register.
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "bte_operand" "rK"))
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "bte %1,%0,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "bte_operand" "rK"))
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "btne %1,%0,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "bte_operand" "rK"))
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "btne %1,%0,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "bte_operand" "rK"))
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "bte %1,%0,%2")
-
-;; Load byte/halfword, zero-extend, & compare-and-branch insns.
-;; These are made by combining.
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.b %0,%3;bte %1,%3,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.b %0,%3;btne %1,%3,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (pc)
- (label_ref (match_operand 2 "" ""))))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.b %0,%3;btne %1,%3,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (pc)
- (label_ref (match_operand 2 "" ""))))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.b %0,%3;bte %1,%3,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.s %0,%3;bte %1,%3,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.s %0,%3;btne %1,%3,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (pc)
- (label_ref (match_operand 2 "" ""))))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.s %0,%3;btne %1,%3,%2")
-
-(define_insn ""
- [(set (pc)
- (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
- (match_operand:SI 1 "bte_operand" "K"))
- (pc)
- (label_ref (match_operand 2 "" ""))))
- (match_scratch:SI 3 "=r")]
- ""
- "ld.s %0,%3;bte %1,%3,%2")
-
-\f
-;; Generation of conditionals.
-
-;; We save the compare operands in the cmpxx patterns and use then when
-;; we generate the branch.
-
-(define_expand "cmpsi"
- [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "compare_operand" "")))]
- ""
- "
-{ i860_compare_op0 = operands[0];
- i860_compare_op1 = operands[1];
- DONE;
-}")
-
-(define_expand "cmpsf"
- [(set (cc0) (compare (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "register_operand" "")))]
- ""
- "
-{ i860_compare_op0 = operands[0];
- i860_compare_op1 = operands[1];
- DONE;
-}")
-
-(define_expand "cmpdf"
- [(set (cc0) (compare (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" "")))]
- ""
- "
-{ i860_compare_op0 = operands[0];
- i860_compare_op1 = operands[1];
- DONE;
-}")
-
-;; These are the standard-named conditional branch patterns.
-;; Detailed comments are found in the first one only.
-
-(define_expand "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- /* Emit a single-condition compare insn according to
- the type of operands and the condition to be tested. */
-
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
- emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == SFmode)
- emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == DFmode)
- emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1));
- else
- abort ();
-
- /* Emit branch-if-true. */
-
- emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
- DONE;
-}")
-
-(define_expand "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
- emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == SFmode)
- emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == DFmode)
- emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1));
- else
- abort ();
-
- emit_jump_insn (gen_flipped_cbranch (operands[0]));
-
- DONE;
-}")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
- emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == SFmode)
- emit_insn (gen_cmpgtsf (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == DFmode)
- emit_insn (gen_cmpgtdf (i860_compare_op0, i860_compare_op1));
- else
- abort ();
-
- emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
- DONE;
-}")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
- emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == SFmode)
- emit_insn (gen_cmpltsf (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == DFmode)
- emit_insn (gen_cmpltdf (i860_compare_op0, i860_compare_op1));
- else
- abort ();
-
- emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
- DONE;
-}")
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
- {
- emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1));
- emit_jump_insn (gen_flipped_cbranch (operands[0]));
- }
- else
- {
- if (GET_MODE (i860_compare_op0) == SFmode)
- emit_insn (gen_cmplesf (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == DFmode)
- emit_insn (gen_cmpledf (i860_compare_op0, i860_compare_op1));
- else
- abort ();
- emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
- }
- DONE;
-}")
-
-(define_expand "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
- {
- emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1));
- emit_jump_insn (gen_flipped_cbranch (operands[0]));
- }
- else
- {
- if (GET_MODE (i860_compare_op0) == SFmode)
- emit_insn (gen_cmpgesf (i860_compare_op0, i860_compare_op1));
- else if (GET_MODE (i860_compare_op0) == DFmode)
- emit_insn (gen_cmpgedf (i860_compare_op0, i860_compare_op1));
- else
- abort ();
- emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
- }
- DONE;
-}")
-
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
- abort ();
-
- emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1));
- emit_jump_insn (gen_flipped_cbranch (operands[0]));
- DONE;
-}")
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
- abort ();
-
- emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1));
- emit_jump_insn (gen_flipped_cbranch (operands[0]));
- DONE;
-}")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
- abort ();
-
- emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1));
- emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
- DONE;
-}")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
- abort ();
-
- emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1));
- emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
- DONE;
-}")
-\f
-;; Move instructions
-
-;; Note that source operands for `mov' pseudo-instructions are no longer
-;; allowed (by the svr4 assembler) to be "big" things, i.e. constants that
-;; won't fit in 16-bits. (This includes any sort of a relocatable address
-;; also.) Thus, we must use an explicit orh/or pair of instructions if
-;; the source operand is something "big".
-
-(define_insn "movsi"
- [(set (match_operand:SI 0 "general_operand" "=r,m,f")
- (match_operand:SI 1 "general_operand" "rmif,rfJ,rmfJ"))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- return output_store (operands);
- if (FP_REG_P (operands[1]))
- return \"fst.l %1,%0\";
- return \"st.l %r1,%0\";
- }
- if (GET_CODE (operands[1]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- return output_load (operands);
- if (FP_REG_P (operands[0]))
- return \"fld.l %1,%0\";
- return \"ld.l %1,%0\";
- }
- if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
- return \"fmov.ss %1,%0\";
- if (FP_REG_P (operands[1]))
- return \"fxfr %1,%0\";
- if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
- return \"fmov.ss %?f0,%0\";
- if (FP_REG_P (operands[0]))
- return \"ixfr %1,%0\";
-
- if (GET_CODE (operands[1]) == REG)
- return \"shl %?r0,%1,%0\";
-
- CC_STATUS_PARTIAL_INIT;
-
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- if((INTVAL (operands[1]) & 0xffff0000) == 0)
- return \"or %L1,%?r0,%0\";
- if((INTVAL (operands[1]) & 0x0000ffff) == 0)
- return \"orh %H1,%?r0,%0\";
- }
- return \"orh %H1,%?r0,%0\;or %L1,%0,%0\";
-}")
-
-(define_insn "movhi"
- [(set (match_operand:HI 0 "general_operand" "=r,m,!*f,!r")
- (match_operand:HI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- return output_store (operands);
- return \"st.s %r1,%0\";
- }
- if (GET_CODE (operands[1]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- return output_load (operands);
- return \"ld.s %1,%0\";
- }
- if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
- return \"fmov.ss %1,%0\";
- if (FP_REG_P (operands[1]))
- return \"fxfr %1,%0\";
- if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
- return \"fmov.ss %?f0,%0\";
- if (FP_REG_P (operands[0]))
- return \"ixfr %1,%0\";
-
- if (GET_CODE (operands[1]) == REG)
- return \"shl %?r0,%1,%0\";
-
- CC_STATUS_PARTIAL_INIT;
-
- return \"or %L1,%?r0,%0\";
-}")
-
-(define_insn "movqi"
- [(set (match_operand:QI 0 "general_operand" "=r,m,!*f,!r")
- (match_operand:QI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- return output_store (operands);
- return \"st.b %r1,%0\";
- }
- if (GET_CODE (operands[1]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- return output_load (operands);
- return \"ld.b %1,%0\";
- }
- if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
- return \"fmov.ss %1,%0\";
- if (FP_REG_P (operands[1]))
- return \"fxfr %1,%0\";
- if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
- return \"fmov.ss %?f0,%0\";
- if (FP_REG_P (operands[0]))
- return \"ixfr %1,%0\";
-
- if (GET_CODE (operands[1]) == REG)
- return \"shl %?r0,%1,%0\";
-
- CC_STATUS_PARTIAL_INIT;
-
- return \"or %L1,%?r0,%0\";
-}")
-
-;; The definition of this insn does not really explain what it does,
-;; but it should suffice
-;; that anything generated as this insn will be recognized as one
-;; and that it won't successfully combine with anything.
-(define_expand "movstrsi"
- [(parallel [(set (match_operand:BLK 0 "general_operand" "")
- (match_operand:BLK 1 "general_operand" ""))
- (use (match_operand:SI 2 "nonmemory_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))
- (clobber (match_dup 7))
- (clobber (match_dup 8))])]
- ""
- "
-{
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = gen_reg_rtx (SImode);
- operands[6] = gen_reg_rtx (SImode);
- operands[7] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
- operands[8] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
-
- operands[0] = replace_equiv_address (operands[0], operands[7]);
- operands[1] = replace_equiv_address (operands[1], operands[8]);
-}")
-
-(define_insn ""
- [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
- (mem:BLK (match_operand:SI 1 "register_operand" "r")))
- (use (match_operand:SI 2 "general_operand" "rn"))
- (use (match_operand:SI 3 "immediate_operand" "i"))
- (clobber (match_operand:SI 4 "register_operand" "=r"))
- (clobber (match_operand:SI 5 "register_operand" "=r"))
- (clobber (match_operand:SI 6 "register_operand" "=r"))
- (clobber (match_dup 0))
- (clobber (match_dup 1))]
- ""
- "* return output_block_move (operands);")
-\f
-;; Floating point move insns
-
-;; This pattern forces (set (reg:DF ...) (const_double ...))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general movdf pattern.
-(define_insn ""
- [(set (match_operand:DF 0 "general_operand" "=r,f,o")
- (match_operand:DF 1 "" "mG,m,G"))]
- "GET_CODE (operands[1]) == CONST_DOUBLE"
- "*
-{
- if (FP_REG_P (operands[0]) || operands[1] == CONST0_RTX (DFmode))
- return output_fp_move_double (operands);
- return output_move_double (operands);
-}")
-
-(define_insn "movdf"
- [(set (match_operand:DF 0 "general_operand" "=*rm,*r,?f,?*rm")
- (match_operand:DF 1 "general_operand" "*r,m,*rfmG,f"))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM
- && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- return output_store (operands);
- if (GET_CODE (operands[1]) == MEM
- && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- return output_load (operands);
-
- if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
- return output_fp_move_double (operands);
- return output_move_double (operands);
-}")
-
-(define_insn "movdi"
- [(set (match_operand:DI 0 "general_operand" "=rm,r,?f,?rm")
- (match_operand:DI 1 "general_operand" "r,miF,rfmG,f"))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM
- && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- return output_store (operands);
- if (GET_CODE (operands[1]) == MEM
- && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- return output_load (operands);
-
- /* ??? How can we have a DFmode arg here with DImode above? */
- if (FP_REG_P (operands[0]) && operands[1] == CONST0_RTX (DFmode))
- return \"fmov.dd %?f0,%0\";
-
- if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
- return output_fp_move_double (operands);
- return output_move_double (operands);
-}")
-
-;; The alternative m/r is separate from m/f
-;; The first alternative is separate from the second for the same reason.
-(define_insn "movsf"
- [(set (match_operand:SF 0 "general_operand" "=*rf,*rf,*r,m,m")
- (match_operand:SF 1 "general_operand" "*r,fmG,F,*r,f"))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM
- && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- return output_store (operands);
- if (GET_CODE (operands[1]) == MEM
- && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- return output_load (operands);
- if (FP_REG_P (operands[0]))
- {
- if (FP_REG_P (operands[1]))
- return \"fmov.ss %1,%0\";
- if (GET_CODE (operands[1]) == REG)
- return \"ixfr %1,%0\";
- if (operands[1] == CONST0_RTX (SFmode))
- return \"fmov.ss %?f0,%0\";
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && cc_prev_status.mdep == XEXP(operands[1],0)))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[1], 0);
- return \"orh %h1,%?r0,%?r31\;fld.l %L1(%?r31),%0\";
- }
- return \"fld.l %L1(%?r31),%0\";
- }
- return \"fld.l %1,%0\";
- }
- if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- if (GET_CODE (operands[0]) == REG && FP_REG_P (operands[1]))
- return \"fxfr %1,%0\";
- if (GET_CODE (operands[0]) == REG)
- {
- CC_STATUS_PARTIAL_INIT;
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- register unsigned long ul;
-
- ul = sfmode_constant_to_ulong (operands[1]);
- if ((ul & 0x0000ffff) == 0)
- return \"orh %H1,%?r0,%0\";
- if ((ul & 0xffff0000) == 0)
- return \"or %L1,%?r0,%0\";
- }
- return \"orh %H1,%?r0,%0\;or %L1,%0,%0\";
- }
- /* Now operand 0 must be memory.
- If operand 1 is CONST_DOUBLE, its value must be 0. */
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && XEXP (operands[0], 0) == cc_prev_status.mdep))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[0], 0);
- output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
- }
- return \"fst.l %r1,%L0(%?r31)\";
- }
- return \"fst.l %r1,%0\";
- }
- if (GET_CODE (operands[0]) == MEM)
- return \"st.l %r1,%0\";
- if (GET_CODE (operands[1]) == MEM)
- return \"ld.l %1,%0\";
- if (operands[1] == CONST0_RTX (SFmode))
- return \"shl %?r0,%?r0,%0\";
- return \"mov %1,%0\";
-}")
-\f
-;; Special load insns for REG+REG addresses.
-;; Such addresses are not "legitimate" because st rejects them.
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=rf")
- (match_operand:DF 1 "indexed_operand" "m"))]
- ""
- "*
-{
- if (FP_REG_P (operands[0]))
- return output_fp_move_double (operands);
- return output_move_double (operands);
-}")
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=rf")
- (match_operand:SF 1 "indexed_operand" "m"))]
- ""
- "*
-{
- if (FP_REG_P (operands[0]))
- return \"fld.l %1,%0\";
- return \"ld.l %1,%0\";
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=rf")
- (match_operand:SI 1 "indexed_operand" "m"))]
- ""
- "*
-{
- if (FP_REG_P (operands[0]))
- return \"fld.l %1,%0\";
- return \"ld.l %1,%0\";
-}")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (match_operand:HI 1 "indexed_operand" "m"))]
- ""
- "ld.s %1,%0")
-
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=r")
- (match_operand:QI 1 "indexed_operand" "m"))]
- ""
- "ld.b %1,%0")
-
-;; Likewise for floating-point store insns.
-
-(define_insn ""
- [(set (match_operand:DF 0 "indexed_operand" "=m")
- (match_operand:DF 1 "register_operand" "f"))]
- ""
- "fst.d %1,%0")
-
-(define_insn ""
- [(set (match_operand:SF 0 "indexed_operand" "=m")
- (match_operand:SF 1 "register_operand" "f"))]
- ""
- "fst.l %1,%0")
-\f
-;;- truncation instructions
-(define_insn "truncsiqi2"
- [(set (match_operand:QI 0 "general_operand" "=g")
- (truncate:QI
- (match_operand:SI 1 "register_operand" "r")))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && XEXP (operands[0], 0) == cc_prev_status.mdep))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[0], 0);
- output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
- }
- return \"st.b %1,%L0(%?r31)\";
- }
- else
- return \"st.b %1,%0\";
- }
- return \"shl %?r0,%1,%0\";
-}")
-
-(define_insn "trunchiqi2"
- [(set (match_operand:QI 0 "general_operand" "=g")
- (truncate:QI
- (match_operand:HI 1 "register_operand" "r")))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && XEXP (operands[0], 0) == cc_prev_status.mdep))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[0], 0);
- output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
- }
- return \"st.b %1,%L0(%?r31)\";
- }
- else
- return \"st.b %1,%0\";
- }
- return \"shl %?r0,%1,%0\";
-}")
-
-(define_insn "truncsihi2"
- [(set (match_operand:HI 0 "general_operand" "=g")
- (truncate:HI
- (match_operand:SI 1 "register_operand" "r")))]
- ""
- "*
-{
- if (GET_CODE (operands[0]) == MEM)
- {
- if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
- {
- if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
- && (cc_prev_status.flags & CC_HI_R31_ADJ)
- && XEXP (operands[0], 0) == cc_prev_status.mdep))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[0], 0);
- output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
- }
- return \"st.s %1,%L0(%?r31)\";
- }
- else
- return \"st.s %1,%0\";
- }
- return \"shl %?r0,%1,%0\";
-}")
-\f
-;;- zero extension instructions
-
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI
- (match_operand:HI 1 "register_operand" "r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"and 0xffff,%1,%0\";
-}")
-
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (zero_extend:HI
- (match_operand:QI 1 "register_operand" "r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"and 0xff,%1,%0\";
-}")
-
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI
- (match_operand:QI 1 "register_operand" "r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"and 0xff,%1,%0\";
-}")
-\f
-;; Sign extension instructions.
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI
- (match_operand:HI 1 "indexed_operand" "m")))]
- ""
- "ld.s %1,%0")
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (sign_extend:HI
- (match_operand:QI 1 "indexed_operand" "m")))]
- ""
- "ld.b %1,%0")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI
- (match_operand:QI 1 "indexed_operand" "m")))]
- ""
- "ld.b %1,%0")
-
-(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI
- (match_operand:HI 1 "nonimmediate_operand" "mr")))]
- ""
- "*
-{
- if (REG_P (operands[1]))
- return \"shl 16,%1,%0\;shra 16,%0,%0\";
- if (GET_CODE (operands[1]) == CONST_INT)
- abort ();
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[1], 0);
- return \"orh %h1,%?r0,%?r31\;ld.s %L1(%?r31),%0\";
- }
- else
- return \"ld.s %1,%0\";
-}")
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (sign_extend:HI
- (match_operand:QI 1 "nonimmediate_operand" "mr")))]
- ""
- "*
-{
- if (REG_P (operands[1]))
- return \"shl 24,%1,%0\;shra 24,%0,%0\";
- if (GET_CODE (operands[1]) == CONST_INT)
- abort ();
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[1], 0);
- return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
- }
- else
- return \"ld.b %1,%0\";
-}")
-
-(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI
- (match_operand:QI 1 "nonimmediate_operand" "mr")))]
- ""
- "*
-{
- if (REG_P (operands[1]))
- return \"shl 24,%1,%0\;shra 24,%0,%0\";
- if (GET_CODE (operands[1]) == CONST_INT)
- abort ();
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[1], 0);
- return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
- }
- else
- return \"ld.b %1,%0\";
-}")
-
-;; Signed bitfield extractions come out looking like
-;; (shiftrt (sign_extend (shift <Y> <C1>)) <C2>)
-;; which we expand poorly as four shift insns.
-;; These patterns yield two shifts:
-;; (shiftrt (shift <Y> <C3>) <C4>)
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashiftrt:SI
- (sign_extend:SI
- (match_operand:QI 1 "register_operand" "r"))
- (match_operand:SI 2 "logic_int" "n")))]
- "INTVAL (operands[2]) < 8"
- "*
-{
- return \"shl 24,%1,%0\;shra 24+%2,%0,%0\";
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashiftrt:SI
- (sign_extend:SI
- (subreg:QI (ashift:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "logic_int" "n")) 0))
- (match_operand:SI 3 "logic_int" "n")))]
- "INTVAL (operands[3]) < 8"
- "*
-{
- return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashiftrt:SI
- (sign_extend:SI
- (ashift:QI (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "logic_int" "n")))
- (match_operand:SI 3 "logic_int" "n")))]
- "INTVAL (operands[3]) < 8"
- "*
-{
- return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
-}")
-\f
-;; Special patterns for optimizing bit-field instructions.
-
-;; First two patterns are for bitfields that came from memory
-;; testing only the high bit. They work with old combiner.
-
-(define_insn ""
- [(set (cc0)
- (eq (zero_extend:SI (subreg:QI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")
- (const_int 7)) 0))
- (const_int 0)))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"and 128,%0,%?r0\";
-}")
-
-(define_insn ""
- [(set (cc0)
- (eq (sign_extend:SI (subreg:QI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")
- (const_int 7)) 0))
- (const_int 0)))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"and 128,%0,%?r0\";
-}")
-
-;; next two patterns are good for bitfields coming from memory
-;; (via pseudo-register) or from a register, though this optimization
-;; is only good for values contained wholly within the bottom 13 bits
-(define_insn ""
- [(set (cc0)
- (eq
- (and:SI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "logic_int" "n"))
- (match_operand:SI 2 "logic_int" "n"))
- (const_int 0)))]
- "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- operands[2] = GEN_INT (INTVAL (operands[2]) << INTVAL (operands[1]));
- return \"and %2,%0,%?r0\";
-}")
-
-(define_insn ""
- [(set (cc0)
- (eq
- (and:SI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "logic_int" "n"))
- (match_operand:SI 2 "logic_int" "n"))
- (const_int 0)))]
- "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- operands[2] = GEN_INT (INTVAL (operands[2]) << INTVAL (operands[1]));
- return \"and %2,%0,%?r0\";
-}")
-\f
-;; Conversions between float and double.
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float_extend:DF
- (match_operand:SF 1 "register_operand" "f")))]
- ""
- "fmov.sd %1,%0")
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF
- (match_operand:DF 1 "register_operand" "f")))]
- ""
- "fmov.ds %1,%0")
-\f
-;; Conversion between fixed point and floating point.
-;; Note that among the fix-to-float insns
-;; the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general floatsisf2 pattern.
-(define_expand "floatsidf2"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "")
- (const_int -2147483648)))
- (set (match_dup 5) (match_dup 3))
- (set (subreg:SI (match_dup 5) 0) (match_dup 4))
- (set (match_operand:DF 0 "register_operand" "")
- (minus:DF (match_dup 5) (match_dup 2)))]
- ""
- "
-{
- REAL_VALUE_TYPE d;
- /* 4503601774854144 is (1 << 30) * ((1 << 22) + (1 << 1)). */
- d = REAL_VALUE_ATOF (\"4503601774854144\", DFmode);
- operands[2] = gen_reg_rtx (DFmode);
- operands[3] = CONST_DOUBLE_FROM_REAL_VALUE (d, DFmode);
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = gen_reg_rtx (DFmode);
-}")
-\f
-;; Floating to fixed conversion.
-
-(define_expand "fix_truncdfsi2"
- ;; This first insn produces a double-word value
- ;; in which only the low word is valid.
- [(set (match_dup 2)
- (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
- (set (match_operand:SI 0 "register_operand" "=f")
- (subreg:SI (match_dup 2) 0))]
- ""
- "
-{
- operands[2] = gen_reg_rtx (DImode);
-}")
-
-;; Recognize the first insn generated above.
-;; This RTL looks like a fix_truncdfdi2 insn,
-;; but we don't call it that, because only 32 bits
-;; of the result are valid.
-;; This pattern will work for the intended purposes
-;; as long as we do not have any fixdfdi2 or fix_truncdfdi2.
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=f")
- (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
- ""
- "ftrunc.dd %1,%0")
-
-(define_expand "fix_truncsfsi2"
- ;; This first insn produces a double-word value
- ;; in which only the low word is valid.
- [(set (match_dup 2)
- (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
- (set (match_operand:SI 0 "register_operand" "=f")
- (subreg:SI (match_dup 2) 0))]
- ""
- "
-{
- operands[2] = gen_reg_rtx (DImode);
-}")
-
-;; Recognize the first insn generated above.
-;; This RTL looks like a fix_truncsfdi2 insn,
-;; but we don't call it that, because only 32 bits
-;; of the result are valid.
-;; This pattern will work for the intended purposes
-;; as long as we do not have any fixsfdi2 or fix_truncsfdi2.
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=f")
- (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
- ""
- "ftrunc.sd %1,%0")
-\f
-;;- arithmetic instructions
-
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,*f")
- (plus:SI (match_operand:SI 1 "nonmemory_operand" "%r,*f")
- (match_operand:SI 2 "arith_operand" "rI,*f")))]
- ""
- "*
-{
- if (which_alternative == 1)
- return \"fiadd.ss %2,%1,%0\";
- CC_STATUS_PARTIAL_INIT;
- return \"addu %2,%1,%0\";
-}")
-
-(define_insn "adddi3"
- [(set (match_operand:DI 0 "register_operand" "=f")
- (plus:DI (match_operand:DI 1 "register_operand" "%f")
- (match_operand:DI 2 "register_operand" "f")))]
- ""
- "fiadd.dd %1,%2,%0")
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,*f")
- (minus:SI (match_operand:SI 1 "register_operand" "r,I,*f")
- (match_operand:SI 2 "arith_operand" "rI,r,*f")))]
- ""
- "*
-{
- if (which_alternative == 2)
- return \"fisub.ss %1,%2,%0\";
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[2]))
- return \"subu %1,%2,%0\";
- operands[2] = GEN_INT (- INTVAL (operands[2]));
- return \"addu %2,%1,%0\";
-}")
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "register_operand" "=f")
- (minus:DI (match_operand:DI 1 "register_operand" "f")
- (match_operand:DI 2 "register_operand" "f")))]
- ""
- "fisub.dd %1,%2,%0")
-
-(define_expand "mulsi3"
- [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
- (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
- (clobber (match_dup 3))
- (set (subreg:SI (match_dup 3) 0)
- (mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
- (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
- ""
- "
-{
- if (WORDS_BIG_ENDIAN)
- emit_insn (gen_mulsi3_big (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_mulsi3_little (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_expand "mulsi3_little"
- [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
- (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
- (clobber (match_dup 3))
- (set (subreg:SI (match_dup 3) 0)
- (mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
- (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
- "! WORDS_BIG_ENDIAN"
- "
-{
- operands[3] = gen_reg_rtx (DImode);
- operands[4] = gen_reg_rtx (DImode);
- operands[5] = gen_reg_rtx (DImode);
-}")
-
-(define_expand "mulsi3_big"
- [(set (subreg:SI (match_dup 4) 4) (match_operand:SI 1 "general_operand" ""))
- (set (subreg:SI (match_dup 5) 4) (match_operand:SI 2 "general_operand" ""))
- (clobber (match_dup 3))
- (set (subreg:SI (match_dup 3) 4)
- (mult:SI (subreg:SI (match_dup 4) 4) (subreg:SI (match_dup 5) 4)))
- (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 4))]
- "WORDS_BIG_ENDIAN"
- "
-{
- operands[3] = gen_reg_rtx (DImode);
- operands[4] = gen_reg_rtx (DImode);
- operands[5] = gen_reg_rtx (DImode);
-}")
-
-(define_insn ""
- [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 0)
- (mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 0)
- (subreg:SI (match_operand:DI 2 "register_operand" "f") 0)))]
- "! WORDS_BIG_ENDIAN"
- "fmlow.dd %2,%1,%0")
-
-(define_insn ""
- [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 4)
- (mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 4)
- (subreg:SI (match_operand:DI 2 "register_operand" "f") 4)))]
- "WORDS_BIG_ENDIAN"
- "fmlow.dd %2,%1,%0")
-\f
-;;- and instructions (with compliment also)
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (and:SI (match_operand:SI 1 "nonmemory_operand" "%r")
- (match_operand:SI 2 "nonmemory_operand" "rL")))]
- ""
- "*
-{
- rtx xop[3];
-
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
- return \"and %2,%1,%0\";
- if ((INTVAL (operands[2]) & 0xffff) == 0)
- {
- operands[2]
- = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) >> 16);
- return \"andh %2,%1,%0\";
- }
- xop[0] = operands[0];
- xop[1] = operands[1];
- xop[2] = GEN_INT (~INTVAL (operands[2]) & 0xffff);
- output_asm_insn (\"andnot %2,%1,%0\", xop);
- operands[2] = GEN_INT (~(unsigned HOST_WIDE_INT) INTVAL (operands[2]) >> 16);
- return \"andnoth %2,%0,%0\";
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (and:SI (not:SI (match_operand:SI 1 "register_operand" "rn"))
- (match_operand:SI 2 "register_operand" "r")))]
- ""
- "*
-{
- rtx xop[3];
-
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[1]) || LOGIC_INT (operands[1]))
- return \"andnot %1,%2,%0\";
- if ((INTVAL (operands[1]) & 0xffff) == 0)
- {
- operands[1]
- = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (operands[1]) >> 16);
- return \"andnoth %1,%2,%0\";
- }
- xop[0] = operands[0];
- xop[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
- xop[2] = operands[2];
- output_asm_insn (\"andnot %1,%2,%0\", xop);
- operands[1] = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (operands[1]) >> 16);
- return \"andnoth %1,%0,%0\";
-}")
-
-(define_insn "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ior:SI (match_operand:SI 1 "nonmemory_operand" "%r")
- (match_operand:SI 2 "nonmemory_operand" "rL")))]
- ""
- "*
-{
- rtx xop[3];
-
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
- return \"or %2,%1,%0\";
- if ((INTVAL (operands[2]) & 0xffff) == 0)
- {
- operands[2]
- = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) >> 16);
- return \"orh %2,%1,%0\";
- }
- xop[0] = operands[0];
- xop[1] = operands[1];
- xop[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
- output_asm_insn (\"or %2,%1,%0\", xop);
- operands[2] = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) >> 16);
- return \"orh %2,%0,%0\";
-}")
-
-(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (xor:SI (match_operand:SI 1 "nonmemory_operand" "%r")
- (match_operand:SI 2 "nonmemory_operand" "rL")))]
- ""
- "*
-{
- rtx xop[3];
-
- CC_STATUS_PARTIAL_INIT;
- if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
- return \"xor %2,%1,%0\";
- if ((INTVAL (operands[2]) & 0xffff) == 0)
- {
- operands[2]
- = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) >> 16);
- return \"xorh %2,%1,%0\";
- }
- xop[0] = operands[0];
- xop[1] = operands[1];
- xop[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
- output_asm_insn (\"xor %2,%1,%0\", xop);
- operands[2] = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) >> 16);
- return \"xorh %2,%0,%0\";
-}")
-
-;(The i860 instruction set doesn't allow an immediate second operand in
-; a subtraction.)
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "general_operand" "=r")
- (neg:SI (match_operand:SI 1 "arith_operand" "r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"subu %?r0,%1,%0\";
-}")
-
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "general_operand" "=r")
- (not:SI (match_operand:SI 1 "arith_operand" "r")))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- return \"subu -1,%1,%0\";
-}")
-\f
-;; Floating point arithmetic instructions.
-
-(define_insn "adddf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (plus:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- ""
- "fadd.dd %1,%2,%0")
-
-(define_insn "addsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (plus:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- ""
- "fadd.ss %1,%2,%0")
-
-(define_insn "subdf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- ""
- "fsub.dd %1,%2,%0")
-
-(define_insn "subsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- ""
- "fsub.ss %1,%2,%0")
-
-(define_insn "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- ""
- "fmul.dd %1,%2,%0")
-
-(define_insn "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- ""
- "fmul.ss %1,%2,%0")
-
-(define_insn "negdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))]
- ""
- "fsub.dd %?f0,%1,%0")
-
-(define_insn "negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))]
- ""
- "fsub.ss %?f0,%1,%0")
-\f
-(define_insn "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (div:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))
- (clobber (match_scratch:DF 3 "=&f"))
- (clobber (match_scratch:DF 4 "=&f"))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0)
- || (cc_prev_status.flags & CC_HI_R31_ADJ)
- || (cc_prev_status.mdep != CONST2_RTX (SFmode)))
- {
- cc_status.flags |= CC_KNOW_HI_R31;
- cc_status.flags &= ~CC_HI_R31_ADJ;
- cc_status.mdep = CONST2_RTX (SFmode);
- return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\
-orh 0x4000,%?r0,%?r31\;ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\
-fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\";
- }
- else
- return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\
-ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\
-fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\";
-}")
-
-(define_insn "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=&f")
- (div:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))
- (clobber (match_scratch:SF 3 "=&f"))
- (clobber (match_scratch:SF 4 "=&f"))]
- ""
- "*
-{
- CC_STATUS_PARTIAL_INIT;
- if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0)
- || (cc_prev_status.flags & CC_HI_R31_ADJ)
- || (cc_prev_status.mdep != CONST2_RTX (SFmode)))
- {
- cc_status.flags |= CC_KNOW_HI_R31;
- cc_status.flags &= ~CC_HI_R31_ADJ;
- cc_status.mdep = CONST2_RTX (SFmode);
- output_asm_insn (\"orh 0x4000,%?r0,%?r31\", operands);
- }
- return \"ixfr %?r31,%4\;frcp.ss %2,%0\;\\
-fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;fmul.ss %0,%3,%0\;\\
-fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;\\
-fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
-}")
-\f
-;; Shift instructions
-
-;; Optimized special case of shifting.
-;; Must precede the general case.
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
- (const_int 24)))]
- ""
- "*
-{
- if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
- {
- CC_STATUS_INIT;
- cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
- cc_status.mdep = XEXP (operands[1], 0);
- return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
- }
- return \"ld.b %1,%0\";
-}")
-
-\f
-;;- arithmetic shift instructions
-(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashift:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "shift_operand" "rn")))]
- ""
- "*
-{
- return \"shl %2,%1,%0\";
-}")
-
-(define_insn "ashlhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (ashift:HI (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "shift_operand" "rn")))]
- ""
- "*
-{
- return \"shl %2,%1,%0\";
-}")
-
-(define_insn "ashlqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (ashift:QI (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "shift_operand" "rn")))]
- ""
- "*
-{
- return \"shl %2,%1,%0\";
-}")
-
-(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "shift_operand" "rn")))]
- ""
- "*
-{
- return \"shra %2,%1,%0\";
-}")
-
-(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "shift_operand" "rn")))]
- ""
- "*
-{
- return \"shr %2,%1,%0\";
-}")
-\f
-;; Unconditional and other jump instructions
-
-(define_insn "jump"
- [(set (pc) (label_ref (match_operand 0 "" "")))]
- ""
- "*
-{
- return \"br %l0\;nop\";
-}")
-
-;; Here are two simple peepholes which fill the delay slot of
-;; an unconditional branch.
-;
-;; ??? All disabled, because output_delayed_branch is a crock
-;; that will reliably segfault. This should be using the dbr
-;; pass in any case. Anyone who cares is welcome to fix it.
-;
-;(define_peephole
-; [(set (match_operand:SI 0 "register_operand" "=rf")
-; (match_operand:SI 1 "single_insn_src_p" "gfG"))
-; (set (pc) (label_ref (match_operand 2 "" "")))]
-; ""
-; "* return output_delayed_branch (\"br %l2\", operands, insn);")
-;
-;(define_peephole
-; [(set (match_operand:SI 0 "memory_operand" "=m")
-; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
-; (set (pc) (label_ref (match_operand 2 "" "")))]
-; ""
-; "* return output_delayed_branch (\"br %l2\", operands, insn);")
-
-(define_insn "tablejump"
- [(set (pc) (match_operand:SI 0 "register_operand" "r"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
- "bri %0\;nop")
-
-;(define_peephole
-; [(set (match_operand:SI 0 "memory_operand" "=m")
-; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
-; (set (pc) (match_operand:SI 2 "register_operand" "r"))
-; (use (label_ref (match_operand 3 "" "")))]
-; ""
-; "* return output_delayed_branch (\"bri %2\", operands, insn);")
-
-;;- jump to subroutine
-(define_expand "call"
- [(call (match_operand:SI 0 "memory_operand" "m")
- (match_operand 1 "" "i"))]
- ;; operand[2] is next_arg_register
- ""
- "
-{
- /* Make sure the address is just one reg and will stay that way. */
- if (! call_insn_operand (operands[0], QImode))
- operands[0]
- = replace_equiv_address (operands[0],
- copy_to_mode_reg (Pmode,
- XEXP (operands[0], 0)));
- if (INTVAL (operands[1]) > 0)
- {
- emit_move_insn (arg_pointer_rtx, stack_pointer_rtx);
- emit_insn (gen_rtx_USE (VOIDmode, arg_pointer_rtx));
- }
-}")
-
-;;- jump to subroutine
-(define_insn ""
- [(call (match_operand:SI 0 "call_insn_operand" "m")
- (match_operand 1 "" "i"))]
- ;; operand[2] is next_arg_register
- ""
- "*
-{
- /* strip the MEM. */
- operands[0] = XEXP (operands[0], 0);
- CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
- return \"calli %0\;nop\";
- return \"call %0\;nop\";
-}")
-
-;(define_peephole
-; [(set (match_operand:SI 0 "register_operand" "=rf")
-; (match_operand:SI 1 "single_insn_src_p" "gfG"))
-; (call (match_operand:SI 2 "memory_operand" "m")
-; (match_operand 3 "" "i"))]
-; ;;- Don't use operand 1 for most machines.
-; "! reg_mentioned_p (operands[0], operands[2])"
-; "*
-;{
-; /* strip the MEM. */
-; operands[2] = XEXP (operands[2], 0);
-; if (GET_CODE (operands[2]) == REG)
-; return output_delayed_branch (\"calli %2\", operands, insn);
-; return output_delayed_branch (\"call %2\", operands, insn);
-;}")
-
-;(define_peephole
-; [(set (match_operand:SI 0 "memory_operand" "=m")
-; (match_operand:SI 1 "reg_or_0_operand" "rfJ"))
-; (call (match_operand:SI 2 "call_insn_operand" "m")
-; (match_operand 3 "" "i"))]
-; ;;- Don't use operand 1 for most machines.
-; ""
-; "*
-;{
-; /* strip the MEM. */
-; operands[2] = XEXP (operands[2], 0);
-; if (GET_CODE (operands[2]) == REG)
-; return output_delayed_branch (\"calli %2\", operands, insn);
-; return output_delayed_branch (\"call %2\", operands, insn);
-;}")
-
-(define_expand "call_value"
- [(set (match_operand 0 "register_operand" "=rf")
- (call (match_operand:SI 1 "memory_operand" "m")
- (match_operand 2 "" "i")))]
- ;; operand 3 is next_arg_register
- ""
- "
-{
- /* Make sure the address is just one reg and will stay that way. */
- if (! call_insn_operand (operands[1], QImode))
- operands[1]
- = replace_equiv_address (operands[1],
- copy_to_mode_reg (Pmode,
- XEXP (operands[1], 0)));
- if (INTVAL (operands[2]) > 0)
- {
- emit_move_insn (arg_pointer_rtx, stack_pointer_rtx);
- emit_insn (gen_rtx_USE (VOIDmode, arg_pointer_rtx));
- }
-}")
-
-(define_insn ""
- [(set (match_operand 0 "register_operand" "=rf")
- (call (match_operand:SI 1 "call_insn_operand" "m")
- (match_operand 2 "" "i")))]
- ;; operand 3 is next_arg_register
- ""
- "*
-{
- /* strip the MEM. */
- operands[1] = XEXP (operands[1], 0);
- CC_STATUS_INIT;
- if (GET_CODE (operands[1]) == REG)
- return \"calli %1\;nop\";
- return \"call %1\;nop\";
-}")
-
-;(define_peephole
-; [(set (match_operand:SI 0 "register_operand" "=rf")
-; (match_operand:SI 1 "single_insn_src_p" "gfG"))
-; (set (match_operand 2 "" "=rf")
-; (call (match_operand:SI 3 "call_insn_operand" "m")
-; (match_operand 4 "" "i")))]
-; ;;- Don't use operand 4 for most machines.
-; "! reg_mentioned_p (operands[0], operands[3])"
-; "*
-;{
-; /* strip the MEM. */
-; operands[3] = XEXP (operands[3], 0);
-; if (GET_CODE (operands[3]) == REG)
-; return output_delayed_branch (\"calli %3\", operands, insn);
-; return output_delayed_branch (\"call %3\", operands, insn);
-;}")
-
-;(define_peephole
-; [(set (match_operand:SI 0 "memory_operand" "=m")
-; (match_operand:SI 1 "reg_or_0_operand" "rJf"))
-; (set (match_operand 2 "" "=rf")
-; (call (match_operand:SI 3 "call_insn_operand" "m")
-; (match_operand 4 "" "i")))]
-; ;;- Don't use operand 4 for most machines.
-; ""
-; "*
-;{
-; /* strip the MEM. */
-; operands[3] = XEXP (operands[3], 0);
-; if (GET_CODE (operands[3]) == REG)
-; return output_delayed_branch (\"calli %3\", operands, insn);
-; return output_delayed_branch (\"call %3\", operands, insn);
-;}")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
- (const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
- ""
- "
-{
- int i;
-
- emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
-
- for (i = 0; i < XVECLEN (operands[2], 0); i++)
- {
- rtx set = XVECEXP (operands[2], 0, i);
- emit_move_insn (SET_DEST (set), SET_SRC (set));
- }
-
- /* The optimizer does not know that the call sets the function value
- registers we stored in the result block. We avoid problems by
- claiming that all hard registers are used and clobbered at this
- point. */
- emit_insn (gen_blockage ());
-
- DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory. This blocks insns from being moved across this point.
-
-(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
- ""
- "")
-\f
-(define_insn "nop"
- [(const_int 0)]
- ""
- "nop")
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
- ""
- "bri %0")
-\f
-;;
-;; A special insn that does the work to get setup just
-;; before a table jump.
-;;
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
- (label_ref (match_operand 2 "" "")))))]
- ""
- "*
-{
- CC_STATUS_INIT;
- return \"orh %H2,%?r0,%?r31\;or %L2,%?r31,%?r31\;ld.l %?r31(%1),%0\";
-}")
-
-;(define_peephole
-; [(set (match_operand:SI 0 "register_operand" "=rf")
-; (match_operand:SI 1 "single_insn_src_p" "gfG"))
-; (set (pc) (match_operand:SI 2 "register_operand" "r"))
-; (use (label_ref (match_operand 3 "" "")))]
-; "REGNO (operands[0]) != REGNO (operands[2])"
-; "* return output_delayed_branch (\"bri %2\", operands, insn);")
+++ /dev/null
-/* Configuration for an i860 running Mach as the target machine. */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 Mach3.x)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di860 -DMACH -Asystem=unix -Asystem=mach -Acpu=i860 -Amachine=i860"
-
-/* Specify extra dir to search for include files. */
-#define SYSTEM_INCLUDE_DIR "/usr/mach/include"
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
- we want to retain compatibility with older gcc versions. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
+++ /dev/null
-/* Target definitions for GNU compiler for Intel 80860 running OSF/1AD
- Copyright (C) 1991, 1996, 1999, 2000, 2002 Free Software Foundation, Inc.
- Based upon original work of Ron Guilmette (rfg@monkeys.com).
- Contributed by Andy Pfiffer (andyp@ssd.intel.com).
- Partially inspired by
- Pete Beckman of Indiana University (beckman@cs.indiana.edu)
- Harry Dolan of Intel Corporation (dolan@ssd.intel.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#undef TARGET_SWITCHES
-#define TARGET_SWITCHES \
- { {"xp", 1, N_("Generate code which uses the FPU")}, \
- {"noxp", -1, N_("Do not generate code which uses the FPU")}, \
- {"xr", -1, N_("Do not generate code which uses the FPU")}, \
- {"noieee", -1, N_("Do not generate code which uses the FPU")}, \
- {"nx", 2, NULL}, \
- { "", TARGET_DEFAULT, NULL}}
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-
-/* The Intel as860 assembler does not understand .stabs, must use COFF */
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 OSF/1AD)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di860 -D__i860 -D__i860__ -D__PARAGON__ -D__OSF1__ -D_COFF -Dunix -DMACH -DCMU"
-
-#define CPP_SPEC "%{mnx:-D__NODE}"
-
-/* autoinit.o autolaunches NX applications */
-#define STARTFILE_SPEC "crt0.o%s %{mnx:-yoptions/autoinit.o%s}"
-
-/* libic.a is the PGI intrinsic library */
-/* libpm.o and guard.o are for the performance monitoring modules (ignored) */
-/* /usr/lib/noieee contains non-IEEE compliant (but faster) math routines */
-#if HAVE_DASH_G
-#define LIB_SPEC \
-"%{mnoieee:-L/usr/lib/noieee} %{mnx:-lnx} %{g*:-lg} -lc -lmach -lc -lic"
-#else /* HAVE_DASH_G */
-/* can't use -g for -lg; libg.a doesn't have a symbol table and ld complains */
-#define LIB_SPEC "%{mnoieee:-L/usr/lib/noieee} %{mnx:-lnx} -lc -lmach -lc -lic"
-#endif /* HAVE_DASH_G */
-
-/* Get rid of definition from svr3.h. */
-#undef SIZE_TYPE
-
-#undef I860_REG_PREFIX
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "//"
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT "\"%s\""
-
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP "\t.byte\t"
-
-/*
- * the assembler we're using doesn't grok .ident...
- */
-#undef ASM_OUTPUT_IDENT
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
- fprintf (FILE, "//\t.ident \"%s\"\n", NAME);
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH) \
- do \
- { \
- register const unsigned char *str = (const unsigned char *) (STR); \
- register const unsigned char *limit = str + (LENGTH); \
- register unsigned bytes_in_chunk = 0; \
- for (; str < limit; str++) \
- { \
- register unsigned ch = *str; \
- if (ch < 32 || ch == '\\' || ch == '"' || ch >= 127) \
- { \
- if (bytes_in_chunk > 0) \
- { \
- fprintf ((FILE), "\"\n"); \
- bytes_in_chunk = 0; \
- } \
- assemble_aligned_integer (1, GEN_INT (ch)); \
- } \
- else \
- { \
- if (bytes_in_chunk >= 60) \
- { \
- fprintf ((FILE), "\"\n"); \
- bytes_in_chunk = 0; \
- } \
- if (bytes_in_chunk == 0) \
- fprintf ((FILE), "%s\"", ASCII_DATA_ASM_OP); \
- putc (ch, (FILE)); \
- bytes_in_chunk++; \
- } \
- } \
- if (bytes_in_chunk > 0) \
- fprintf ((FILE), "\"\n"); \
- } \
- while (0)
-
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/*
- * not defining ASM_STABS_OP yields .stabs in the .s file
- * when using g++ -- so, I'll define it.
- */
-#define ASM_STABS_OP "//.stabs"
-
-/* Define this macro if an instruction to load a value narrower
- than a word from memory into a register also zero-extends the
- value to the whole register. */
-/*#define BYTE_LOADS_ZERO_EXTEND*/
-
-/* Define this macro as a C expression which is nonzero if
- accessing less than a word of memory (i.e. a `char' or a
- `short') is no faster than accessing a word of memory, i.e., if
- such access require more than one instruction or if there is no
- difference in cost between byte and (aligned) word loads.
-
- On RISC machines, it tends to generate better code to define
- this as 1, since it avoids making a QI or HI mode register. */
-/*
-#undef SLOW_BYTE_ACCESS
-#define SLOW_BYTE_ACCESS 1
-*/
-
-/* Define if shifts truncate the shift count
- which implies one can omit a sign-extension or zero-extension
- of a shift count. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-
-#define FASTEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster. */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- (TREE_CODE (EXP) == STRING_CST \
- && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons. */
-#define DATA_ALIGNMENT(TYPE, ALIGN) \
- (TREE_CODE (TYPE) == ARRAY_TYPE \
- && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
- && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/*
- * disable a few things picked up from svr3.h
- */
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef READONLY_DATA_SECTION_ASM_OP
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-#undef DO_GLOBAL_CTORS_BODY
-#undef ASM_OUTPUT_DESTRUCTOR
-#undef TARGET_ASM_SELECT_SECTION
-
-#define BSS_SECTION_ASM_OP "\t.bss" /* XXX */
-#undef EXTRA_SECTIONS
-#undef EXTRA_SECTION_FUNCTIONS
+++ /dev/null
-/* Target definitions for GNU compiler for Intel 80860 running System V.3
- Copyright (C) 1991, 1996, 2000, 2002 Free Software Foundation, Inc.
- Contributed by Ron Guilmette (rfg@monkeys.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860, System V Release 3)")
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
- the i860 running svr3. */
-#define CPP_PREDEFINES "-Di860 -Dunix -D__svr3__ -Asystem=unix -Asystem=svr3 -Acpu=i860 -Amachine=i860"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file. */
-
-#define STARTFILE_SPEC \
- "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-#define LIB_SPEC "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} -lc crtn.o%s"
-
-/* Special flags for the linker. I don't know what they do. */
-
-#define LINK_SPEC "%{T*} %{z:-lm}"
-
-/* The prefix to be used in assembler output for all names of registers.
- None is needed in V.3. */
-
-#define I860_REG_PREFIX ""
-
-/* Delimiter that starts comments in the assembler code. */
-
-#define ASM_COMMENT_START "//"
-
-/* Output the special word the System V SDB wants to see just before
- the first word of each function's prologue code. */
-
-extern const char *current_function_original_name;
-
-/* This special macro is used to output a magic word just before the
- first word of each function. On some versions of UNIX running on
- the i860, this word can be any word that looks like a NOP, however
- under svr4, this neds to be an `shr r0,r0,r0' instruction in which
- the normally unused low-order bits contain the length of the function
- prologue code (in bytes). This is needed to make the System V SDB
- debugger happy. */
-
-#undef ASM_OUTPUT_FUNCTION_PREFIX
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \
- do { ASM_OUTPUT_ALIGN (FILE, 2); \
- fprintf ((FILE), "\t.long\t.ep."); \
- assemble_name (FILE, FNNAME); \
- fprintf (FILE, "-"); \
- assemble_name (FILE, FNNAME); \
- fprintf (FILE, "+0xc8000000\n"); \
- current_function_original_name = (FNNAME); \
- } while (0)
-
-/* Output the special label that must go just after each function's
- prologue code to support svr4 SDB. */
-
-#define ASM_OUTPUT_PROLOGUE_SUFFIX(FILE) \
- do { fprintf (FILE, ".ep."); \
- assemble_name (FILE, current_function_original_name); \
- fprintf (FILE, ":\n"); \
- } while (0)
-
-/* This says how to output an assembler line
- to define a local common symbol.
- The difference from svr3.h is we don't limit align to 2. */
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
- do { \
- int align = exact_log2 (ROUNDED); \
- data_section (); \
- ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \
- ASM_OUTPUT_LABEL ((FILE), (NAME)); \
- fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \
- } while (0)
-
-/* The routine used to output string literals. */
-
-#define ASCII_DATA_ASM_OP "\t.byte\t"
-
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH) \
- do \
- { \
- register const unsigned char *str = (const unsigned char *) (STR); \
- register const unsigned char *limit = str + (LENGTH); \
- register unsigned bytes_in_chunk = 0; \
- for (; str < limit; str++) \
- { \
- register unsigned ch = *str; \
- if (ch < 32 || ch == '\\' || ch == '"' || ch >= 127) \
- { \
- if (bytes_in_chunk > 0) \
- { \
- fprintf ((FILE), "\"\n"); \
- bytes_in_chunk = 0; \
- } \
- assemble_aligned_integer (1, GEN_INT (ch)); \
- } \
- else \
- { \
- if (bytes_in_chunk >= 60) \
- { \
- fprintf ((FILE), "\"\n"); \
- bytes_in_chunk = 0; \
- } \
- if (bytes_in_chunk == 0) \
- fprintf ((FILE), "%s\"", ASCII_DATA_ASM_OP); \
- putc (ch, (FILE)); \
- bytes_in_chunk++; \
- } \
- } \
- if (bytes_in_chunk > 0) \
- fprintf ((FILE), "\"\n"); \
- } \
- while (0)
-
-
-#define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata, \"x\""
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"x\""
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"x\""
-
-/* Add definitions to support the .tdesc section as specified in the svr4
- ABI for the i860. */
-
-#define TDESC_SECTION_ASM_OP "\t.section\t.tdesc"
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_tdesc
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS \
- TDESC_SECTION_FUNCTION
-
-#define TDESC_SECTION_FUNCTION \
-void \
-tdesc_section () \
-{ \
- if (in_section != in_tdesc) \
- { \
- fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP); \
- in_section = in_tdesc; \
- } \
-}
+++ /dev/null
-/* Target definitions for GNU compiler for Intel 80860 running System V.4
- Copyright (C) 1991, 1996, 2000, 2002 Free Software Foundation, Inc.
- Contributed by Ron Guilmette (rfg@monkeys.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 System V Release 4)");
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
- the i860 running svr4. Note that the symbol `__svr4__' MUST BE
- DEFINED! It is needed so that the va_list struct in va-i860.h
- will get correctly defined for the svr4 (ABI compliant) case rather
- than for the previous (svr3, svr2, ...) case. It also needs to be
- defined so that the correct (svr4) version of __builtin_saveregs
- will be selected when we are building gnulib2.c.
- __svr4__ is our extension. */
-
-#define CPP_PREDEFINES \
- "-Di860 -Dunix -DSVR4 -D__svr4__ -Asystem=unix -Asystem=svr4 -Acpu=i860 -Amachine=i860"
-
-/* For the benefit of i860_va_arg, flag it this way too. */
-
-#define I860_SVR4_VA_LIST 1
-
-/* The prefix to be used in assembler output for all names of registers.
- This string gets prepended to all i860 register names (svr4 only). */
-
-#define I860_REG_PREFIX "%"
-
-#define ASM_COMMENT_START "#"
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT "\"%s\""
-
-/* The following macro definition overrides the one in i860.h
- because the svr4 i860 assembler requires a different syntax
- for getting parts of constant/relocatable values. */
-
-#undef PRINT_OPERAND_PART
-#define PRINT_OPERAND_PART(FILE, X, PART_CODE) \
- do { fprintf (FILE, "["); \
- output_address (X); \
- fprintf (FILE, "]@%s", PART_CODE); \
- } while (0)
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
- do { output_file_directive (FILE, main_input_filename); \
- fprintf (FILE, "\t.version\t\"01.01\"\n"); \
- } while (0)
-
-/* Output the special word the svr4 SDB wants to see just before
- the first word of each function's prologue code. */
-
-extern const char *current_function_original_name;
-
-/* This special macro is used to output a magic word just before the
- first word of each function. On some versions of UNIX running on
- the i860, this word can be any word that looks like a NOP, however
- under svr4, this neds to be an `shr r0,r0,r0' instruction in which
- the normally unused low-order bits contain the length of the function
- prologue code (in bytes). This is needed to make the svr4 SDB debugger
- happy. */
-
-#undef ASM_OUTPUT_FUNCTION_PREFIX
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \
- do { ASM_OUTPUT_ALIGN (FILE, 2); \
- fprintf ((FILE), "\t.long\t.ep."); \
- assemble_name (FILE, FNNAME); \
- fprintf (FILE, "-"); \
- assemble_name (FILE, FNNAME); \
- fprintf (FILE, "+0xc8000000\n"); \
- current_function_original_name = (FNNAME); \
- } while (0)
-
-/* Output the special label that must go just after each function's
- prologue code to support svr4 SDB. */
-
-#define ASM_OUTPUT_PROLOGUE_SUFFIX(FILE) \
- do { fprintf (FILE, ".ep."); \
- assemble_name (FILE, current_function_original_name); \
- fprintf (FILE, ":\n"); \
- } while (0)
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
-
- Note that we want to give these sections the SHF_WRITE attribute
- because these sections will actually contain data (i.e. tables of
- addresses of functions in the current root executable or shared library
- file) and, in the case of a shared library, the relocatable addresses
- will have to be properly resolved/relocated (and then written into) by
- the dynamic linker when it actually attaches the given shared library
- to the executing process. (Note that on SVR4, you may wish to use the
- `-z text' option to the ELF linker, when building a shared library, as
- an additional check that you are doing everything right. But if you do
- use the `-z text' option when building a shared library, you will get
- errors unless the .ctors and .dtors sections are marked as writable
- via the SHF_WRITE attribute.) */
-
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
-
-/* Add definitions to support the .tdesc section as specified in the svr4
- ABI for the i860. */
-
-#define TDESC_SECTION_ASM_OP "\t.section\t.tdesc"
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_tdesc
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS \
- TDESC_SECTION_FUNCTION
-
-#define TDESC_SECTION_FUNCTION \
-void \
-tdesc_section () \
-{ \
- if (in_section != in_tdesc) \
- { \
- fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP); \
- in_section = in_tdesc; \
- } \
-}
-
+++ /dev/null
-# Use ieee rounding rules for divide and square root operations.
-# /bin/cc is assumed to point to fxc version 1.3 or newer.
-CCLIBFLAGS=-O -ieee -uniproc
+++ /dev/null
-/* Special varargs support for i860.
- Copyright (C) 2001 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file. (The General Public License restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#if defined(__svr4__) || defined(__alliant__)
- .text
- .align 4
-
-/* The Alliant needs the added underscore. */
- .globl __builtin_saveregs
-__builtin_saveregs:
- .globl ___builtin_saveregs
-___builtin_saveregs:
-
- andnot 0x0f,%sp,%sp /* round down to 16-byte boundary */
- adds -96,%sp,%sp /* allocate stack space for reg save
- area and also for a new va_list
- structure */
- /* Save all argument registers in the arg reg save area. The
- arg reg save area must have the following layout (according
- to the svr4 ABI):
-
- struct {
- union {
- float freg[8];
- double dreg[4];
- } float_regs;
- long ireg[12];
- };
- */
-
- fst.q %f8, 0(%sp) /* save floating regs (f8-f15) */
- fst.q %f12,16(%sp)
-
- st.l %r16,32(%sp) /* save integer regs (r16-r27) */
- st.l %r17,36(%sp)
- st.l %r18,40(%sp)
- st.l %r19,44(%sp)
- st.l %r20,48(%sp)
- st.l %r21,52(%sp)
- st.l %r22,56(%sp)
- st.l %r23,60(%sp)
- st.l %r24,64(%sp)
- st.l %r25,68(%sp)
- st.l %r26,72(%sp)
- st.l %r27,76(%sp)
-
- adds 80,%sp,%r16 /* compute the address of the new
- va_list structure. Put in into
- r16 so that it will be returned
- to the caller. */
-
- /* Initialize all fields of the new va_list structure. This
- structure looks like:
-
- typedef struct {
- unsigned long ireg_used;
- unsigned long freg_used;
- long *reg_base;
- long *mem_ptr;
- } va_list;
- */
-
- st.l %r0, 0(%r16) /* nfixed */
- st.l %r0, 4(%r16) /* nfloating */
- st.l %sp, 8(%r16) /* __va_ctl points to __va_struct. */
- bri %r1 /* delayed return */
- st.l %r28,12(%r16) /* pointer to overflow args */
-
-#else /* not __svr4__ */
-#if defined(__PARAGON__)
- /*
- * we'll use SVR4-ish varargs but need SVR3.2 assembler syntax,
- * and we stand a better chance of hooking into libraries
- * compiled by PGI. [andyp@ssd.intel.com]
- */
- .text
- .align 4
- .globl __builtin_saveregs
-__builtin_saveregs:
- .globl ___builtin_saveregs
-___builtin_saveregs:
-
- andnot 0x0f,sp,sp /* round down to 16-byte boundary */
- adds -96,sp,sp /* allocate stack space for reg save
- area and also for a new va_list
- structure */
- /* Save all argument registers in the arg reg save area. The
- arg reg save area must have the following layout (according
- to the svr4 ABI):
-
- struct {
- union {
- float freg[8];
- double dreg[4];
- } float_regs;
- long ireg[12];
- };
- */
-
- fst.q f8, 0(sp)
- fst.q f12,16(sp)
- st.l r16,32(sp)
- st.l r17,36(sp)
- st.l r18,40(sp)
- st.l r19,44(sp)
- st.l r20,48(sp)
- st.l r21,52(sp)
- st.l r22,56(sp)
- st.l r23,60(sp)
- st.l r24,64(sp)
- st.l r25,68(sp)
- st.l r26,72(sp)
- st.l r27,76(sp)
-
- adds 80,sp,r16 /* compute the address of the new
- va_list structure. Put in into
- r16 so that it will be returned
- to the caller. */
-
- /* Initialize all fields of the new va_list structure. This
- structure looks like:
-
- typedef struct {
- unsigned long ireg_used;
- unsigned long freg_used;
- long *reg_base;
- long *mem_ptr;
- } va_list;
- */
-
- st.l r0, 0(r16) /* nfixed */
- st.l r0, 4(r16) /* nfloating */
- st.l sp, 8(r16) /* __va_ctl points to __va_struct. */
- bri r1 /* delayed return */
- st.l r28,12(r16) /* pointer to overflow args */
-#else /* not __PARAGON__ */
- .text
- .align 4
-
- .globl ___builtin_saveregs
-___builtin_saveregs:
- mov sp,r30
- andnot 0x0f,sp,sp
- adds -96,sp,sp /* allocate sufficient space on the stack */
-
-/* Fill in the __va_struct. */
- st.l r16, 0(sp) /* save integer regs (r16-r27) */
- st.l r17, 4(sp) /* int fixed[12] */
- st.l r18, 8(sp)
- st.l r19,12(sp)
- st.l r20,16(sp)
- st.l r21,20(sp)
- st.l r22,24(sp)
- st.l r23,28(sp)
- st.l r24,32(sp)
- st.l r25,36(sp)
- st.l r26,40(sp)
- st.l r27,44(sp)
-
- fst.q f8, 48(sp) /* save floating regs (f8-f15) */
- fst.q f12,64(sp) /* int floating[8] */
-
-/* Fill in the __va_ctl. */
- st.l sp, 80(sp) /* __va_ctl points to __va_struct. */
- st.l r28,84(sp) /* pointer to more args */
- st.l r0, 88(sp) /* nfixed */
- st.l r0, 92(sp) /* nfloating */
-
- adds 80,sp,r16 /* return address of the __va_ctl. */
- bri r1
- mov r30,sp
- /* recover stack and pass address to start
- of data. */
-#endif /* not __PARAGON__ */
-#endif /* not __svr4__ */
+++ /dev/null
-/* Definitions for Motorola 680x0 running A/UX
- Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* This file was renamed from aux.h because of MSDOS: aux.anything
- isn't usable. Sigh. */
-
-/* Execution environment */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020) /* 68020, 68881 */
-
-#define CPP_PREDEFINES "-Dunix -Dm68k -DAUX -DmacII \
--Asystem=unix -Asystem=AUX -Acpu=m68k -Amachine=m68k -Amachine=macII"
-
-#define CPP_SPEC \
-"%{!msoft-float:%{!ansi:-Dmc68881 }-D__HAVE_68881__ }\
--Acpu=mc68000 -D__mc68000__ %{!ansi:-Dmc68000 }\
-%{!mc68000:%{!m68000:-Acpu=mc68020 -D__mc68020__ %{!ansi:-Dmc68020 }}}\
-%{m68030:-Acpu=mc68030 -D__mc68030__ %{!ansi:-Dmc68030 }}\
-%{m68040:-Acpu=mc68040 -D__mc68040__ %{!ansi:-Dmc68040 }}\
-%{!ansi:-D__STDC__=2 }\
-%{sbsd:-D_BSD_SOURCE -DBSD }%{ZB:-D_BSD_SOURCE -DBSD }\
-%{ssysv:-D_SYSV_SOURCE -DSYSV -DUSG }%{ZS:-D_SYSV_SOURCE -DSYSV -DUSG }\
-%{sposix:-D_POSIX_SOURCE -DPOSIX }%{ZP:-D_POSIX_SOURCE -DPOSIX }\
-%{sposix+:-D_POSIX_SOURCE -DPOSIX }\
-%{saux:-D_AUX_SOURCE }%{ZA:-D_AUX_SOURCE }\
-%{!sbsd:%{!ZB:%{!ssysv:%{!ZS:%{!sposix:%{!ZP:%{!snone:\
--D_BSD_SOURCE -D_SYSV_SOURCE -D_AUX_SOURCE }}}}}}}"
-
-#define LIB_SPEC \
-"%{sbsd:-lbsd }%{ZB:-lbsd }\
-%{ssysv:-lsvid }%{ZS:-lsvid }\
-%{sposix:-lposix }%{ZP:-lposix }%{sposix+:-lposix }\
-%{!static:%{smac:-lmac_s -lat -lld -lmr }-lc_s }\
-%{static:%{smac:-lmac -lat -lld -lmr }-lc }"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-"%{pg:mcrt0.o%s }%{!pg:%{p:mcrt1.o%s }\
-%{!p:%{smac:maccrt1.o%s low.o%s }%{!smac:crt1.o%s }}}\
-crt2.o%s "
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtn.o%s "
-
-
-/*===================================================================*/
-/* Compilation environment -- mostly */
-
-/* We provide atexit(), A/UX does not have it */
-#define NEED_ATEXIT
-
-/* Generate calls to memcpy, memcmp and memset, as opposed to bcopy, bcmp,
- and bzero */
-#define TARGET_MEM_FUNCTIONS
-
-/* Resize standard types */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "unsigned int"
-
-/* Every structure or union's size must be a multiple of 2 bytes. */
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Bits needed by collect */
-
-#define OBJECT_FORMAT_COFF
-#define MY_ISCOFF(m) ((m) == M68TVMAGIC || \
- (m) == M68MAGIC || \
- (m) == MC68TVMAGIC || \
- (m) == MC68MAGIC || \
- (m) == M68NSMAGIC)
-
-
-#ifndef USE_COLLECT2
-/* For .ctor/.dtor sections for collecting constructors */
-/* We have special start/end files for defining [cd]tor lists */
-#define CTOR_LISTS_DEFINED_EXTERNALLY
-#endif
-
-
-/*======================================================================*/
-/* Calling convention and library support changes */
-
-/* Define how to generate (in the callee) the output value of a function
- and how to find (in the caller) the value returned by a function. VALTYPE
- is the data type of the value (as a tree). If the precise function being
- called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
- For A/UX generate the result in d0, a0, or fp0 as appropriate. */
-
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881 \
- ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \
- : (POINTER_TYPE_P (VALTYPE) \
- ? gen_rtx_REG (TYPE_MODE (VALTYPE), 8) \
- : gen_rtx_REG (TYPE_MODE (VALTYPE), 0)))
-
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG ((MODE), ((TARGET_68881 && \
- ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0))
-
-/* 1 if N is a possible register number for a function value.
- For A/UX allow d0, a0, or fp0 as return registers, for integral,
- pointer, or floating types, respectively. Reject fp0 if not using a
- 68881 coprocessor. */
-
-#undef FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) \
- ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16))
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
- more than one register. */
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
-
-/* For compatibility with the large body of existing code which does not
- always properly declare external functions returning pointer types, the
- A/UX convention is to copy the value returned for pointer functions
- from a0 to d0 in the function epilogue, so that callers that have
- neglected to properly declare the callee can still find the correct return
- value. */
-
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \
-{ \
- if (current_function_returns_pointer \
- && ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \
- asm_fprintf (FILE, "\t%s %Ra0,%Rd0\n", ASM_MOV_INSN); \
-}
-
-/* How to call the function profiler */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- asm_fprintf (FILE, "\t%Olea %LLP%d,%Ra0\n\t%Ojbsr %s\n", \
- (LABELNO), FUNCTION_PROFILER_SYMBOL)
-
-/* Finalize the trampoline by flushing the insn cache */
-
-#undef FINALIZE_TRAMPOLINE
-#define FINALIZE_TRAMPOLINE(TRAMP) \
- emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
- 0, VOIDmode, 2, TRAMP, Pmode, \
- plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode);
-
-/* Clear the instruction cache from `beg' to `end'. This makes an
- inline system call to SYS_sysm68k. The arguments are as follows:
-
- sysm68k(105, addr, scope, cache, len)
-
- 105 - the subfunction code to clear the cache
- addr - the start address for the flush
- scope - the scope of the flush (see the cpush insn)
- cache - which cache to flush (see the cpush insn)
- len - a factor relating to the number of flushes to perform :
- len/16 lines, or len/4096 pages.
-
- While all this is only really relevant to 040's, the system call
- will just return an error (which we ignore) on other systems. */
-
-#define CLEAR_INSN_CACHE(beg, end) \
-{ \
- unsigned _beg = (unsigned)(beg), _end = (unsigned)(end); \
- unsigned _len = ((_end / 16) - (_beg / 16) + 1) * 16; \
- __asm __volatile( \
- ASM_MOV_INSN " %1, %-\n\t" /* nr lines */ \
- ASM_MOV_INSN " %#3, %-\n\t" /* insn+data caches */ \
- ASM_MOV_INSN " %#1, %-\n\t" /* clear lines */ \
- ASM_MOV_INSN " %0, %-\n\t" /* beginning of buffer */ \
- ASM_MOV_INSN " %#105, %-\n\t" /* cache sub-function nr */ \
- ASM_MOV_INSN " %#0, %-\n\t" /* dummy return address */ \
- ASM_MOV_INSN " %#38, %/d0\n\t" /* system call nr */ \
- "trap %#0\n\t" \
- "add%.l %#24, %/sp" \
- : /* no outputs */ \
- : "g"(_beg), "g"(_len) \
- : "%d0"); \
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Altos 3068 68020 version.
- Copyright (C) 1988, 1989, 1993, 1996 Free Software Foundation, Inc.
- Contributed by Jyrki Kuoppala <jkp@cs.hut.fi>
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-#include "m68k/m68k.h"
-
-/* See m68k.h. 7 means 68020 with 68881. */
-/* 5 is without 68881. Change to 7 if you have 68881 */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-/* Don't try using XFmode. */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-#endif
-
-/* Define __HAVE_68881__ in preprocessor,
- according to the -m flags.
- This will control the use of inline 68881 insns in certain macros.
- Also inform the program which CPU this is for. */
-
-#if TARGET_DEFAULT & MASK_68881
-
-/* -m68881 is the default */
-#define CPP_SPEC \
-"%{!msoft-float:-D__HAVE_68881__ }\
-%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }\
-%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}"
-
-#endif
-
-/* -m68000 requires special flags to the assembler. */
-
-#define ASM_SPEC \
- "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}"
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Dmc68000 -DPORTAR -Dmc68k32 -Uvax -Dm68k -Dunix -Asystem=unix -Acpu=m68k -Amachine=m68k"
-
-/* Every structure or union's size must be a multiple of 2 bytes. */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Generate calls to memcpy, memcmp and memset. */
-#define TARGET_MEM_FUNCTIONS
-
-/* We use gnu assembler, linker and gdb, so we want DBX format. */
-
-#define DBX_DEBUGGING_INFO
-
-/* Tell some conditionals we will use GAS. Is this really used? */
-
-#define USE_GAS
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
- do { \
- if (CODE == 'f') \
- { \
- char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
- fprintf (FILE, "#0r%s", dstr); \
- } \
- else \
- { \
- long l; \
- REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
- if (sizeof (int) == sizeof (long)) \
- asm_fprintf ((FILE), "%I0x%x", (int) l); \
- else \
- asm_fprintf ((FILE), "%I0x%lx", l); \
- } \
- } while (0)
-
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
- do { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
- fprintf (FILE, "#0r%s", dstr); \
- } while (0)
-
-/* Return pointer values in both d0 and a0. */
-
-#undef FUNCTION_EXTRA_EPILOGUE
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \
-{ \
- if (current_function_returns_pointer \
- && ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \
- fprintf (FILE, "\tmovel d0,a0\n"); \
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Apollo 680X0 version.
- Copyright (C) 1989, 1992, 1996, 1997, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "m68k/m68k.h"
-
-/* This symbol may be tested in other files for special Apollo handling */
-
-#define TM_APOLLO
-
-/* See m68k.h. 7 means 68020 with 68881. */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Target switches for the Apollo is the same as in m68k.h, except
- there is no Sun FPA. */
-
-#undef TARGET_SWITCHES
-#define TARGET_SWITCHES \
- { { "68020", 5}, \
- { "c68020", 5}, \
- { "68881", 2}, \
- { "bitfield", 4}, \
- { "68000", -5}, \
- { "c68000", -5}, \
- { "soft-float", -0102}, \
- { "nobitfield", -4}, \
- { "rtd", 8}, \
- { "nortd", -8}, \
- { "short", 040}, \
- { "noshort", -040}, \
- { "", TARGET_DEFAULT}}
-
-/* Define __HAVE_68881__ in preprocessor,
- according to the -m flags.
- This will control the use of inline 68881 insns in certain macros.
- Also inform the program which CPU this is for. */
-
-#if TARGET_DEFAULT & MASK_68881
-
-/* -m68881 is the default */
-#define CPP_SPEC \
-"%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\
-%{!ansi:%{m68000:-Dmc68010 }%{mc68000:-Dmc68010 }%{!mc68000:%{!m68000:-Dmc68020 }}\
-%{!ansi:-D_APOLLO_SOURCE}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\
-%{!ansi:%{m68000:-Dmc68010 }%{mc68000:-Dmc68010 }%{!mc68000:%{!m68000:-Dmc68020 }}\
-%{!ansi:-D_APOLLO_SOURCE}}"
-
-#endif
-
-/* Names to predefine in the preprocessor for this target machine. */
-/* These are the ones defined by Apollo, plus mc68000 for uniformity with
- GCC on other 68000 systems. */
-
-#define CPP_PREDEFINES "-Dapollo -Daegis -Dunix -Asystem=unix -Acpu=m68k -Amachine=m68k"
-
-/* cpp has to support a #sccs directive for the /usr/include files */
-
-#define SCCS_DIRECTIVE
-
-/* Allow #ident but output nothing for it. */
-
-#define IDENT_DIRECTIVE
-#define ASM_OUTPUT_IDENT(FILE, NAME)
-
-/* -m68000 requires special flags to the assembler. */
-
-#define ASM_SPEC \
- "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}"
-
-/* STARTFILE_SPEC
- Note that includes knowledge of the default specs for gcc, ie. no
- args translates to the same effect as -m68881 */
-
-#if TARGET_DEFAULT & MASK_68881
-/* -m68881 is the default */
-#define STARTFILE_SPEC \
- "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-#else
-/* -msoft-float is the default */
-#define STARTFILE_SPEC \
- "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-#endif
-
-/* Specify library to handle `-a' basic block profiling. */
-
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{a:/usr/lib/bb_link.o} "
-
-/* Debugging is not supported yet */
-
-#undef DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-
-/* troy@cbme.unsw.edu.au says people are still using sr10.2
- and it does not support atexit. */
-#define NEED_ATEXIT
-
-/* Every structure or union's size must be a multiple of 2 bytes. */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#undef STACK_BOUNDARY
-#define STACK_BOUNDARY 32
-
-/* Functions which return large structures get the address
- to place the wanted value from a hidden parameter. */
-
-#undef PCC_STATIC_STRUCT_RETURN
-#undef STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE 0
-#define STRUCT_VALUE_INCOMING 0
-
-/* Specify how to pad function arguments.
- Arguments are not padded at all; the stack is kept aligned on long
- boundaries. */
-
-#define FUNCTION_ARG_PADDING(mode, size) none
-
-/* The definition of this macro imposes a limit on the size of
- an aggregate object which can be treated as if it were a scalar
- object. */
-
-#define MAX_FIXED_MODE_SIZE BITS_PER_WORD
-
-/* The definition of this macro implies that there are cases where
- a scalar value cannot be returned in registers.
- For Apollo, anything larger than one integer register is returned
- using the structure-value mechanism, i.e. objects of DFmode are
- returned that way. */
-
-#define RETURN_IN_MEMORY(type) \
- (TYPE_MODE (type) == BLKmode \
- || GET_MODE_SIZE (TYPE_MODE (type)) > UNITS_PER_WORD)
-
-/* In order to link with Apollo libraries, we can't prefix external
- symbols with an underscore. */
-
-#undef USER_LABEL_PREFIX
-
-/* Use a prefix for local labels, just to be on the save side. */
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* Use a register prefix to avoid clashes with external symbols (classic
- example: `extern char PC;' in termcap). */
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-/* config/m68k.md has an explicit reference to the program counter,
- prefix this by the register prefix. */
-
-#define ASM_RETURN_CASE_JUMP \
- do { \
- if (TARGET_5200) \
- return "ext%.l %0\n\tjmp %%pc@(2,%0:l)"; \
- else \
- return "jmp %%pc@(2,%0:w)"; \
- } while (0)
-
-/* Here are the new register names. */
-
-#undef REGISTER_NAMES
-#ifndef SUPPORT_SUN_FPA
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" }
-#else /* SUPPORTED_SUN_FPA */
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", \
- "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6", "%fpa7", \
- "%fpa8", "%fpa9", "%fpa10", "%fpa11", "%fpa12", "%fpa13", "%fpa14", "%fpa15", \
- "%fpa16", "%fpa17", "%fpa18", "%fpa19", "%fpa20", "%fpa21", "%fpa22", "%fpa23", \
- "%fpa24", "%fpa25", "%fpa26", "%fpa27", "%fpa28", "%fpa29", "%fpa30", "%fpa31" }
-#endif /* defined SUPPORT_SUN_FPA */
+++ /dev/null
-/* Startup code for A/UX
- Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file. (The General Public License restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* This file is compiled three times to produce crt1.o, mcrt1.o, and
- maccrt1.o. The final two are created by defining MCRT1 and MACCRT1
- respectively. */
-
-#include <stdlib.h>
-#ifdef MCRT1
-#include <unistd.h>
-#include <mon.h>
-#endif
-
-/* Extern function declarations */
-
-extern void initfpu(void);
-extern void __istart(void);
-extern void __compatmode(void);
-extern void _cleanup(void);
-extern int main(int, char **, char **);
-extern void exit(int) __attribute__((noreturn));
-extern void _exit(int) __attribute__((noreturn));
-
-#ifdef MACCRT1
-extern void InitMac(void);
-#endif
-#ifdef MCRT1
-static void monitor_start(void);
-#endif
-
-/* Global variables */
-
-char **environ;
-char *__splimit; /* address of top of stack */
-
-
-/* Initialize system and run */
-
-void _start() __attribute__((noreturn));
-void _start()
-{
- register int *fp __asm__("%a6");
- register char *d0 __asm__("%d0");
- char **argv;
- int argc;
-
- __splimit = d0;
- argc = fp[1];
- argv = (char **)&fp[2];
- environ = &argv[argc+1];
-
- initfpu();
- __istart();
- __compatmode();
-
- atexit(_cleanup);
-#ifdef MCRT1
- monitor_start();
-#endif
-#ifdef MACCRT1
- InitMac();
-#endif
-
- exit(main(argc, argv, environ));
-}
-
-
-#ifdef MCRT1
-/* Start/Stop program monitor */
-
-extern void monitor(void *, void *, WORD *, int, int);
-
-static WORD *monitor_buffer;
-
-static void monitor_cleanup(void)
-{
- monitor(NULL, NULL, NULL, 0, 0);
- free(monitor_buffer);
-}
-
-static void monitor_start(void)
-{
- extern int etext;
- extern int stext __asm__(".text");
-
- /* Choice of buffer size should be "no more than a few times
- smaller than the program size" -- I don't believe that there
- are any (useful) functions smaller than two insns (4 bytes)
- so that is the scale factor used here */
- int len = (&etext - &stext + 1) / 4;
-
- monitor_buffer = (WORD *)calloc(len, sizeof(WORD));
- if (monitor_buffer == NULL)
- {
- static const char msg[] = "mcrt1: could not allocate monitor buffer\n";
- write(2, msg, sizeof(msg)-1);
- _exit(-1);
- }
-
- /* I'm not sure why the count cap at 600 -- but that is what A/UX does */
- monitor(&stext, &etext, monitor_buffer, len, 600);
-
- atexit(monitor_cleanup);
-}
-#endif /* MCRT1 */
+++ /dev/null
-/* More startup code for A/UX */
-
-#include "tconfig.h"
-
-#ifdef USE_BIN_AS
- file "crt2.s"
-
-/* The init section is used to support shared libraries */
- init
- global __istart
-
-__istart:
- link %fp,&-4
-#else
- .file "crt2.s"
-
-/* The init section is used to support shared libraries */
-.section .init, "x"
-.even
-.globl __istart
-
-__istart:
- link %fp,#-4
-
-#ifndef USE_COLLECT2
-/* The ctors and dtors sections are used to support COFF collection of
- c++ constructors and destructors */
-.section .ctors, "d"
-.even
-.globl __CTOR_LIST__
-
-__CTOR_LIST__:
- .long -1
-
-.section .dtors, "d"
-.even
-.globl __DTOR_LIST__
-
-__DTOR_LIST__:
- .long -1
-#endif /* USE_COLLECT2 */
-#endif /* USE_BIN_AS */
+++ /dev/null
-/* More startup code for A/UX */
-
-#include "tconfig.h"
-
-#ifdef USE_BIN_AS
- file "crtn.s"
-
- init
-
- unlk %fp
- rts
-#else
- .file "crtn.s"
-
-.section .init, "x"
- unlk %fp
- rts
-
-#ifndef USE_COLLECT2
-.section .ctors, "d"
- .long 0
-
-.section .dtors, "d"
- .long 0
-#endif /* USE_COLLECT2 */
-#endif /* USE_BIN_AS */
+++ /dev/null
-/* Generic atexit()
- Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file. (The General Public License restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Rather than come up with some ugly hack to make mcrt1 work, it is
- better to just go ahead and provide atexit(). */
-
-
-#include <stdlib.h>
-
-
-void exit(int) __attribute__((noreturn));
-void _exit(int) __attribute__((noreturn));
-void _cleanup(void);
-
-
-#define FNS_PER_BLOCK 32
-
-struct atexit_fn_block
-{
- struct atexit_fn_block *next;
- void (*fns[FNS_PER_BLOCK])(void);
- short used;
-};
-
-
-/* statically allocate the first block */
-static struct atexit_fn_block atexit_fns;
-static struct atexit_fn_block *current_block = &atexit_fns;
-
-
-int atexit(void (*fn)(void))
-{
- if (current_block->used >= FNS_PER_BLOCK)
- {
- struct atexit_fn_block *new_block =
- (struct atexit_fn_block *)malloc(sizeof(struct atexit_fn_block));
- if (new_block == NULL)
- return -1;
-
- new_block->used = 0;
- new_block->next = current_block;
- current_block = new_block;
- }
-
- current_block->fns[current_block->used++] = fn;
-
- return 0;
-}
-
-
-void exit(int status)
-{
- struct atexit_fn_block *block = current_block, *old_block;
- short i;
-
- while (1)
- {
- for (i = block->used; --i >= 0 ;)
- (*block->fns[i])();
- if (block == &atexit_fns)
- break;
- /* I know what you are thinking -- we are about to exit, why free?
- Because it is friendly to memory leak detectors, that's why. */
- old_block = block;
- block = block->next;
- free(old_block);
- }
-
- _exit(status);
-}
+++ /dev/null
-/* GLD link script for building mac-compatible executables */
-
-OUTPUT_FORMAT("coff-m68k")
-
-SEARCH_DIR(@tooldir@/lib);
-SEARCH_DIR(@libdir@);
-SEARCH_DIR(/lib);
-SEARCH_DIR(/usr/lib);
-SEARCH_DIR(@local_prefix@/lib);
-
-ENTRY(_start)
-
-SECTIONS
-{
- .lowmem 0 (DSECT) : {
- /usr/lib/low.o (.data)
- }
- .text 0x10000000 : {
- *(.text)
- *(.init)
- *(.fini)
- etext = .;
- _etext = .;
- }
- .data ALIGN(0x40000) : {
- *(.data)
- *(.ctors)
- *(.dtors)
- edata = .;
- _edata = .;
- }
- .bss : {
- *(.bss)
- *(COMMON)
- end = .;
- _end = .;
- }
-}
+++ /dev/null
-/* Profiling support code for A/UX
- Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file. (The General Public License restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* This routine is called at the beginning of functions compiled with -p
- or -pg. The A/UX libraries call mcount%, but gas cannot generate
- symbols with embedded percent signs. Previous ports of GCC to A/UX
- have done things like (1) assemble a stub routine with the native
- assembler, or (2) assemble a stub routine with gas and edit the object
- file. This solution has the advantage that it can interoperate with
- the A/UX version and can be used in an eventual port of glibc to A/UX. */
-
-#ifndef __GNUC__
-#error This file uses GNU C extensions
-#endif
-
-#include "tconfig.h"
-#include <mon.h>
-
-struct cnt *_countbase;
-
-#ifdef FUNCTION_PROFILER_SYMBOL
-void __mcount() __asm__(FUNCTION_PROFILER_SYMBOL);
-#endif
-
-void __mcount()
-{
- register long **pfncnt __asm__("%a0");
- register long *fncnt = *pfncnt;
-
- if (!fncnt)
- {
- struct cnt *newcnt = _countbase++;
- newcnt->fnpc = (char *)__builtin_return_address(0);
- *pfncnt = fncnt = &newcnt->mcnt;
- }
- *fncnt += 1;
-}
+++ /dev/null
-/* Definitions for Motorola 680x0 running A/UX using /bin/as
- Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define USE_BIN_AS
-
-#ifndef USE_COLLECT2
-#define USE_COLLECT2
-#endif
-
-#ifndef __ASSEMBLY__
-
-#include "m68k/sgs.h"
-
-#define ASM_SPEC "%{m68030:-68030 }%{m68040:-68040 }"
-
-/* Modify AT&T SGS assembler syntax */
-/* A/UX's as doesn't do dots in pseudo-ops */
-
-#define SDB_DEBUGGING_INFO
-
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-
-#undef INT_OP_GROUP
-#define INT_OP_GROUP INT_OP_NO_DOT
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP "\ttext"
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP "\tdata\t1"
-
-#undef SPACE_ASM_OP
-#define SPACE_ASM_OP "\tspace\t"
-
-#undef ALIGN_ASM_OP
-#define ALIGN_ASM_OP "\talign\t"
-
-#undef GLOBAL_ASM_OP
-#define GLOBAL_ASM_OP "\tglobal\t"
-
-#undef SWBEG_ASM_OP
-#define SWBEG_ASM_OP "\tswbeg\t"
-
-#undef SET_ASM_OP
-#define SET_ASM_OP "\tset\t"
-
-#undef ASM_PN_FORMAT
-#define ASM_PN_FORMAT "%s%%%d"
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "L%"
-
-#define ADDITIONAL_REGISTER_NAMES { {"%a6", 14}, {"%a7", 15} }
-
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\tcomm\t", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\tlcomm\t", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
- output_file_directive ((FILE), main_input_filename)
-
-#undef ASM_OUTPUT_SOURCE_FILENAME
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) \
-( fputs ("\tfile\t", (FILE)), \
- output_quoted_string ((FILE), (NAME)), \
- fputc ('\n', (FILE)) )
-
-#undef ASM_OUTPUT_CASE_FETCH
-#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
- asm_fprintf (file, "10(%Rpc,%s.", regname)
-
-#define SGS_NO_LI
-
-/* Random macros describing parts of SDB data. */
-
-#define PUT_SDB_SCL(a) \
- fprintf(asm_out_file, "\tscl\t%d%s", (a), SDB_DELIM)
-
-#define PUT_SDB_INT_VAL(a) \
- fprintf (asm_out_file, "\tval\t%d%s", (a), SDB_DELIM)
-
-#define PUT_SDB_VAL(a) \
-( fputs ("\tval\t", asm_out_file), \
- output_addr_const (asm_out_file, (a)), \
- fprintf (asm_out_file, SDB_DELIM))
-
-#define PUT_SDB_DEF(a) \
-do { fprintf (asm_out_file, "\tdef\t"); \
- ASM_OUTPUT_LABELREF (asm_out_file, a); \
- fprintf (asm_out_file, SDB_DELIM); } while (0)
-
-#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s%s", a, SDB_DELIM)
-
-#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file)
-
-#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o%s", a, SDB_DELIM)
-
-#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d%s", a, SDB_DELIM)
-
-#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t")
-
-#define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a)
-
-#define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d%s", a, SDB_DELIM)
-
-#define PUT_SDB_TAG(a) \
-do { fprintf (asm_out_file, "\ttag\t"); \
- ASM_OUTPUT_LABELREF (asm_out_file, a); \
- fprintf (asm_out_file, SDB_DELIM); } while (0)
-
-#define PUT_SDB_BLOCK_START(LINE) \
- fprintf (asm_out_file, \
- "\tdef\t~bb%s\tval\t~%s\tscl\t100%s\tline\t%d%s\tendef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_END(LINE) \
- fprintf (asm_out_file, \
- "\tdef\t~eb%s\tval\t~%s\tscl\t100%s\tline\t%d%s\tendef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_START(LINE) \
- fprintf (asm_out_file, \
- "\tdef\t~bf%s\tval\t~%s\tscl\t101%s\tline\t%d%s\tendef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_END(LINE) \
- fprintf (asm_out_file, \
- "\tdef\t~ef%s\tval\t~%s\tscl\t101%s\tline\t%d%s\tendef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_EPILOGUE_END(NAME) \
-do { fprintf (asm_out_file, "\tdef\t"); \
- ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
- fprintf (asm_out_file, \
- "%s\tval\t~%s\tscl\t-1%s\tendef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
-
-#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
- sprintf ((BUFFER), "~%dfake", (NUMBER));
-
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
- fprintf((FILE), "\tln\t%d\n", \
- (sdb_begin_function_line > 1 ? \
- (LINE) - sdb_begin_function_line : 1))
-
-#define ASM_MOV_INSN "mov.l"
-
-#define FUNCTION_PROFILER_SYMBOL "mcount%"
-
-#endif /* !__ASSEMBLY__ */
+++ /dev/null
-/* Definitions for Motorola 680x0 running A/UX using GAS
- Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define USE_GAS
-
-#ifndef __ASSEMBLY__
-
-#include "m68k/m68k.h"
-#include "m68k/coff.h"
-
-#define ASM_SPEC "%{m68000:-Am68000 }%{m68030:-Am68030 }%{m68040:-Am68040 }"
-
-/* Output #ident as a .ident. */
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
- fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-#ifdef USE_COLLECT2
-/* for the sake of link-level compatibility with /bin/as version */
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-#endif
-
-#define ADDITIONAL_REGISTER_NAMES { {"%fp", 14}, {"%a7", 15} }
-
-#define ASM_MOV_INSN "movel"
-
-#define FUNCTION_PROFILER_SYMBOL "__mcount"
-
-#endif /* !__ASSEMBLY__ */
+++ /dev/null
-/* Definitions for Motorola 680x0 running A/UX using GLD
- Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define USE_GNU_LD
-
-#ifndef __ASSEMBLY__
-
-#define LINK_SPEC \
-"%{p:-L/lib/libp -L/usr/lib/libp }%{pg:-L/lib/libp -L/usr/lib/libp }\
-%{smac:-T low.gld%s }"
-
-#endif /* !__ASSEMBLY__ */
+++ /dev/null
-/* Definitions for Motorola 680x0 running A/UX using /bin/ld
- Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define USE_BIN_LD
-
-#ifndef USE_COLLECT2
-#define USE_COLLECT2
-#endif
-
-#ifndef __ASSEMBLY__
-
-#define LINK_SPEC \
-"%{p:-L/lib/libp -L/usr/lib/libp }%{pg:-L/lib/libp -L/usr/lib/libp }\
-%{smac:low.ld%s }%{!smac:shlib.ld%s }"
-
-#define SWITCHES_NEED_SPACES "o"
-
-#endif /* !__ASSEMBLY__ */
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Convergent Technologies MiniFrame version,
- using GAS and binutils with COFF encapsulation.
-
- Written by Ronald Cole
-
- Because the MiniFrame's C compiler is so completely lobotomized,
- bootstrapping this is damn near impossible!
- Write to me for information on obtaining the binaries...
-
- bug reports to csusac!unify!rjc@ucdavis.edu
-
- Copyright (C) 1990 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "m68k/3b1g.h"
-
-/* Names to predefine in the preprocessor for this target machine. */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000 -Dmc68k -Dunix -Dctix -Asystem=unix -Acpu=m68k -Amachine=m68k"
-
-/* Where to look for robotussinized startfiles. */
-#undef STANDARD_STARTFILE_PREFIX
-#define STANDARD_STARTFILE_PREFIX "/usr/local/lib/gnu/"
-
-/* Generate calls to the MiniFrame's library (for speed). */
-#define DIVSI3_LIBCALL "ldiv"
-#define UDIVSI3_LIBCALL "uldiv"
-#define MODSI3_LIBCALL "lrem"
-#define UMODSI3_LIBCALL "ulrem"
-#define MULSI3_LIBCALL "lmul"
-#define UMULSI3_LIBCALL "ulmul"
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Bull DPX/2 200 and 300 systems (m68k, SysVr3).
- Copyright (C) 1987, 1993, 1994, 1995, 1996, 1999, 2000, 2002
- Free Software Foundation, Inc.
- Contributed by Frederic Pierresteguy (F.Pierresteguy@frcl.bull.fr).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-#ifndef USE_GAS
-#define MOTOROLA /* Use Motorola syntax rather than "MIT" */
-#define SGS_NO_LI /* Suppress jump table label usage */
-#define VERSADOS /* This is the name of the assembler we have */
-#endif
-
-#include "m68k/m68k.h"
-#include "svr3.h"
-
-#undef INT_OP_GROUP
-#define INT_OP_GROUP INT_OP_DC
-
-/* We use collect2 instead of ctors_section constructors. */
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-#undef DO_GLOBAL_CTORS_BODY
-
-/* Remove handling for a separate constant data section. We put
- constant data in text_section, which is the default. */
-#undef TARGET_ASM_SELECT_SECTION
-#undef EXTRA_SECTIONS
-#undef EXTRA_SECTION_FUNCTIONS
-#undef READONLY_DATA_SECTION_ASM_OP
-
-#define DPX2
-
-/* See m68k.h. 7 means 68020 with 68881.
- * We really have 68030 and 68882,
- * but this will get us going.
- */
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-#define OBJECT_FORMAT_COFF
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-/*
- * define all the things the compiler should
- */
-#ifdef ncl_mr
-# define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_mr=1 -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k"
-#else
-# ifdef ncl_el
-# define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_el -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k"
-# else
-# define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem=unix -Asystem=svr3 -Acpu=m68k -Amachine=m68k"
-# endif
-#endif
-
-#undef CPP_SPEC
-/*
- * you can't get a DPX/2 without a 68882 but allow it
- * to be ignored...
- */
-# define __HAVE_68881__ 1
-# define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ }"
-
-#undef DO_GLOBAL_CTORS_BODY /* don't use svr3.h version */
-#undef DO_GLOBAL_DTORS_BODY
-
-#ifndef USE_GAS
-/*
- * handle the native MOTOROLA VERSAdos assembler.
- */
-
-/* See m68k.h. 3 means 68020 with 68881 and no bitfield
- * bitfield instructions do not seem to work a clean way.
- */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_68881|MASK_68020)
-
-/* The native assembler doesn't support fmovecr. */
-#define NO_ASM_FMOVECR
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP "\tsection 10"
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP "\tsection 15"
-#define BSS_SECTION_ASM_OP "\tsection 14"
-
-
-/* Don't try using XFmode. */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-#undef ASM_OUTPUT_SOURCE_FILENAME
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, NA) \
- do { \
- fprintf (FILE, "\t.file\t"); \
- output_quoted_string (FILE, NA); \
- putc ('\n', FILE); \
- } while (0)
-
-/*
- * we don't seem to support any of:
- * .globl
- * .even
- * .align
- * .ascii
- */
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\tdcb.b %u,0\n", (SIZE))
-
-#undef GLOBAL_ASM_OP
-#define GLOBAL_ASM_OP "\txdef\t"
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG) >= 1) \
- fprintf (FILE, "\tds.w 0\n");
-
-
-#define STRING_LIMIT (0)
-#undef ASM_APP_ON
-#define ASM_APP_ON ""
-#undef ASM_APP_OFF
-#define ASM_APP_OFF ""
-/*
- * dc.b 'hello, world!'
- * dc.b 10,0
- * is how we have to output "hello, world!\n"
- */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(asm_out_file, p, thissize) \
- do { register int i, c, f=0, len=0; \
- for (i = 0; i < thissize; i++) { \
- c = p[i]; \
- if (c == '\'' || c < ' ' || c > 127) { \
- switch(f) { \
- case 0: /* need to output dc.b etc */ \
- fprintf(asm_out_file, "\tdc.b %d", c); \
- f=1; \
- break; \
- case 1: \
- fprintf(asm_out_file, ",%d", c); \
- break; \
- default: \
- /* close a string */ \
- fprintf(asm_out_file, "'\n\tdc.b %d", c); \
- f=1; \
- break; \
- } \
- } else { \
- switch(f) { \
- case 0: \
- fprintf(asm_out_file, "\tdc.b '%c", c); \
- f=2; \
- break; \
- case 2: \
- if (len >= 79) { \
- fprintf(asm_out_file, "'\n\tdc.b '%c", c); \
- len = 0; } \
- else \
- fprintf(asm_out_file, "%c", c); \
- break; \
- default: \
- len = 0; \
- fprintf(asm_out_file, "\n\tdc.b '%c", c); \
- f=2; \
- break; \
- } \
- } \
- len++; \
- } \
- if (f==2) \
- putc('\'', asm_out_file); \
- putc('\n', asm_out_file); } while (0)
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tmove.l (sp)+,%s\n", reg_names[REGNO])
-
-
-#define PUT_SDB_FUNCTION_START(LINE) \
- fprintf (asm_out_file, \
- "\t.def\t.bf%s\t.val\t*%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_END(LINE) \
- fprintf (asm_out_file, \
- "\t.def\t.ef%s\t.val\t*%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_START(LINE) \
- fprintf (asm_out_file, \
- "\t.def\t.bb%s\t.val\t*%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_END(LINE) \
- fprintf (asm_out_file, \
- "\t.def\t.eb%s\t.val\t*%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
- SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_EPILOGUE_END(NAME)
-
-/* Output type in decimal not in octal as done in sdbout.c */
-#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0%d%s", a, SDB_DELIM)
-
-/* Translate Motorola opcodes such as `jbeq'
- into VERSAdos opcodes such as `beq'.
- Change `fbeq' to `fbseq', `fbne' to `fbsneq'.
-*/
-
-#undef ASM_OUTPUT_OPCODE
-#define ASM_OUTPUT_OPCODE(FILE, PTR) \
-{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \
- { ++(PTR); \
- while (*(PTR) != ' ') \
- { putc (*(PTR), (FILE)); ++(PTR); } \
- } \
- else if ((PTR)[0] == 'f') \
- { \
- if (!strncmp ((PTR), "fbeq", 4)) \
- { fprintf ((FILE), "fbseq"); (PTR) += 4; } \
- else if (!strncmp ((PTR), "fbne", 4)) \
- { fprintf ((FILE), "fbsneq"); (PTR) += 4; } \
- } \
- else if ((PTR)[0] == 'b' && (PTR)[1] == 'f') \
- { \
- char *s; \
- if ((s = (char*)strchr ((PTR), '{'))) \
- while (*s != '}') { \
- if (*s == 'b') \
- /* hack, I replace it with R ie nothing */ \
- *s = '0'; \
- s++; } \
- } \
-}
-
-/* This is how to output an element of a case-vector that is absolute.
- (The 68000 does not use such vectors,
- but we must define this macro anyway.) */
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- asm_fprintf (FILE, "\tdc.l %LL%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative. */
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- asm_fprintf (FILE, "\tdc.w %LL%d-%LL%d\n", VALUE, REL)
-
-/* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to
- keep switch tables in the text section. */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Output a float value (represented as a C double) as an immediate operand.
- This macro is a 68k-specific macro. */
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
- do { \
- if (CODE == 'f') \
- { \
- char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
- asm_fprintf ((FILE), "%I%s", dstr); \
- } \
- else \
- { \
- long l; \
- REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
- if (sizeof (int) == sizeof (long)) \
- asm_fprintf ((FILE), "%I$%x", (int) l); \
- else \
- asm_fprintf ((FILE), "%I$%lx", l); \
- } \
- } while (0)
-
-/* Output a double value (represented as a C double) as an immediate operand.
- This macro is a 68k-specific macro. */
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
- do { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
- asm_fprintf (FILE, "%I%s", dstr); \
- } while (0)
-
-/* Note, long double immediate operands are not actually
- generated by m68k.md. */
-#undef ASM_OUTPUT_LONG_DOUBLE_OPERAND
-#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
- do { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
- asm_fprintf (FILE, "%I%s", dstr); \
- } while (0)
-
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
- do { \
- int align = exact_log2 (ROUNDED); \
- /*fprintf ((FILE), "\tsection 14\n"); */ \
- data_section (); \
- ASM_OUTPUT_ALIGN ((FILE), align) \
- ASM_OUTPUT_LABEL ((FILE), (NAME)); \
- fprintf ((FILE), "\tdcb.b %u,0\n", (ROUNDED)); \
- /* fprintf ((FILE), "\tsection 10\n"); */ \
- } while (0)
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-{ register rtx reg1, reg2, breg, ireg; \
- register rtx addr = ADDR; \
- rtx offset; \
- switch (GET_CODE (addr)) \
- { \
- case REG: \
- fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \
- break; \
- case PRE_DEC: \
- fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \
- break; \
- case POST_INC: \
- fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \
- break; \
- case PLUS: \
- reg1 = 0; reg2 = 0; \
- ireg = 0; breg = 0; \
- offset = 0; \
- if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \
- { \
- offset = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \
- { \
- offset = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- if (GET_CODE (addr) != PLUS) ; \
- else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \
- { \
- reg1 = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \
- { \
- reg1 = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- else if (GET_CODE (XEXP (addr, 0)) == MULT) \
- { \
- reg1 = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (GET_CODE (XEXP (addr, 1)) == MULT) \
- { \
- reg1 = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- else if (GET_CODE (XEXP (addr, 0)) == REG) \
- { \
- reg1 = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (GET_CODE (XEXP (addr, 1)) == REG) \
- { \
- reg1 = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \
- || GET_CODE (addr) == SIGN_EXTEND) \
- { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \
-/* for OLD_INDEXING \
- else if (GET_CODE (addr) == PLUS) \
- { \
- if (GET_CODE (XEXP (addr, 0)) == REG) \
- { \
- reg2 = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (GET_CODE (XEXP (addr, 1)) == REG) \
- { \
- reg2 = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- } \
- */ \
- if (offset != 0) { if (addr != 0) abort (); addr = offset; } \
- if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \
- || GET_CODE (reg1) == MULT)) \
- || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \
- { breg = reg2; ireg = reg1; } \
- else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \
- { breg = reg1; ireg = reg2; } \
- if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \
- { int scale = 1; \
- if (GET_CODE (ireg) == MULT) \
- { scale = INTVAL (XEXP (ireg, 1)); \
- ireg = XEXP (ireg, 0); } \
- if (GET_CODE (ireg) == SIGN_EXTEND) \
- fprintf (FILE, "(.L%d,pc,%s.w", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (XEXP (ireg, 0))]); \
- else \
- fprintf (FILE, "(.L%d,pc,%s.l", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (ireg)]); \
- if (scale != 1) fprintf (FILE, "*%d", scale); \
- putc (')', FILE); \
- break; } \
- if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF \
- && ! (flag_pic && breg == pic_offset_table_rtx)) \
- { \
- fprintf (FILE, "(.L%d,pc,%s.l", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (breg)]); \
- putc (')', FILE); \
- break; } \
- if (ireg != 0 || breg != 0) \
- { int scale = 1; \
- if (breg == 0) \
- abort (); \
- putc ('(', FILE); \
- if (addr != 0) \
- { \
- output_addr_const (FILE, addr); \
- putc (',', FILE); \
- } \
- fprintf (FILE, "%s", reg_names[REGNO (breg)]); \
- if (ireg != 0) \
- putc (',', FILE); \
- if (ireg != 0 && GET_CODE (ireg) == MULT) \
- { scale = INTVAL (XEXP (ireg, 1)); \
- ireg = XEXP (ireg, 0); } \
- if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \
- fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \
- else if (ireg != 0) \
- fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \
- if (scale != 1) fprintf (FILE, "*%d", scale); \
- putc (')', FILE); \
- break; \
- } \
- else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \
- { fprintf (FILE, "(.L%d,pc,%s.w)", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (reg1)]); \
- break; } \
- default: \
- if (GET_CODE (addr) == CONST_INT \
- && INTVAL (addr) < 0x8000 \
- && INTVAL (addr) >= -0x8000) \
- fprintf (FILE, "%d.w", INTVAL (addr)); \
- else \
- output_addr_const (FILE, addr); \
- }}
-
-
-#endif /* ! use gas */
+++ /dev/null
-/*
- * dpx2.ifile - for collectless G++ on Bull DPX/2
- *
- * Peter Schauer <Peter.Schauer@regent.e-technik.tu-muenchen.dbp.de>
- *
- * Install this file as $prefix/gcc-lib/dpx2/VERSION/gcc.ifile
- * and comment out the lines referring to COLLECT at the top
- * of Makefile before building GCC.
- *
- * This file has been tested with gcc-2.2.2 on a DPX/2 340
- * running BOS 2.00.45, if it doesn't work for you, stick
- * with collect.
- * --sjg
- */
-/*
- * Ifile to link with memory configured at 0.
- * BLOCK to an offset that leaves room for many headers ( the value
- * here allows for a file header, an outheader, and up to 11 section
- * headers on most systems.
- * BIND to an address that excludes page 0 from being mapped. The value
- * used for BLOCK should be or'd into this value. Here I'm setting BLOCK
- * to 0x200 and BIND to ( 0x100000 | value_used_for(BLOCK) )
- * If you are using shared libraries, watch that you don't overlap the
- * address ranges assigned for shared libs.
- *
- * GROUP BIND to a location in the next segment. Here, the only value
- * that you should change (I think) is that within NEXT, which I've set
- * to my hardware segment size. You can always use a larger size, but not
- * a smaller one.
- */
-SECTIONS
-{
- .text BIND(0x100200) BLOCK (0x200) :
- {
- /* plenty of room for headers */
- *(.init)
- *(.text)
- _vfork = _fork; /* I got tired of editing peoples sloppy code */
- *(.fini)
- }
- GROUP BIND( NEXT(0x100000) + (ADDR(.text) + (SIZEOF(.text)) % 0x1000)):
- {
- .data : {
- ___CTOR_LIST__ = . ;
- . += 4 ; /* leading NULL */
- *(.ctor)
- . += 4 ; /* trailing NULL */
- ___DTOR_LIST__ = . ;
- . += 4 ; /* leading NULL */
- *(.dtor)
- . += 4 ; /* trailing NULL */
- }
- .bss : { }
- }
-}
+++ /dev/null
-/* Definitions for Bull dpx/2 200 and 300 with gas
- using dbx-in-coff encapsulation.
- Copyright (C) 1992, 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-#include "m68k/dpx2g.h"
-
-/* Use STABS debugging information inside COFF. */
-#ifndef DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-#endif
-
-/* Let sbd debugging be the default. */
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
+++ /dev/null
-/*
- * dpx2g.h - Bull DPX/2 200 and 300 systems (m68k, SysVr3) with gas
- */
-
-#define USE_GAS
-#include "m68k/dpx2.h"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}\
- huge.o%s"
-
-/* Gas understands dollars in labels. */
-#undef NO_DOLLAR_IN_LABEL
-/* GAS does not understand .ident so don't output anything for #ident. */
-#undef ASM_OUTPUT_IDENT
-
-/* end of dpx2g.h */
+++ /dev/null
-/* Define target machine as an ISI 68000/68020 with no 68881. */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-#include "m68k/isi.h"
-
-/* Don't try using XFmode. */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
+++ /dev/null
-/* Definitions of target machine for GNU compiler. ISI 68000/68020 version.
- Intended only for use with GAS, and not ISI's assembler, which is buggy
- Copyright (C) 1988, 1996, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "m68k/m68k.h"
-
-/* See m68k.h. 7 means 68020 with 68881. */
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-#if TARGET_DEFAULT & MASK_68881
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
- This will control the use of inline 68881 insns in certain macros. */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}"
-
-/* If the 68881 is used, link must load libmc.a before libc.a. */
-
-#define LIB_SPEC "%{!msoft-float:%{!p:%{!pg:-lmc}}%{p:-lmc_p}%{pg:-lmc_p}} \
-%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
-
-#else
-/* Define __HAVE_68881__ in preprocessor if -m68881 is specified.
- This will control the use of inline 68881 insns in certain macros. */
-
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__}"
-
-/* If the 68881 is used, link must load libmc.a instead of libc.a */
-
-#define LIB_SPEC "%{m68881:%{!p:%{!pg:-lmc}}%{p:-lmc_p}%{pg:-lmc_p}} \
-%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
-#endif
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Dunix -Dmc68000 -Dis68k -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-
-/* This is BSD, so it wants DBX format. */
-
-#define DBX_DEBUGGING_INFO
-
-/* Override parts of m68k.h to fit the ISI 68k machine. */
-
-#undef FUNCTION_VALUE
-#undef LIBCALL_VALUE
-#undef FUNCTION_VALUE_REGNO_P
-#undef NEEDS_UNTYPED_CALL
-#undef ASM_FILE_START
-
-/* Every structure or union's size must be a multiple of 2 bytes. */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* If TARGET_68881, return SF and DF values in f0 instead of d0. */
-
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG ((MODE), ((TARGET_68881 && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0))
-
-/* 1 if N is a possible register number for a function value.
- D0 may be used, and F0 as well if -m68881 is specified. */
-
-#define FUNCTION_VALUE_REGNO_P(N) \
- ((N) == 0 || (TARGET_68881 && (N) == 16))
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
- more than one register. */
-
-#define NEEDS_UNTYPED_CALL 1
-
-/* Also output something to cause the correct _doprnt to be loaded. */
-#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n%s\n", TARGET_68881 ? ".globl fltused" : "")
+++ /dev/null
-/* Definitions for Motorola 680x0 running LynxOS, using Lynx's old as and ld.
- Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include <m68k/m68k.h>
-#include <m68k/coff.h>
-#include <lynx-ng.h>
-
-/* See m68k.h. 7 means 68020 with 68881. */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dmc68000 -DM68K -DLynx -DIBITS32 -Asystem=unix -Asystem=lynx -Acpu=m68k -Amachine=m68k"
-
-/* Provide required defaults for linker switches. */
-
-#undef LINK_SPEC
-#define LINK_SPEC "-P1000 %{msystem-v:-V} %{mcoff:-k}"
-
-/* Every structure or union's size must be a multiple of 2 bytes. */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
+++ /dev/null
-/* Definitions for Motorola 680x0 running LynxOS.
- Copyright (C) 1993, 1994, 1995, 1996, 1998, 1999, 2000
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include <m68k/m68k.h>
-#include <m68k/coff.h>
-
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-#undef ASM_OUTPUT_DESTRUCTOR
-
-#define BSS_SECTION_ASM_OP "\t.bss"
-
-#include <lynx.h>
-
-/* See m68k.h. 7 means 68020 with 68881. */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dmc68000 -DM68K -DLynx -DIBITS32 -Asystem=unix -Asystem=lynx -Acpu=m68k -Amachine=m68k"
-
-/* Every structure or union's size must be a multiple of 2 bytes. */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Lynx uses d2 and d3 as scratch registers. */
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0, \
- 1, 1, 0, 0, 0, 0, 0, 1, \
- 1, 1, 0, 0, 0, 0, 0, 0 }
-
-/* Return floating point values in a fp register. This make fp code a
- little bit faster. It also makes -msoft-float code incompatible with
- -m68881 code, so people have to be careful not to mix the two. */
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG ((MODE), \
- ((TARGET_68881 \
- && ((MODE) == SFmode || (MODE) == DFmode \
- || (MODE) == XFmode)) \
- ? 16 : 0))
-
-#undef FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (TARGET_68881 && (N) == 16))
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
+++ /dev/null
-/******************************************************************\
-* *
-* <math-68881.h> last modified: 18 May 1989. *
-* *
-* Copyright (C) 1989 by Matthew Self. *
-* You may freely distribute verbatim copies of this software *
-* provided that this copyright notice is retained in all copies. *
-* You may distribute modifications to this software under the *
-* conditions above if you also clearly note such modifications *
-* with their author and date. *
-* *
-* Note: errno is not set to EDOM when domain errors occur for *
-* most of these functions. Rather, it is assumed that the *
-* 68881's OPERR exception will be enabled and handled *
-* appropriately by the operating system. Similarly, overflow *
-* and underflow do not set errno to ERANGE. *
-* *
-* Send bugs to Matthew Self (self@bayes.arc.nasa.gov). *
-* *
-\******************************************************************/
-
-#include <errno.h>
-
-#undef HUGE_VAL
-#define HUGE_VAL \
-({ \
- double huge_val; \
- \
- __asm ("fmove%.d %#0x7ff0000000000000,%0" /* Infinity */ \
- : "=f" (huge_val) \
- : /* no inputs */); \
- huge_val; \
-})
-
-__inline static const double sin (double x)
-{
- double value;
-
- __asm ("fsin%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double cos (double x)
-{
- double value;
-
- __asm ("fcos%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double tan (double x)
-{
- double value;
-
- __asm ("ftan%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double asin (double x)
-{
- double value;
-
- __asm ("fasin%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double acos (double x)
-{
- double value;
-
- __asm ("facos%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double atan (double x)
-{
- double value;
-
- __asm ("fatan%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double atan2 (double y, double x)
-{
- double pi, pi_over_2;
-
- __asm ("fmovecr%.x %#0,%0" /* extended precision pi */
- : "=f" (pi)
- : /* no inputs */ );
- __asm ("fscale%.b %#-1,%0" /* no loss of accuracy */
- : "=f" (pi_over_2)
- : "0" (pi));
- if (x > 0)
- {
- if (y > 0)
- {
- if (x > y)
- return atan (y / x);
- else
- return pi_over_2 - atan (x / y);
- }
- else
- {
- if (x > -y)
- return atan (y / x);
- else
- return - pi_over_2 - atan (x / y);
- }
- }
- else
- {
- if (y > 0)
- {
- if (-x > y)
- return pi + atan (y / x);
- else
- return pi_over_2 - atan (x / y);
- }
- else
- {
- if (-x > -y)
- return - pi + atan (y / x);
- else if (y < 0)
- return - pi_over_2 - atan (x / y);
- else
- {
- double value;
-
- errno = EDOM;
- __asm ("fmove%.d %#0x7fffffffffffffff,%0" /* quiet NaN */
- : "=f" (value)
- : /* no inputs */);
- return value;
- }
- }
- }
-}
-
-__inline static const double sinh (double x)
-{
- double value;
-
- __asm ("fsinh%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double cosh (double x)
-{
- double value;
-
- __asm ("fcosh%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double tanh (double x)
-{
- double value;
-
- __asm ("ftanh%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double atanh (double x)
-{
- double value;
-
- __asm ("fatanh%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double exp (double x)
-{
- double value;
-
- __asm ("fetox%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double expm1 (double x)
-{
- double value;
-
- __asm ("fetoxm1%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double log (double x)
-{
- double value;
-
- __asm ("flogn%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double log1p (double x)
-{
- double value;
-
- __asm ("flognp1%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double log10 (double x)
-{
- double value;
-
- __asm ("flog10%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double sqrt (double x)
-{
- double value;
-
- __asm ("fsqrt%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double pow (const double x, const double y)
-{
- if (x > 0)
- return exp (y * log (x));
- else if (x == 0)
- {
- if (y > 0)
- return 0.0;
- else
- {
- double value;
-
- errno = EDOM;
- __asm ("fmove%.d %#0x7fffffffffffffff,%0" /* quiet NaN */
- : "=f" (value)
- : /* no inputs */);
- return value;
- }
- }
- else
- {
- double temp;
-
- __asm ("fintrz%.x %1,%0"
- : "=f" (temp) /* integer-valued float */
- : "f" (y));
- if (y == temp)
- {
- int i = (int) y;
-
- if ((i & 1) == 0) /* even */
- return exp (y * log (x));
- else
- return - exp (y * log (x));
- }
- else
- {
- double value;
-
- errno = EDOM;
- __asm ("fmove%.d %#0x7fffffffffffffff,%0" /* quiet NaN */
- : "=f" (value)
- : /* no inputs */);
- return value;
- }
- }
-}
-
-__inline static const double fabs (double x)
-{
- double value;
-
- __asm ("fabs%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- return value;
-}
-
-__inline static const double ceil (double x)
-{
- int rounding_mode, round_up;
- double value;
-
- __asm volatile ("fmove%.l %%fpcr,%0"
- : "=dm" (rounding_mode)
- : /* no inputs */ );
- round_up = rounding_mode | 0x30;
- __asm volatile ("fmove%.l %0,%%fpcr"
- : /* no outputs */
- : "dmi" (round_up));
- __asm volatile ("fint%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- __asm volatile ("fmove%.l %0,%%fpcr"
- : /* no outputs */
- : "dmi" (rounding_mode));
- return value;
-}
-
-__inline static const double floor (double x)
-{
- int rounding_mode, round_down;
- double value;
-
- __asm volatile ("fmove%.l %%fpcr,%0"
- : "=dm" (rounding_mode)
- : /* no inputs */ );
- round_down = (rounding_mode & ~0x10)
- | 0x20;
- __asm volatile ("fmove%.l %0,%%fpcr"
- : /* no outputs */
- : "dmi" (round_down));
- __asm volatile ("fint%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- __asm volatile ("fmove%.l %0,%%fpcr"
- : /* no outputs */
- : "dmi" (rounding_mode));
- return value;
-}
-
-__inline static const double rint (double x)
-{
- int rounding_mode, round_nearest;
- double value;
-
- __asm volatile ("fmove%.l %%fpcr,%0"
- : "=dm" (rounding_mode)
- : /* no inputs */ );
- round_nearest = rounding_mode & ~0x30;
- __asm volatile ("fmove%.l %0,%%fpcr"
- : /* no outputs */
- : "dmi" (round_nearest));
- __asm volatile ("fint%.x %1,%0"
- : "=f" (value)
- : "f" (x));
- __asm volatile ("fmove%.l %0,%%fpcr"
- : /* no outputs */
- : "dmi" (rounding_mode));
- return value;
-}
-
-__inline static const double fmod (double x, double y)
-{
- double value;
-
- __asm ("fmod%.x %2,%0"
- : "=f" (value)
- : "0" (x),
- "f" (y));
- return value;
-}
-
-__inline static const double drem (double x, double y)
-{
- double value;
-
- __asm ("frem%.x %2,%0"
- : "=f" (value)
- : "0" (x),
- "f" (y));
- return value;
-}
-
-__inline static const double scalb (double x, int n)
-{
- double value;
-
- __asm ("fscale%.l %2,%0"
- : "=f" (value)
- : "0" (x),
- "dmi" (n));
- return value;
-}
-
-__inline static double logb (double x)
-{
- double exponent;
-
- __asm ("fgetexp%.x %1,%0"
- : "=f" (exponent)
- : "f" (x));
- return exponent;
-}
-
-__inline static const double ldexp (double x, int n)
-{
- double value;
-
- __asm ("fscale%.l %2,%0"
- : "=f" (value)
- : "0" (x),
- "dmi" (n));
- return value;
-}
-
-__inline static double frexp (double x, int *exp)
-{
- double float_exponent;
- int int_exponent;
- double mantissa;
-
- __asm ("fgetexp%.x %1,%0"
- : "=f" (float_exponent) /* integer-valued float */
- : "f" (x));
- int_exponent = (int) float_exponent;
- __asm ("fgetman%.x %1,%0"
- : "=f" (mantissa) /* 1.0 <= mantissa < 2.0 */
- : "f" (x));
- if (mantissa != 0)
- {
- __asm ("fscale%.b %#-1,%0"
- : "=f" (mantissa) /* mantissa /= 2.0 */
- : "0" (mantissa));
- int_exponent += 1;
- }
- *exp = int_exponent;
- return mantissa;
-}
-
-__inline static double modf (double x, double *ip)
-{
- double temp;
-
- __asm ("fintrz%.x %1,%0"
- : "=f" (temp) /* integer-valued float */
- : "f" (x));
- *ip = temp;
- return x - temp;
-}
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler. SONY NEWS-OS 4 version.
- Copyright (C) 1987, 1989, 1993, 1994, 1996, 1997, 1998, 1999
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifndef USE_GAS
-/* This controls conditionals in m68k.h. */
-#define MOTOROLA /* Use Motorola syntax rather than "MIT" */
-#define SGS_NO_LI /* Suppress jump table label usage */
-#endif
-
-#define NEWS
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-
-#include "m68k/m68k.h"
-
-/* See m68k.h. 7 means 68020 with 68881. */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
- This will control the use of inline 68881 insns in certain macros. */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}"
-
-/* Names to predefine in the preprocessor for this target machine. */
-/* These are the ones defined by Sony, plus mc68000 for uniformity with
- GCC on other 68000 systems. */
-
-#ifdef MOTOROLA
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews700 -D__motorola__ -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#else
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews700 -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#endif
-
-/* These conditionals tested for different submodels,
- but they were incorrect since they tested the host rather than the target.
- The choice of model shouldn't actually matter. */
-
-#if 0
-#ifdef news800
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews800 -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#endif
-#ifdef news900
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews900 -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#endif
-#ifdef news1500
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1500 -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#endif
-#ifdef news1700
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1700 -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#endif
-#ifdef news1800
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1800 -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#endif
-#ifdef news1900
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1900 -Asystem=unix -Asystem=bsd -Acpu=m68k -Amachine=m68k"
-#endif
-#endif
-
-/* Link with libg.a when debugging, for dbx's sake. */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* This is BSD, so it wants DBX format. */
-
-#define DBX_DEBUGGING_INFO
-
-#if 0
-/* This is to be compatible with types.h.
- It was found to be necessary with Newsos 3. */
-
-#define SIZE_TYPE "long int"
-#endif
-\f
-/* Override parts of m68k.h to fit Sony's assembler syntax. */
-
-#undef BIGGEST_ALIGNMENT
-#undef CALL_USED_REGISTERS
-#undef FUNCTION_VALUE
-#undef LIBCALL_VALUE
-#undef FUNCTION_PROFILER
-
-#ifdef MOTOROLA
-#undef REGISTER_NAMES
-#undef ASM_OUTPUT_REG_PUSH
-#undef ASM_OUTPUT_REG_POP
-#undef ASM_OUTPUT_SKIP
-#undef ASM_FORMAT_PRIVATE_NAME
-#endif
-
-#undef ASM_OUTPUT_ALIGN
-
-/* There is no point aligning anything to a rounder boundary than this. */
-#define BIGGEST_ALIGNMENT 32
-
-/* A bitfield declared as `int' forces `int' alignment for the struct. */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* NEWS makes d2, d3, fp2 and fp3 unsaved registers, unlike the Sun system. */
-
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0, \
- 1, 1, 0, 0, 0, 0, 0, 1, \
- 1, 1, 1, 1, 0, 0, 0, 0}
-
-/* NEWS returns floats and doubles in fp0, not d0/d1. */
-
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG ((MODE), \
- ((TARGET_68881 \
- && ((MODE) == SFmode || (MODE) == DFmode \
- || (MODE) == XFmode)) \
- ? 16 : 0))
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- fprintf (FILE, "\t.align %d\n", (LOG))
-\f
-#ifdef MOTOROLA
-
-#define FUNCTION_PROFILER(FILE, LABEL_NO) \
- fprintf (FILE, "\tmove.l #LP%d,d0\n\tjsr mcount\n", (LABEL_NO));
-
-/* Difference from m68k.h is in `fp' instead of `a6'. */
-
-#define REGISTER_NAMES \
-{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
- "a0", "a1", "a2", "a3", "a4", "a5", "fp", "sp", \
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7"}
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tmove.l (sp)+,%s\n", reg_names[REGNO])
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\t.space %u\n", (SIZE))
-
-#if 0
-/* The NEWS assembler in version 3.4 complains about fmove.d, but this
- macro proved not to work right. 3.4 is old, so forget about it. */
-#define ASM_OUTPUT_OPCODE(FILE, STRING) \
-{ \
- if (!strncmp (STRING, "fmove.d", 7) \
- && CONSTANT_P (operands[1])) \
- { \
- fprintf (FILE, "fmove.x"); \
- STRING += 7; \
- } \
-}
-#endif
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 13), \
- sprintf ((OUTPUT), "%s$$$%d", (NAME), (LABELNO)))
-
-/* Output a float value (represented as a C double) as an immediate operand.
- This macro is a 68k-specific macro. */
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
- do { \
- if (CODE == 'f') \
- { \
- char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.9e", dstr); \
- if (REAL_VALUE_ISINF (VALUE) || REAL_VALUE_ISNAN (VALUE)) \
- { \
- if (REAL_VALUE_NEGATIVE (VALUE)) \
- fprintf (FILE, "#0f-99e999"); \
- else \
- fprintf (FILE, "#0f99e999"); \
- } \
- else if (REAL_VALUE_MINUS_ZERO (VALUE)) \
- fprintf (FILE, "#0f-0.0"); \
- else \
- fprintf (FILE, "#0f%s", dstr); \
- } \
- else \
- { \
- long l; \
- REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
- fprintf (FILE, "#0x%lx", l); \
- } \
- } while (0)
-
-/* Output a double value (represented as a C double) as an immediate operand.
- This macro is a 68k-specific macro. */
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
- do { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr ); \
- if (REAL_VALUE_ISINF (VALUE) || REAL_VALUE_ISNAN (VALUE)) \
- { \
- if (REAL_VALUE_NEGATIVE (VALUE)) \
- fprintf (FILE, "#0d-99e999"); \
- else \
- fprintf (FILE, "#0d99e999"); \
- } \
- else if (REAL_VALUE_MINUS_ZERO (VALUE)) \
- fprintf (FILE, "#0d-0.0"); \
- else \
- fprintf (FILE, "#0d%s", dstr); \
- } while (0)
-
-/* Note, long double immediate operands are not actually
- generated by m68k.md. */
-#undef ASM_OUTPUT_LONG_DOUBLE_OPERAND
-#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
- do { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
- asm_fprintf (FILE, "%I0r%s", dstr); \
- } while (0)
-
-#if 0
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE) \
-{ if (CODE == '.') fprintf (FILE, "."); \
- else if (CODE == '#') fprintf (FILE, "#"); \
- else if (CODE == '-') fprintf (FILE, "-(sp)"); \
- else if (CODE == '+') fprintf (FILE, "(sp)+"); \
- else if (CODE == '@') fprintf (FILE, "(sp)"); \
- else if (CODE == '!') fprintf (FILE, "fpcr"); \
- else if (CODE == '$') {if (TARGET_68040_ONLY) fprintf (FILE, "s");} \
- else if (CODE == '&') {if (TARGET_68040_ONLY) fprintf (FILE, "d");} \
- else if (CODE == '/') \
- ; \
- else if (GET_CODE (X) == REG) \
- fprintf (FILE, "%s", reg_names[REGNO (X)]); \
- else if (GET_CODE (X) == MEM) \
- output_address (XEXP (X, 0)); \
- else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
- { REAL_VALUE_TYPE r; \
- REAL_VALUE_FROM_CONST_DOUBLE (r, X); \
- if (CODE == 'f') \
- { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL (r, "%.9e", dstr); \
- if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r)) { \
- if (REAL_VALUE_NEGATIVE (r)) \
- fprintf (FILE, "#0f-99e999"); \
- else \
- fprintf (FILE, "#0f99e999"); } \
- else if (REAL_VALUE_MINUS_ZERO (r)) \
- fprintf (FILE, "#0f-0.0"); \
- else \
- fprintf (FILE, "#0f%s", dstr); \
- } \
- else \
- { long l; \
- REAL_VALUE_TO_TARGET_SINGLE (r, l); \
- fprintf (FILE, "#0x%lx", l); \
- }} \
- else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \
- { REAL_VALUE_TYPE r; \
- REAL_VALUE_FROM_CONST_DOUBLE (r, X); \
- ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); } \
- else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \
- { REAL_VALUE_TYPE r; char dstr[30]; \
- REAL_VALUE_FROM_CONST_DOUBLE (r, X); \
- REAL_VALUE_TO_DECIMAL (r, "%.20e", dstr ); \
- if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r)) { \
- if (REAL_VALUE_NEGATIVE (r)) \
- fprintf (FILE, "#0d-99e999"); \
- else \
- fprintf (FILE, "#0d99e999"); } \
- else if (REAL_VALUE_MINUS_ZERO (r)) \
- fprintf (FILE, "#0d-0.0"); \
- else \
- fprintf (FILE, "#0d%s", dstr); } \
- else if (CODE == 'b') output_addr_const (FILE, X); \
- else { putc ('#', FILE); output_addr_const (FILE, X); }}
-#endif
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-{ register rtx reg1, reg2, breg, ireg; \
- register rtx addr = ADDR; \
- rtx offset; \
- switch (GET_CODE (addr)) \
- { \
- case REG: \
- fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \
- break; \
- case PRE_DEC: \
- fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \
- break; \
- case POST_INC: \
- fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \
- break; \
- case PLUS: \
- reg1 = 0; reg2 = 0; \
- ireg = 0; breg = 0; \
- offset = 0; \
- if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \
- { \
- offset = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \
- { \
- offset = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- if (GET_CODE (addr) != PLUS) ; \
- else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \
- { \
- reg1 = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \
- { \
- reg1 = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- else if (GET_CODE (XEXP (addr, 0)) == MULT) \
- { \
- reg1 = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (GET_CODE (XEXP (addr, 1)) == MULT) \
- { \
- reg1 = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- else if (GET_CODE (XEXP (addr, 0)) == REG) \
- { \
- reg1 = XEXP (addr, 0); \
- addr = XEXP (addr, 1); \
- } \
- else if (GET_CODE (XEXP (addr, 1)) == REG) \
- { \
- reg1 = XEXP (addr, 1); \
- addr = XEXP (addr, 0); \
- } \
- if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \
- || GET_CODE (addr) == SIGN_EXTEND) \
- { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \
- if (offset != 0) { if (addr != 0) abort (); addr = offset; } \
- if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \
- || GET_CODE (reg1) == MULT)) \
- || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \
- { breg = reg2; ireg = reg1; } \
- else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \
- { breg = reg1; ireg = reg2; } \
- if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \
- { int scale = 1; \
- if (GET_CODE (ireg) == MULT) \
- { scale = INTVAL (XEXP (ireg, 1)); \
- ireg = XEXP (ireg, 0); } \
- if (GET_CODE (ireg) == SIGN_EXTEND) \
- fprintf (FILE, "(L%d.b,pc,%s.w", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (XEXP (ireg, 0))]); \
- else \
- fprintf (FILE, "(L%d.b,pc,%s.l", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (ireg)]); \
- if (scale != 1) fprintf (FILE, "*%d", scale); \
- putc (')', FILE); \
- break; } \
- if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \
- { fprintf (FILE, "(L%d.b,pc,%s.l", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (breg)]); \
- putc (')', FILE); \
- break; } \
- if (ireg != 0 || breg != 0) \
- { int scale = 1; \
- if (breg == 0) \
- abort (); \
- if (addr && GET_CODE (addr) == LABEL_REF) abort (); \
- fprintf (FILE, "("); \
- if (addr != 0) { \
- output_addr_const (FILE, addr); \
- putc (',', FILE); } \
- fprintf (FILE, "%s", reg_names[REGNO (breg)]); \
- if (ireg != 0) \
- putc (',', FILE); \
- if (ireg != 0 && GET_CODE (ireg) == MULT) \
- { scale = INTVAL (XEXP (ireg, 1)); \
- ireg = XEXP (ireg, 0); } \
- if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \
- fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \
- else if (ireg != 0) \
- fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \
- if (scale != 1) fprintf (FILE, "*%d", scale); \
- putc (')', FILE); \
- break; \
- } \
- else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \
- { fprintf (FILE, "(L%d.b,pc,%s.l)", \
- CODE_LABEL_NUMBER (XEXP (addr, 0)), \
- reg_names[REGNO (reg1)]); \
- break; } \
- default: \
- if (GET_CODE (addr) == CONST_INT \
- && INTVAL (addr) < 0x8000 \
- && INTVAL (addr) >= -0x8000) \
- fprintf (FILE, "%d.w", INTVAL (addr)); \
- else \
- output_addr_const (FILE, addr); \
- }}
-
-#else /* Using GAS, which uses the MIT assembler syntax, like a Sun. */
-
-#define FUNCTION_PROFILER(FILE, LABEL_NO) \
- fprintf (FILE, "\tmovl #LP%d,d0\n\tjsr mcount\n", (LABEL_NO));
-
-#endif /* MOTOROLA */
+++ /dev/null
-#include "m68k/news.h"
-
-/* This is to be compatible with types.h.
- It was found to be necessary with Newsos 3. */
-
-#define SIZE_TYPE "long int"
+++ /dev/null
-#include "m68k/newsgas.h"
-
-/* This is to be compatible with types.h.
- It was found to be necessary with Newsos 3. */
-
-#define SIZE_TYPE "long int"
+++ /dev/null
-/* In Sony versions before 3.0, use the GNU Assembler, because the
- system's assembler has no way to assemble the difference of two
- labels for the displacement in a switch-dispatch instruction. */
-
-#define USE_GAS
-
-/* This is the assembler directive to equate two values. */
-
-#undef SET_ASM_OP
-#define SET_ASM_OP "\t.set\t"
-
-/* This is how we tell the assembler that a symbol is weak. */
-
-#undef ASM_WEAKEN_LABEL
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
- do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
- fputc ('\n', FILE); } while (0)
-
-#include "m68k/news.h"
+++ /dev/null
-/* Target definitions for GNU compiler for mc680x0 running NeXTSTEP
- Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998, 1999
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "m68k/m68k.h"
-#include "nextstep.h"
-
-/* See m68k.h. 0407 means 68040 (or 68030 or 68020, with 68881/2). */
-
-#define TARGET_DEFAULT (MASK_68040|MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-
-#undef STACK_BOUNDARY
-#define STACK_BOUNDARY 32
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dm68k -DNeXT -Dunix -D__MACH__ -D__BIG_ENDIAN__ -D__ARCHITECTURE__=\"m68k\" -Asystem=unix -Asystem=mach -Acpu=m68k -Amachine=m68k -D_NEXT_SOURCE"
-
-/* Every structure or union's size must be a multiple of 2 bytes.
- (Why isn't this in m68k.h?) */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#ifdef REAL_VALUE_TO_TARGET_SINGLE
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
- do { \
- long hex; \
- REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex); \
- fprintf (FILE, "#0%c%lx", (CODE) == 'f' ? 'b' : 'x', hex); \
- } while (0)
-#else
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
- do{ \
- if (CODE != 'f') \
- { \
- long l; \
- REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
- if (sizeof (int) == sizeof (long)) \
- asm_fprintf ((FILE), "%I0x%x", (int) l); \
- else \
- asm_fprintf ((FILE), "%I0x%lx", l); \
- } \
- else if (REAL_VALUE_ISINF (VALUE)) \
- { \
- if (REAL_VALUE_NEGATIVE (VALUE)) \
- fprintf (FILE, "#0r-99e999"); \
- else \
- fprintf (FILE, "#0r99e999"); \
- } \
- else \
- { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr); \
- fprintf (FILE, "#0r%s", dstr); \
- } \
- } while (0)
-#endif
-
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#ifdef REAL_VALUE_TO_TARGET_DOUBLE
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
- do { \
- long hex[2]; \
- REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex); \
- fprintf (FILE, "#0b%lx%08lx", hex[0], hex[1]); \
- } while (0)
-#else
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
- do { if (REAL_VALUE_ISINF (VALUE)) \
- { \
- if (REAL_VALUE_NEGATIVE (VALUE)) \
- fprintf (FILE, "#0r-99e999"); \
- else \
- fprintf (FILE, "#0r99e999"); \
- } \
- else \
- { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", dstr); \
- fprintf (FILE, "#0r%s", dstr); \
- } \
- } while (0)
-#endif
-
-/* We do not define JUMP_TABLES_IN_TEXT_SECTION, since we wish to keep
- the text section pure. There is no point in addressing the jump
- tables using pc relative addressing, since they are not in the text
- section, so we undefine CASE_VECTOR_PC_RELATIVE. This also
- causes the compiler to use absolute addresses in the jump table,
- so we redefine CASE_VECTOR_MODE to be SImode. */
-
-#undef CASE_VECTOR_MODE
-#define CASE_VECTOR_MODE SImode
-#undef CASE_VECTOR_PC_RELATIVE
-
-/* Make sure jump tables have the same alignment as other pointers. */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
-{ ASM_OUTPUT_ALIGN (FILE, 1); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* Don't treat addresses involving labels differently from symbol names.
- Previously, references to labels generated pc-relative addressing modes
- while references to symbol names generated absolute addressing modes. */
-
-#undef GO_IF_INDEXABLE_BASE
-#define GO_IF_INDEXABLE_BASE(X, ADDR) \
-{ if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
-
-/* This accounts for the return pc and saved fp on the m68k. */
-
-#define OBJC_FORWARDING_STACK_OFFSET 8
-#define OBJC_FORWARDING_MIN_OFFSET 8
-
-/* FINALIZE_TRAMPOLINE enables executable stack. The
- __enable_execute_stack also clears the insn cache. */
-
-#undef FINALIZE_TRAMPOLINE
-#define FINALIZE_TRAMPOLINE(TRAMP) \
- emit_library_call(gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), \
- 0, VOIDmode, 1, memory_address (SImode, (TRAMP)), Pmode)
-
-/* A C expression used to clear the instruction cache from
- address BEG to address END. On NeXTSTEP this i a system trap. */
-
-#define CLEAR_INSN_CACHE(BEG, END) \
- asm volatile ("trap #2")
-
-/* GCC is the primary compiler for NeXTSTEP, so we don't need this. */
-#undef PCC_STATIC_STRUCT_RETURN
+++ /dev/null
-/* Target definitions for GNU compiler for mc680x0 running NeXTSTEP 2.1
- Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994
- Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Changed for NeXTStep2.1, Ch. Kranz, 2/94, 3/94 */
-
-#include "m68k/next.h"
-#include "nextstep21.h"
-
-/* for #include <mach.h> in libgcc2.c */
-#define NeXTStep21
-
-/* called from m68k.c line 1881 */
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
- do{ \
- if (CODE != 'f') \
- { \
- long l; \
- REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
- if (sizeof (int) == sizeof (long)) \
- asm_fprintf ((FILE), "%I0x%x", (int) l); \
- else \
- asm_fprintf ((FILE), "%I0x%lx", l); \
- } \
- else if (REAL_VALUE_ISINF (VALUE)) \
- { \
- if (REAL_VALUE_NEGATIVE (VALUE)) \
- fprintf (FILE, "#0r-99e999"); \
- else \
- fprintf (FILE, "#0r99e999"); \
- } \
- else \
- { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr); \
- fprintf (FILE, "#0r%s", dstr); \
- } \
- } while (0)
-
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
- do { if (REAL_VALUE_ISINF (VALUE)) \
- { \
- if (REAL_VALUE_NEGATIVE (VALUE)) \
- fprintf (FILE, "#0r-99e999"); \
- else \
- fprintf (FILE, "#0r99e999"); \
- } \
- else \
- { char dstr[30]; \
- REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", dstr); \
- fprintf (FILE, "#0r%s", dstr); \
- } \
- } while (0)
-
+++ /dev/null
-/* Definitions for rtems targeting a Motorola m68k using coff.
- Copyright (C) 1996, 1997, 2000, 2002 Free Software Foundation, Inc.
- Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Specify predefined symbols in preprocessor. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000 -D__rtems__ \
- -Asystem=rtems -Acpu=mc68000 -Acpu=m68k -Amachine=m68k"
+++ /dev/null
-# Makefile additions for A/UX
-
-LIB2FUNCS_EXTRA=aux-mcount.c aux-exit.c
-
-FIXPROTO_DEFINES=-D_POSIX_SOURCE
-
-# Needed to support builds for multiple versions of A/UX
-# LDFLAGS=-static
-
-# Make sure we get the right assembler by letting gcc choose
-AS = $(GCC_FOR_TARGET) -xassembler-with-cpp -D__ASSEMBLY__ $(INCLUDES) -c
-
-aux-mcount.c: $(srcdir)/config/m68k/aux-mcount.c
- cp $(srcdir)/config/m68k/aux-mcount.c aux-mcount.c
-
-aux-exit.c: $(srcdir)/config/m68k/aux-exit.c
- cp $(srcdir)/config/m68k/aux-exit.c aux-exit.c
-
-crt1.o: $(srcdir)/config/m68k/aux-crt1.c $(GCC_PASSES)
- $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) $(INCLUDES) -o crt1.o -c \
- -fno-omit-frame-pointer $(srcdir)/config/m68k/aux-crt1.c
-
-mcrt1.o: $(srcdir)/config/m68k/aux-crt1.c $(GCC_PASSES)
- $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) $(INCLUDES) -o mcrt1.o -c \
- -fno-omit-frame-pointer -DMCRT1 $(srcdir)/config/m68k/aux-crt1.c
-
-maccrt1.o: $(srcdir)/config/m68k/aux-crt1.c $(GCC_PASSES)
- $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) $(INCLUDES) -o maccrt1.o -c \
- -fno-omit-frame-pointer -DMACCRT1 $(srcdir)/config/m68k/aux-crt1.c
-
-crt2.o: $(srcdir)/config/m68k/aux-crt2.asm $(GCC_PASSES)
- $(AS) -o crt2.o $(srcdir)/config/m68k/aux-crt2.asm
-
-crtn.o: $(srcdir)/config/m68k/aux-crtn.asm $(GCC_PASSES)
- $(AS) -o crtn.o $(srcdir)/config/m68k/aux-crtn.asm
-
-low.gld: $(srcdir)/config/m68k/aux-low.gld
- sed -e 's|@libdir@|$(libdir)|' -e 's|@tooldir@|$(tooldir)|' \
- -e 's|@local_prefix@|$(local_prefix)|' \
- $(srcdir)/config/m68k/aux-low.gld > tmp-low.gld
- mv tmp-low.gld low.gld
+++ /dev/null
-LIB1ASMSRC = m68k/lb1sf68.asm
-LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \
- _double _float _floatex \
- _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \
- _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2
+++ /dev/null
-# Specify other dirs of system header files to be fixed.
-OTHER_FIXINCLUDES_DIRS= /LocalDeveloper/Headers
-
-# <limits.h> is sometimes in /usr/include/ansi/limits.h.
-LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h -o -f $(SYSTEM_HEADER_DIR)/ansi/limits.h ]
-
-nextstep.o: $(srcdir)/config/nextstep.c $(CONFIG_H) flags.h tree.h
- $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
+++ /dev/null
-# f771 is so big, we need to tell linker on m68k-next-nextstep* to
-# make enough room for it.
-BOOT_LDFLAGS=-segaddr __DATA 6000000
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Motorola m88100 running DG/UX.
- Copyright (C) 1988, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002
- Free Software Foundation, Inc.
- Contributed by Michael Tiemann (tiemann@mcc.com)
- Currently maintained by (gcc@dg-rtp.dg.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* You're not seeing double! To transition to dwarf debugging, both are
- supported. The option -msvr4 specifies elf. With these combinations,
- -g means dwarf. */
-/* DWARF_DEBUGGING_INFO defined in svr4.h. */
-#undef SDB_DEBUGGING_INFO
-#define SDB_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE \
- (TARGET_SVR4 ? DWARF_DEBUG : SDB_DEBUG)
-
-#ifndef NO_BUGS
-#define AS_BUG_IMMEDIATE_LABEL
-/* The DG/UX 4.30 assembler doesn't accept the symbol `fcr63'. */
-#define AS_BUG_FLDCR
-#endif
-
-/* TODO: convert includes to ${tm_file} list in config.gcc. */
-#include "m88k/m88k.h"
-
-/* Augment TARGET_SWITCHES with the MXDB options. */
-#define MASK_STANDARD 0x40000000 /* Retain standard information */
-#define MASK_NOLEGEND 0x20000000 /* Discard legend information */
-#define MASK_EXTERNAL_LEGEND 0x10000000 /* Make external legends */
-
-#define TARGET_STANDARD (target_flags & MASK_STANDARD)
-#define TARGET_NOLEGEND (target_flags & MASK_NOLEGEND)
-#define TARGET_EXTERNAL_LEGEND (target_flags & MASK_EXTERNAL_LEGEND)
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- { "standard", MASK_STANDARD }, \
- { "legend", -MASK_NOLEGEND }, \
- { "no-legend", MASK_NOLEGEND }, \
- { "external-legend", MASK_EXTERNAL_LEGEND }, \
- /* the following is used only in the *_SPEC's */ \
- { "keep-coff", 0 },
-
-/* Default switches */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV | \
- MASK_OCS_DEBUG_INFO | \
- MASK_OCS_FRAME_POSITION | \
- MASK_STANDARD | \
- MASK_SVR4)
-#undef CPU_DEFAULT
-#define CPU_DEFAULT MASK_88000
-
-/* Macros to be automatically defined. __svr4__ is our extension.
- __CLASSIFY_TYPE__ is used in the <varargs.h> and <stdarg.h> header
- files with DG/UX revision 5.40 and later. This allows GNU CC to
- operate without installing the header files. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -DDGUX -D__CLASSIFY_TYPE__=2\
- -D__svr4__ -Asystem=unix -Acpu=m88k -Amachine=m88k"
-
-/* If -m88100 is in effect, add -Dm88100; similarly for -m88110.
- Here, the CPU_DEFAULT is assumed to be -m88000. If not -ansi,
- or restricting include files to one specific source
- target, specify full DG/UX features. */
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{msvr3:-D_M88KBCS_TARGET} %{!msvr3:-D_DGUX_TARGET}"
-
-/* Assembler support (-V, silicon filter, legends for mxdb). */
-#undef ASM_SPEC
-#define ASM_SPEC "%{pipe:%{!.s: - }\
- %{!msvr3:%{!m88110:-KV3 }%{m88110:-KV04.00 }}}\
- %(asm_cpu)"
-
-/* Override svr4.h. */
-#undef ASM_FINAL_SPEC
-#undef STARTFILE_SPEC
-
-/* Linker and library spec's.
- -msvr4 is the default if -msvr3 is not specified.
- -static, -shared, -symbolic, -h* and -z* access AT&T V.4 link options.
- -svr4 instructs gcc to place /usr/lib/values-X[cat].o on the link line.
- -msvr3 indicates linking done in a COFF environment and the link
- script is added to the link line. In all environments, the first
- and last objects are crtbegin.o (or bcscrtbegin.o) and crtend.o.
- When the -G link option is used (-shared and -symbolic) a final
- link is not being done. */
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
-#undef LIB_SPEC
-#define LIB_SPEC "%{!msvr3:%{!shared:-lstaticdgc}} %{!shared:%{!symbolic:-lc}}"
-#undef LINK_SPEC
-#define LINK_SPEC "%{z*} %{h*} %{v:-V} \
- %{static:-dn -Bstatic} \
- %{shared:-G -dy} \
- %{symbolic:-Bsymbolic -G -dy} \
- %{pg:-L/usr/lib/libp}%{p:-L/usr/lib/libp}"
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%(startfile_default)"
-
-
-/* This macro defines names of additional specifications to put in the specs
- that can be used in various specifications like CC1_SPEC. Its definition
- is an initializer with a subgrouping for each command option.
-
- Each subgrouping contains a string constant, that defines the
- specification name, and a string constant that used by the GNU CC driver
- program.
-
- Do not define this macro if it does not need to do anything. */
-
-#define EXTRA_SPECS \
- { "cpp_cpu", CPP_CPU_SPEC }, \
- { "asm_cpu", ASM_CPU_SPEC }, \
- { "startfile_default", STARTFILE_DEFAULT_SPEC }, \
- { "startfile_crtbegin", STARTFILE_CRTBEGIN_SPEC }
-
-/* Keep this left justified, no white space is allowed between
- the arguments to the -Wc option */
-#define ASM_CPU_SPEC "\
- %{v:-V}\
- %{g:\
-%{mno-legend:-Wc,off}\
-%{!mno-legend:-Wc,-fix-bb,-s\"%i\",-lansi-c\
-%{mstandard:,-keep-std}\
-%{mexternal-legend:,-external}\
-%{mocs-frame-position:,-ocs}}}"
-
-#define CPP_CPU_SPEC "\
- %{!m88000:%{!m88100:%{m88110:-D__m88110__}}} \
- %{!m88000:%{!m88110:%{m88100:-D__m88100__}}} \
- %{!ansi:-D__OPEN_NAMESPACE__}"
-
-#define STARTFILE_DEFAULT_SPEC "\
- %{!shared:%{!symbolic:%{pg:gcrt0.o%s} \
- %{!pg:%{p:/lib/mcrt0.o}%{!p:/lib/crt0.o}} \
- %(startfile_crtbegin) \
- %{svr4:%{ansi:/lib/values-Xc.o} \
- %{!ansi:/usr/lib/values-Xa.o}}}}"
-
-#define STARTFILE_CRTBEGIN_SPEC "\
- %{msvr3:m88kdgux.ld%s bcscrtbegin.o%s} \
- %{!msvr3:crtbegin.o%s}"
-
-#undef GPLUSPLUS_INCLUDE_DIR
-#define GPLUSPLUS_INCLUDE_DIR "/usr/opt/g++/lib/g++-include"
-
-/* Fast DG/UX version of profiler that does not require lots of
- registers to be stored. */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- output_function_profiler (FILE, LABELNO, "gcc.mcount", 0)
-
-/* Output the legend info for mxdb when debugging except if standard
- debugging information only is explicitly requested. */
-#undef ASM_FIRST_LINE
-#define ASM_FIRST_LINE(FILE) \
- do { \
- if (TARGET_SVR4) \
- { \
- if (TARGET_88110) \
- fprintf (FILE, "%s\"%s\"\n", VERSION_ASM_OP, "04.00"); \
- else \
- fprintf (FILE, "%s\"%s\"\n", VERSION_ASM_OP, "03.00"); \
- } \
- if (write_symbols != NO_DEBUG && !TARGET_NOLEGEND) \
- { \
- fprintf (FILE, ";legend_info -fix-bb -h\"gcc-%s\" -s\"%s\"", \
- version_string, main_input_filename); \
- fputs (" -lansi-c", FILE); \
- if (TARGET_STANDARD) \
- fputs (" -keep-std", FILE); \
- if (TARGET_EXTERNAL_LEGEND) \
- fputs (" -external", FILE); \
- if (TARGET_OCS_FRAME_POSITION) \
- fputs (" -ocs", FILE); \
- fputc ('\n', FILE); \
- } \
- } while (0)
-
-/* Override svr4.h. */
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-/* Override svr4.h and m88k.h except when compiling crtstuff.c. These must
- be constant strings when compiling crtstuff.c. Otherwise, respect the
- -mversion-STRING option used. */
-#undef INIT_SECTION_PREAMBLE
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-
-#if defined (CRT_BEGIN) || defined (CRT_END) || defined (L__main)
-/* routines to invoke global constructors and destructors are always COFF
- to enable linking mixed COFF and ELF objects */
-#define FINI_SECTION_ASM_OP ("\tsection .fini,\"x\"")
-#ifndef BCS
-#define INIT_SECTION_PREAMBLE asm ("\taddu\tr31,r31,0x20")
-#endif
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP ("\tsection\t .init,\"x\"")
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP ("\tsection\t .ctors,\"d\"")
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP ("\tsection\t .dtors,\"d\"")
-#undef OBJECT_FORMAT_ELF
-#else
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP (TARGET_SVR4 \
- ? "\tsection\t .init,\"xa\"" \
- : "\tsection\t .init,\"x\"")
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP (TARGET_SVR4 \
- ? "\tsection\t .ctors,\"aw\"" \
- : "\tsection\t .ctors,\"d\"")
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP (TARGET_SVR4 \
- ? "\tsection\t .dtors,\"aw\"" \
- : "\tsection\t .dtors,\"d\"")
-#endif /* crtstuff.c */
-
-/* The lists of global object constructors and global destructors are always
- placed in the .ctors/.dtors sections. This requires the use of a link
- script if the COFF linker is used, but otherwise COFF and ELF objects
- can be intermixed. A COFF object will pad the section to 16 bytes with
- zeros; and ELF object will not contain padding. We deal with this by
- putting a -1 marker at the begin and end of the list and ignoring zero
- entries. */
-
-/* Mark the end of the .ctors/.dtors sections with a -1. */
-
-#define CTOR_LIST_BEGIN \
-asm (CTORS_SECTION_ASM_OP); \
-func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) }
-
-#define CTOR_LIST_END \
-asm (CTORS_SECTION_ASM_OP); \
-func_ptr __CTOR_END__[1] = { (func_ptr) (-1) }
-
-#define DTOR_LIST_BEGIN \
-asm (DTORS_SECTION_ASM_OP); \
-func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) }
-
-#define DTOR_LIST_END \
-asm (DTORS_SECTION_ASM_OP); \
-func_ptr __DTOR_END__[1] = { (func_ptr) (-1) }
-
-/* Walk the list ignoring NULL entries till we hit the terminating -1. */
-#define DO_GLOBAL_CTORS_BODY \
- do { \
- int i; \
- for (i=1;(int)(__CTOR_LIST__[i]) != -1; i++) \
- if (((int *)__CTOR_LIST__)[i] != 0) \
- __CTOR_LIST__[i] (); \
- } while (0)
-
-/* Walk the list looking for the terminating -1 that marks the end.
- Go backward and ignore any NULL entries. */
-#define DO_GLOBAL_DTORS_BODY \
- do { \
- int i; \
- for (i=1;(int)(__DTOR_LIST__[i]) != -1; i++); \
- for (i-=1;(int)(__DTOR_LIST__[i]) != -1; i--) \
- if (((int *)__DTOR_LIST__)[i] != 0) \
- __DTOR_LIST__[i] (); \
- } while (0)
-
-/* The maximum alignment which the object file format can support.
- page alignment would seem to be enough */
-#undef MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 0x1000
+++ /dev/null
-/* m88kdgux.ld - COFF linker directives for G++ on an AViiON
-
- This file is part of GNU CC.
-
- GNU CC is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
- any later version.
-
- GNU CC is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GNU CC; see the file COPYING. If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA.
-
- On The AViiON we start the output .text section somewhere after the
- first 64kb (0x10000) of logical address space so that the first
- 64kb can be mapped out, thus catching references through null
- pointers. We actually start at 0x10200 (for efficiency). Ideally,
- we want the page offset of a given word of the .text (output)
- section to be the same as its page offset in the actual (output)
- linked core file so that paging of the .text section is efficient.
- In order to do this we allow for up to 0x200 bytes of header stuff
- in the output (linked) object file.
-
- For .data, the OCS says that regions with different "protections"
- (i.e. read/write, read-only) should not share any 4 megabyte chunk
- of the logical address space, so we start the .data segment at the
- first (lowest) 4 MB boundary past the end of the .text segment.
-
- For some reason, you can't start right at the 4 MB boundary. You
- have to start at some distance past that. The distance must be
- equal to the distance from the start of the last 64 KB segment in
- the (output) .text segment to the actual end of the (output) .text
- segment. */
-
-SECTIONS {
- .text 0x10200 BLOCK(0x200) :
- { *(.init) *(.initp) *(.finip) *(.text) *(.tdesc) }
-
- GROUP BIND (((((ADDR(.text) + SIZEOF(.text) - 1) / 0x400000) + 1) * 0x400000) + ((ADDR(.text) + SIZEOF (.text)) % 0x10000)) :
- { .data : { *(.data) *(.ctors) *(.dtors) }
- .bss : {} }
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Motorola m88100 running DG/UX.
- Copyright (C) 1988, 1992, 1993, 1994, 1995, 1996, 2001
- Free Software Foundation, Inc.
- Contributed by Michael Tiemann (tiemann@mcc.com)
- Currently maintained by (gcc@dg-rtp.dg.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* dgux.h builds an elf gcc which compiles elf objects by default.
- dguxbcs.h builds a bcs gcc which compiles bcs objects by default.
- The default can be overridden in either case with -msvr3 and -msvr4 */
-
-/* Default switches */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV | \
- MASK_OCS_DEBUG_INFO | \
- MASK_OCS_FRAME_POSITION | \
- MASK_SVR3)
-
-/* Assembler support (-V, silicon filter, legends for mxdb). */
-#undef ASM_SPEC
-#define ASM_SPEC "%{pipe:%{!.s: - }\
- %{msvr4:%{!m88110:-KV3 }%{m88110:-KV04.00 }}}\
- %(asm_cpu)"
-
-/* If -m88100 is in effect, add -Dm88100; similarly for -m88110.
- Here, the CPU_DEFAULT is assumed to be -m88000. */
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
- %{!msvr4:-D_M88KBCS_TARGET} %{msvr4:-D_DGUX_TARGET}"
-
-/* Linker and library spec's.
- -msvr3 is the default if -msvr4 is not specified. */
-#undef LIB_SPEC
-#define LIB_SPEC "%{msvr4:%{!shared:-lstaticdgc}} %{!shared:%{!symbolic:-lc}}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%(startfile_default)"
-
-#undef STARTFILE_CRTBEGIN_SPEC
-#define STARTFILE_CRTBEGIN_SPEC "\
- %{!msvr4:m88kdgux.ld%s bcscrtbegin.o%s} \
- %{msvr4:crtbegin.o%s}"
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Motorola m88100 running the Dolphin UNIX System V/88 Release 3.2,
- Version 3.8/7.83 and 3.6/5.86
- Copyright (C) 1992, 1993, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "m88k/sysv3.h"
-
-#define SDB_ALLOW_FORWARD_REFERENCES
-#define SDB_ALLOW_UNKNOWN_REFERENCES
-
-/* Override m88k/sysv3.h */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -DOCS88 -DDOLPHIN -Dunix -DsysV88 -D__CLASSIFY_TYPE__=2 -Asystem=unix -Asystem=svr3 -Acpu=m88k -Amachine=m88k"
-
-/*
- If you want to detect dereferencing of NULL pointers, uncomment the
- following two lines. Alternatively, edit the appropriate specs file.
-
- #undef LINK_SPEC
- #define LINK_SPEC "gcc.ld%s"
-
- */
-
-#undef CPU_DEFAULT
-#define CPU_DEFAULT MASK_88000
+++ /dev/null
-/* COFF linker directives for the Dolphin Triton88 for GNU compiler.
- Copyright (C) 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* This file does the following:
-
- - Sets VIRTUAL addr of .text to 0x400200
- Sets FILE addr of .text to 0x200 (BLOCK directive)
- - Depending on size of .text section rounds up to next
- 4 MG boundary, adds (size of .text and vaddr of .text) mod 64K
- This is to handle sections larger than 4 MG. */
-
-SECTIONS {
- .text 0x400200 BLOCK (0x200):
- { *(.init) *(.text) *(.rodata) *(.tdesc) *(.fini)}
-
- GROUP BIND( (((SIZEOF(.text)+ADDR(.text)) / 0x400000 * 0x400000) + 0x400000) +
- ((SIZEOF(.text) + ADDR(.text)) % 0x10000) ) :
- {
- .data : { }
- .bss : { }
- }
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Motorola m88100 running Omron Luna/88k.
- Copyright (C) 1991, 1997 Free Software Foundation, Inc.
- Contributed by Jeffrey Friedl (jfriedl@omron.co.jp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* The Omron Luna/88k is MACH and uses BSD a.out, not COFF or ELF. */
-#ifndef MACH
-#define MACH
-#endif
-#define DBX_DEBUGGING_INFO
-#define DEFAULT_GDB_EXTENSIONS 0
-
-#include "aoutos.h"
-#include "m88k/m88k.h"
-
-/* Identify the compiler. */
-#undef VERSION_INFO1
-#define VERSION_INFO1 "Omron Luna/88k"
-
-/* Macros to be automatically defined. */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-DMACH -Dm88k -Dunix -Dluna -Dluna88k -D__CLASSIFY_TYPE__=2 -Asystem=unix -Asystem=mach -Acpu=m88k -Amachine=m88k"
-
-/* If -m88000 is in effect, add -Dmc88000; similarly for -m88100 and -m88110.
- However, reproduce the effect of -Dmc88100 previously in CPP_PREDEFINES.
- Here, the CPU_DEFAULT is assumed to be -m88100. */
-#undef CPP_SPEC
-#define CPP_SPEC "%{m88000:-D__mc88000__} \
- %{!m88000:%{m88100:%{m88110:-D__mc88000__}}} \
- %{!m88000:%{!m88100:%{m88110:-D__mc88110__}}} \
- %{!m88000:%{!m88110:-D__mc88100__ -D__mc88100}}"
-
-/* Specify extra dir to search for include files. */
-#undef SYSTEM_INCLUDE_DIR
-#define SYSTEM_INCLUDE_DIR "/usr/mach/include"
+++ /dev/null
-/* Definitions for "naked" Motorola 88k using coff object format files
- and coff debugging info.
-
- Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "m88k/m88k.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Acpu=m88k -Amachine=m88k"
-
-#define SDB_DEBUGGING_INFO
-
-/* Output DBX (stabs) debugging information if using -gstabs. */
-
-#include "dbxcoff.h"
-
-/* end of m88k-coff.h */
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Motorola m88100 running the AT&T/Unisoft/Motorola V.3 reference port.
- Copyright (C) 1990, 1991, 1997, 1998, 1999 Free Software Foundation, Inc.
- Contributed by Ray Essick (ressick@mot.com)
- Enhanced by Tom Wood (Tom_Wood@NeXT.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "m88k/m88k.h"
-
-/* Default switches */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV | \
- MASK_OCS_DEBUG_INFO | \
- MASK_OCS_FRAME_POSITION)
-
-/* Macros to be automatically defined. */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -DsysV88 -D__CLASSIFY_TYPE__=2 -Asystem=unix -Asystem=svr3 -Acpu=m88k -Amachine=m88k"
-
-/* Override svr3.h to link with ?crt0.o instead of ?crt1.o and ?crtn.o.
- From arul@sdsu.edu. */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} crtbegin.o%s"
-
-/* Profiled libraries live in a different directory but keep the same
- names other than that. arul@sdsu.edu says -lg is always needed. */
-#undef LIB_SPEC
-#define LIB_SPEC "%{p:-L/lib/libp}%{pg:%{!p:-L/lib/libp}} -lg -lc crtend.o%s"
-
-/* We need POSIX/XOPEN symbols; otherwise building libio will fail. */
-#define ADD_MISSING_POSIX 1
-#define ADD_MISSING_XOPEN 1
-
-/* Hot version of the profiler that uses r10 to pass the address of
- the counter. the _gcc_mcount routine knows not to screw with
- the parameter registers.
-
- DG/UX does this; i wrote a gnu-c/88k specific version and put it
- in libgcc2.c -- RBE; this macro knows about the leading underscore
- convention. */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- output_function_profiler (FILE, LABELNO, "_gcc_mcount", 0)
-
-/* Various other changes that we want to have in place without
- too many changes to the m88k.h file. */
-#undef USE_LIBG
-#define USE_LIBG
-
-/* Define a few machine-specific details of the implementation of
- constructors. */
-
-/* Although the .init section is used, it is not automatically invoked. */
-#define INVOKE__main
-
-#define CTOR_LIST_BEGIN \
- asm (INIT_SECTION_ASM_OP); \
- asm ("\tsubu\t r31,r31,16"); /* (STACK_BOUNDARY / BITS_PER_UNIT) == 16 */ \
- asm ("\tst\t r0,r31,32"); /* REG_PARM_STACK_SPACE (0) == 32 */
-#define CTOR_LIST_END
-
-#define TARGET_ASM_CONSTRUCTOR m88k_svr3_asm_out_constructor
-#define TARGET_ASM_DESTRUCTOR m88k_svr3_asm_out_destructor
-
-#undef DO_GLOBAL_CTORS_BODY
-#define DO_GLOBAL_CTORS_BODY \
-do { \
- func_ptr *__CTOR_LIST__ = __builtin_alloca (1), *p; \
- for (p = __CTOR_LIST__ + 4; *p; p += 4) \
- (*p) (); \
-} while (0)
-
-#define DTOR_LIST_BEGIN \
- asm (FINI_SECTION_ASM_OP); \
- func_ptr __DTOR_LIST__[4] = { (func_ptr) (-1), (func_ptr) (-1), \
- (func_ptr) (-1), (func_ptr) (-1) }
-#define DTOR_LIST_END \
- asm (FINI_SECTION_ASM_OP); \
- func_ptr __DTOR_END__[4] = { (func_ptr) 0, (func_ptr) 0, \
- (func_ptr) 0, (func_ptr) 0 }
-
-/* Walk the list looking for the terminating zero and ignoring all values of
- -1. */
-#undef DO_GLOBAL_DTORS_BODY
-#define DO_GLOBAL_DTORS_BODY \
- do { \
- int i; \
- for (i = 0; __DTOR_LIST__[i] != 0; i++) \
- if (((int *)__DTOR_LIST__)[i] != -1) \
- __DTOR_LIST__[i] (); \
- } while (0)
-
-#undef INITIALIZE_TRAMPOLINE
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 40)), FNADDR); \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 36)), CXT); \
- emit_call_insn (gen_call \
- (gen_rtx_MEM \
- (SImode, \
- gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack")), \
- const0_rtx)); \
-}
+++ /dev/null
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
- moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
- moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
- $(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
+++ /dev/null
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
- moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
- moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
- $(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-
-# In a coff environment, a link script is required for ctors and dtors.
-m88kdgux.ld: $(srcdir)/config/m88k/dgux.ld
- rm -f m88kdgux.ld; cp $(srcdir)/config/m88k/dgux.ld ./m88kdgux.ld
-
-# A bcs crtbegin.o is needed since bcs does not
-# increment the stack pointer in the init section as elf does
-bcscrtbegin.o: crtstuff.c $(GCC_PASSES) $(CONFIG_H) gbl-ctors.h
- $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) -DCRT_BEGIN -DBCS \
- -finhibit-size-directive -fno-inline-functions \
- -g0 -c $(srcdir)/crtstuff.c -o bcscrtbegin.o
-
-# Build libgcc.a, crtbegin.o, and crtend.o as bcs objects
-GCC_FOR_TARGET = PATH=/usr/sde/m88kbcs/usr/bin/:/usr/bin TARGET_BINARY_INTERFACE=m88kbcs ./xgcc -B./ -msvr3 -D_M88KBCS_TARGET -mno-ocs-debug-info
-
-# Don't run fixproto
-STMP_FIXPROTO =
+++ /dev/null
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
- moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
- moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
- $(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-T_CPPFLAGS = -DUSE_GAS
-
-# In a coff environment, a link script is required.
-m88kdgux.ld: $(srcdir)/config/m88k/dgux.ld
- rm -f m88kdgux.ld; cp $(srcdir)/config/m88k/dgux.ld ./m88kdgux.ld
+++ /dev/null
-T_CFLAGS = -O -D_M88KBCS_TARGET
+++ /dev/null
-# Use link editor directives to make NULL pointers point to
-# invalid addresses.
-
-EXTRA_PARTS=crtbegin.o crtend.o gcc.ld
-
-gcc.ld: $(srcdir)/config/m88k/dolphin.ld
- rm -f gcc.ld; cp $(srcdir)/config/m88k/dolphin.ld gcc.ld
+++ /dev/null
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
- moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
- moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
- $(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-T_CPPFLAGS = -DUSE_GAS
-
-# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
-# end labels to the .ctors and .dtors section when we link using gcc.
-
-EXTRA_PARTS=crtbegin.o crtend.o
+++ /dev/null
-# Install the custom Tektronix XD88 link editor directives file.
-EXTRA_PARTS=crtbegin.o crtend.o gcc.ld
-
-gcc.ld: $(srcdir)/config/m88k/tekXD88.ld
- rm -f gcc.ld; cp $(srcdir)/config/m88k/tekXD88.ld ./gcc.ld
+++ /dev/null
-/* Tektronix XD88 UTekV 3.2e (svr3 derived from UniSoft System V/88)
-
- Copyright (C) 1993, 2000 Free Software Foundation, Inc.
- Contributed by Kaveh R. Ghazi (ghazi@caip.rutgers.edu) 2/22/93.
-
- This file is part of GNU CC.
-
- GNU CC is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
- any later version.
-
- GNU CC is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GNU CC; see the file COPYING. If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA.
- */
-
-#include "m88k/sysv3.h"
-
-/* Don't output structure tag names when it causes a forward reference.
- Symptom:
- Error messages like
- as: "/usr/tmp/cca22733.s": cannot reduce symbol table, unused symbols remain
- when compiling some programs.
- example program (C++): struct bad { bad(); }; bad::bad() {}
-
- This problem seems to have gone away, perhaps with release 3.6 of the O/S
- from Dolphin. */
-/* #undef SDB_ALLOW_FORWARD_REFERENCES */
-/* I don't know if this SDB thing is needed or not --KRG */
-
-
-/* Use T_ARG as T_VOID. T_VOID is not defined in <syms.h> as it
- should be. If we're cross compiling, then don't do this because
- "gsyms.h" has T_VOID. */
-#ifndef CROSS_COMPILE
-#define T_VOID T_ARG
-#endif
-
-
-/* The bundled ld program needs link editor directives which normally
- reside in /lib/default.ld. We'll pass our own copy during the link
- phase because additional information about extra sections must be added
- so that gcc generated files will link properly.
- --KRG.
- */
-#undef LINK_SPEC
-#define LINK_SPEC "gcc.ld%s"
+++ /dev/null
-/* gcc.ld - COFF linker directives for the Tektronix XD88.
-
- This file is part of GNU CC.
-
- GNU CC is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
- any later version.
-
- GNU CC is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GNU CC; see the file COPYING. If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA.
-
-
- This file does the following:
- - Sets VIRTUAL addr of .text to 0x10200
- Sets FILE addr of .text to 0x200 (BLOCK directive)
- - Depending on size of .text section rounds up to next
- 4 MG boundary, adds (size of .text and vaddr of .text) mod 64K
- This is to handle sections larger than 4 MG.
-*/
-
-SECTIONS {
- .text 0x10200 BLOCK (0x200):
- { *(.init) *(.text) *(.rodata) *(.tdesc) *(.fini)}
-
- GROUP BIND( ((SIZEOF(.text) / 0x400000 * 0x400000) + 0x400000) +
- ((SIZEOF(.text) + ADDR(.text)) % 0x10000) ) :
- {
- .data : { }
- .bss : { }
- }
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler. MIPS RISC-OS BSD version.
- Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_BSD43
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
--Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
-
-#define STANDARD_INCLUDE_DIR "/bsd43/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
--systype /bsd43/"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS BSD Mips"
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-/* Override defaults for finding the MIPS tools. */
-#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- MIPS RISC-OS, 5.0 BSD version.
- Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_BSD43
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
--Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
-
-#define STANDARD_INCLUDE_DIR "/bsd43/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
--systype /bsd43/"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS BSD Mips"
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-/* Override defaults for finding the MIPS tools. */
-#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
- to be misassembled, so we just completely avoid it. */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-do { \
- const unsigned char *s; \
- size_t i, limit = (LEN); \
- for (i = 0, s = (const unsigned char *)(PTR); i < limit; s++, i++) \
- { \
- if ((i % 8) == 0) \
- fputs ("\n\t.byte\t", (FILE)); \
- fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
- } \
- fputs ("\n", (FILE)); \
-} while (0)
+++ /dev/null
-/* Definitions for DECstation running BSD as target machine for GNU compiler.
- Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define DECSTATION
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ANSI_COMPAT \
--DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_4 -Dhost_mips -Dmips \
--Dunix -D_mips -D_unix -D_host_mips -D_MIPSEL -D_R3000 \
--Asystem=unix -Asystem=bsd -Amachine=mips"
-#endif
-
-/* Always uses GNU ld. */
-#ifndef LINK_SPEC
-#define LINK_SPEC "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3}"
-#endif
-
-#define LIB_SPEC ""
-#define STARTFILE_SPEC ""
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "DECstation running BSD 4.4"
-#endif
-
-#define TARGET_DEFAULT MASK_GAS
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "mips/mips.h"
-
-/* Since gas and gld are standard on 4.4 BSD, we don't need these */
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-#undef ASM_FINAL_SPEC
-#undef LIB_SPEC
-#undef STARTFILE_SPEC
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler. DECstation (OSF/1) version.
- Copyright (C) 1992, 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define DEC_OSF1
-
-#define CPP_PREDEFINES "\
--D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \
--Dbsd4_2 -Dhost_mips -Dmips -Dosf -Dunix \
--Asystem=unix -Asystem=xpg4 -Acpu=mips -Amachine=mips"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
-
-#include "mips/ultrix.h"
-#include "mips/mips.h"
-
-/* Specify size_t and wchar_t types. */
-#undef SIZE_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-#define SIZE_TYPE "long unsigned int"
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE SHORT_TYPE_SIZE
-
-/* turn off collect2 COFF support, since ldfcn now has elf declaration */
-#undef OBJECT_FORMAT_COFF
-
-#undef MACHINE_TYPE
-#define MACHINE_TYPE "DECstation running DEC OSF/1"
+++ /dev/null
-/* Definitions of target machine for GNU compiler. MIPS ORION version with
- GOFAST floating point library.
- Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_CPU_STRING_DEFAULT "orion"
-
-#include "mips/elfl64.h"
+++ /dev/null
-/* Like iris4.h, but always inhibits assembler optimization for MIPS as.
- Use this via mips-sgi-iris4loser if you need it. */
-
-#define SUBTARGET_MIPS_AS_ASM_SPEC "-O0 %{v}"
-#define SUBTARGET_ASM_OPTIMIZING_SPEC ""
+++ /dev/null
-/* Definitions of target machine for GNU compiler. MIPS RISC-OS 5.0
- default version.
- Copyright (C) 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
- to be misassembled, so we just completely avoid it. */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-do { \
- const unsigned char *s; \
- size_t i, limit = (LEN); \
- for (i = 0, s = (const unsigned char *)(PTR); i < limit; s++, i++) \
- { \
- if ((i % 8) == 0) \
- fputs ("\n\t.byte\t", (FILE)); \
- fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
- } \
- fputs ("\n", (FILE)); \
-} while (0)
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Sony RISC NEWS (mips)
- Copyright (C) 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_NEWS
-
-#define CPP_PREDEFINES "\
--Dr3000 -Dnews3700 -DLANGUAGE_C -DMIPSEB -DSYSTYPE_BSD \
--Dsony_news -Dsony -Dunix -Dmips -Dhost_mips \
--Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
-
-#define SYSTEM_INCLUDE_DIR "/usr/include2.0"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#define MACHINE_TYPE "RISC NEWS-OS"
-
-/* INITIALIZE_TRAMPOLINE calls this library function to flush
- program and data caches. */
-#define CACHE_FLUSH_FUNC "cacheflush"
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Sony RISC NEWS (mips) System V version.
- Copyright (C) 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_SYSV
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -Dsony -Dsonyrisc -DMIPSEB -DSYSTYPE_SYSV \
--Asystem=unix -Asystem=svr3 -Acpu=mips -Amachine=mips"
-
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-
-#define LIB_SPEC "\
-%{ZBSD43: -L/usr/ucblib -lucb -lresolv -lsocket -lnsl} \
--nocount %{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:-nocount crt1.o%s -count}}"
-
-#define MACHINE_TYPE "Sony RISC NEWS (SVR4 mips)"
-
-#define NO_LIB_PROTOTYPE
-
-#define NO_DOLLAR_IN_LABEL
-
-#define NM_FLAGS "-Bp"
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-/* Mips System V.4 doesn't have a getpagesize() function needed by the
- trampoline code, so use the POSIX sysconf function to get it.
- This is only done when compiling the trampoline code. */
-
-#ifdef L_trampoline
-#include <sys/param.h>
-#include <unistd.h>
-
-#ifdef _SC_PAGE_SIZE
-#define getpagesize() sysconf(_SC_PAGE_SIZE)
-
-#else /* older rev of OS */
-#define getpagesize() (NBPC)
-#endif /* !_SC_PAGE_SIZE */
-#endif /* L_trampoline */
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Sony RISC NEWS (mips)
- Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_NEWS
-
-#define CPP_PREDEFINES "\
--Dmips -Dhost_mips -Dsony -Dsonyrisc -Dunix \
--DLANGUAGE_C -DMIPSEB -DSYSTYPE_SYSV \
--Asystem=unix -Asystem=svr3 -Acpu=mips -Amachine=mips"
-
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC NEWS-OS SVr4"
-
-#include "mips/mips.h"
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- DECstation (OSF/1 reference port with OSF/rose) version.
- Copyright (C) 1991, 1992, 1995, 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define DECSTATION
-#define OSF_OS
-
-#define HALF_PIC_DEBUG TARGET_DEBUG_B_MODE
-#define HALF_PIC_PREFIX "$Lp."
-
-#include "halfpic.h"
-
-#define WORD_SWITCH_TAKES_ARG(STR) \
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names"))
-
-#define CPP_PREDEFINES "\
--DOSF -DOSF1 -Dbsd4_2 -DMIPSEL -Dhost_mips -Dmips -Dunix -DR3000 -DSYSTYPE_BSD \
--Asystem=unix -Asystem=xpg4 -Acpu=mips -Amachine=mips"
-
-#define SUBTARGET_CPP_SPEC "\
-%{.S: %{!ansi:%{!traditional-cpp: -traditional}}}"
-
-/* ??? This assumes that GNU as is always used with GNU ld, and MIPS as is
- always used with MIPS ld. */
-#define LINK_SPEC "\
-%{G*} %{EL} %{EB} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} \
-%{!mmips-as: \
- %{v*: -v} \
- %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \
- %{nostdlib} %{noshrlib} %{glue}}"
-
-#define LIB_SPEC "-lc"
-
-/* Define this macro meaning that `gcc' should find the library
- `libgcc.a' by hand, rather than passing the argument `-lgcc' to
- tell the linker to do the search. */
-
-#define LINK_LIBGCC_SPECIAL 1
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#define MACHINE_TYPE "DECstation with OSF/rose objects"
-
-#ifndef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/ccs/gcc/"
-#endif
-
-#ifndef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-#endif
-
-/* Turn on -mpic-extern by default. */
-#define CC1_SPEC "\
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} %{mips3:-mfp64 -mgp64} \
-%{mint64|mlong64|mlong32:-mexplicit-type-size }\
-%{G*} \
-%{pic-none: -mno-half-pic} \
-%{pic-lib: -mhalf-pic} \
-%{pic-extern: -mhalf-pic} \
-%{pic-calls: -mhalf-pic} \
-%{pic-names*: -mhalf-pic} \
-%{!pic-*: -mhalf-pic}"
-
-/* Specify size_t and wchar_t types. */
-#define SIZE_TYPE "long unsigned int"
-#define WCHAR_TYPE "unsigned int"
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-#define MAX_WCHAR_TYPE_SIZE MAX_LONG_TYPE_SIZE
-
-/* OSF/1 uses gas, not the mips assembler. */
-#define TARGET_DEFAULT MASK_GAS
-
-/* OSF/rose uses stabs, not ECOFF. */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* enable dwarf debugging for testing */
-#define DWARF_DEBUGGING_INFO
-/* This is needed by dwarfout.c. */
-#define SET_ASM_OP "\t.set\t"
-
-/* Tell collect that the object format is OSF/rose. */
-#define OBJECT_FORMAT_ROSE
-
-/* Tell collect where the appropriate binaries are. */
-#define REAL_LD_FILE_NAME "/usr/ccs/gcc/gld"
-#define REAL_NM_FILE_NAME "/usr/ccs/bin/nm"
-#define REAL_STRIP_FILE_NAME "/usr/ccs/bin/strip"
-
-/* Default to -G 0 unless doing ecoff work. */
-#define MIPS_DEFAULT_GVALUE ((TARGET_MIPS_AS) ? 8 : 0)
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- MIPS RISC-OS System V version.
- Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_SYSV
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \
--Asystem=unix -Asystem=svr3 -Acpu=mips -Amachine=mips"
-
-#define STANDARD_INCLUDE_DIR "/sysv/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
--systype /sysv/"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS System V Mips"
-
-/* Override defaults for finding the MIPS tools. */
-#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-
-/* Mips System V doesn't have a getpagesize() function needed by the
- trampoline code, so use the POSIX sysconf function to get it.
- This is only done when compiling the trampoline code. */
-
-#ifdef L_trampoline
-#include <sys/param.h>
-#include <unistd.h>
-
-#ifdef _SC_PAGE_SIZE
-#define getpagesize() sysconf(_SC_PAGE_SIZE)
-
-#else /* older rev of OS */
-#define getpagesize() (NBPC)
-#endif /* !_SC_PAGE_SIZE */
-#endif /* L_trampoline */
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- MIPS RISC-OS 5.0 System V version.
- Copyright (C) 1991, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_SYSV
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \
--Asystem=unix -Asystem=svr3 -Acpu=mips -Amachine=mips"
-
-#define STANDARD_INCLUDE_DIR "/sysv/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
--systype /sysv/ "
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS System V Mips"
-
-/* Override defaults for finding the MIPS tools. */
-#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-
-/* Mips System V doesn't have a getpagesize() function needed by the
- trampoline code, so use the POSIX sysconf function to get it.
- This is only done when compiling the trampoline code. */
-
-#ifdef L_trampoline
-#include <sys/param.h>
-#include <unistd.h>
-
-/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a
- _SC_PAGESIZE macro. */
-#ifdef _SC_PAGESIZE
-#define _SC_PAGE_SIZE _SC_PAGESIZE
-#endif
-
-#ifdef _SC_PAGE_SIZE
-#define getpagesize() sysconf(_SC_PAGE_SIZE)
-
-#else /* older rev of OS */
-#define getpagesize() (NBPC)
-#endif /* !_SC_PAGE_SIZE */
-#endif /* L_trampoline */
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
- to be misassembled, so we just completely avoid it. */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-do { \
- const unsigned char *s; \
- size_t i, limit = (LEN); \
- for (i = 0, s = (const unsigned char *)(PTR); i < limit; s++, i++) \
- { \
- if ((i % 8) == 0) \
- fputs ("\n\t.byte\t", (FILE)); \
- fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
- } \
- fputs ("\n", (FILE)); \
-} while (0)
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- MIPS RISC-OS System V.4 version.
- Copyright (C) 1992, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_SVR4
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
--Asystem=unix -Asystem=svr4 -Acpu=mips -Amachine=mips"
-
-#define STANDARD_INCLUDE_DIR "/svr4/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
--systype /svr4/"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS System V.4 Mips"
-
-/* Override defaults for finding the MIPS tools. */
-#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-
-/* Mips System V.4 doesn't have a getpagesize() function needed by the
- trampoline code, so use the POSIX sysconf function to get it.
- This is only done when compiling the trampoline code. */
-
-#ifdef L_trampoline
-#include <unistd.h>
-
-#define getpagesize() sysconf(_SC_PAGE_SIZE)
-#endif /* L_trampoline */
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- MIPS RISC-OS 5.0 System V.4 version.
- Copyright (C) 1992, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define MIPS_SVR4
-
-#define CPP_PREDEFINES \
-"-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
--D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32 \
--Asystem=unix -Asystem=svr4 -Acpu=mips -Amachine=mips"
-
-#define STANDARD_INCLUDE_DIR "/svr4/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
--systype /svr4/ "
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\
- %{ansi:/svr4/usr/ccs/lib/values-Xc.o%s} \
- %{!ansi:/svr4/usr/ccs/lib/values-Xa.o%s}"
-
-#define MACHINE_TYPE "RISC-OS System V.4 Mips"
-
-/* Override defaults for finding the MIPS tools. */
-#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-
-/* Mips System V.4 doesn't have a getpagesize() function needed by the
- trampoline code, so use the POSIX sysconf function to get it.
- This is only done when compiling the trampoline code. */
-
-#ifdef L_trampoline
-#include <unistd.h>
-
-/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a
- _SC_PAGESIZE macro. */
-#ifdef _SC_PAGESIZE
-#define _SC_PAGE_SIZE _SC_PAGESIZE
-#endif
-
-#define getpagesize() sysconf(_SC_PAGE_SIZE)
-#endif /* L_trampoline */
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
- to be misassembled, so we just completely avoid it. */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-do { \
- const unsigned char *s; \
- size_t i, limit = (LEN); \
- for (i = 0, s = (const unsigned char *)(PTR); i < limit; s++, i++) \
- { \
- if ((i % 8) == 0) \
- fputs ("\n\t.byte\t", (FILE)); \
- fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
- } \
- fputs ("\n", (FILE)); \
-} while (0)
+++ /dev/null
-/* Definitions of target machine for GNU compiler. Tandem S2 w/ NonStop UX. */
-
-/* Use the default value for this. */
-#undef STANDARD_INCLUDE_DIR
-
-#undef MACHINE_TYPE
-#define MACHINE_TYPE "TANDEM System V.4 Mips"
-
-/* Use the default values in mips.h. */
-#undef MD_STARTFILE_PREFIX
-#undef MD_EXEC_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
-
-/* These are the same as the ones in svr4-5.h, except that references to
- /svr4/ have been removed. */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\
- %{ansi:/usr/lib/values-Xc.o%s} \
- %{!ansi:/usr/lib/values-Xa.o%s}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
+++ /dev/null
-# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
-# to point to the bsd43 include files.
-SYSTEM_HEADER_DIR = /bsd43/usr/include
+++ /dev/null
-# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
-# to point to the bsd43 include files.
-SYSTEM_HEADER_DIR = /bsd43/usr/include
+++ /dev/null
-# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
-# to point to the svr3 include files.
-SYSTEM_HEADER_DIR = /sysv/usr/include
+++ /dev/null
-# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
-# to point to the svr3 include files.
-SYSTEM_HEADER_DIR = /sysv/usr/include
+++ /dev/null
-# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
-# to point to the svr4 include files.
-SYSTEM_HEADER_DIR = /svr4/usr/include
+++ /dev/null
-# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
-# to point to the svr4 include files.
-SYSTEM_HEADER_DIR = /svr4/usr/include
+++ /dev/null
-CONFIG2_H = $(srcdir)/config/mips/mips.h
+++ /dev/null
-/* Definitions of target machine for GNU compiler; DECstation (Ultrix) version.
- Copyright (C) 1991, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define DECSTATION
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "\
--D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \
--Dbsd4_2 -Dhost_mips -Dmips -Dultrix -Dunix \
--Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
-#endif
-
-#ifndef LIB_SPEC
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-#endif
-
-#define SUBTARGET_CPP_SPEC "\
-%{.cc: -D__LANGUAGE_C -D_LANGUAGE_C} \
-%{.cxx: -D__LANGUAGE_C -D_LANGUAGE_C} \
-%{.C: -D__LANGUAGE_C -D_LANGUAGE_C} \
-"
-
-#ifndef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-#endif
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "DECstation running ultrix"
-#endif
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-/* Work around assembler forward label references generated in exception
- handling code. */
-#define DWARF2_UNWIND_INFO 0
-
-/* INITIALIZE_TRAMPOLINE calls this library function to flush
- program and data caches. */
-#define CACHE_FLUSH_FUNC "cacheflush"
+++ /dev/null
-/* Operating system specific defines to be used when targeting GCC
- for NeXTSTEP.
- Copyright (C) 2001, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-extern void nextstep_asm_out_constructor PARAMS ((struct rtx_def *, int));
-extern void nextstep_asm_out_destructor PARAMS ((struct rtx_def *, int));
-extern int handle_pragma PARAMS ((int(*)(void), void (*)(int), const char *));
-extern void constructor_section PARAMS ((void));
-extern void destructor_section PARAMS ((void));
-extern void nextstep_exception_section PARAMS ((void));
-extern void nextstep_eh_frame_section PARAMS ((void));
-extern void nextstep_select_section PARAMS ((tree, int,
- unsigned HOST_WIDE_INT));
-extern void nextstep_select_rtx_section PARAMS ((enum machine_mode, rtx,
- unsigned HOST_WIDE_INT));
-
-/* Expanded by EXTRA_SECTION_FUNCTIONS into varasm.o. */
-extern void const_section PARAMS ((void));
-extern void cstring_section PARAMS ((void));
-extern void literal4_section PARAMS ((void));
-extern void literal8_section PARAMS ((void));
-extern void constructor_section PARAMS ((void));
-extern void destructor_section PARAMS ((void));
-extern void nextstep_exception_section PARAMS ((void));
-extern void nextstep_eh_frame_section PARAMS ((void));
-extern void objc_class_section PARAMS ((void));
-extern void objc_meta_class_section PARAMS ((void));
-extern void objc_category_section PARAMS ((void));
-extern void objc_class_vars_section PARAMS ((void));
-extern void objc_instance_vars_section PARAMS ((void));
-extern void objc_cls_meth_section PARAMS ((void));
-extern void objc_inst_meth_section PARAMS ((void));
-extern void objc_cat_cls_meth_section PARAMS ((void));
-extern void objc_cat_inst_meth_section PARAMS ((void));
-extern void objc_selector_refs_section PARAMS ((void));
-extern void objc_symbols_section PARAMS ((void));
-extern void objc_module_info_section PARAMS ((void));
-extern void objc_protocol_section PARAMS ((void));
-extern void objc_string_object_section PARAMS ((void));
-extern void objc_class_names_section PARAMS ((void));
-extern void objc_meth_var_names_section PARAMS ((void));
-extern void objc_meth_var_types_section PARAMS ((void));
-extern void objc_cls_refs_section PARAMS ((void));
+++ /dev/null
-/* Functions for generic NeXT as target machine for GNU C compiler.
- Copyright (C) 1989, 1990, 1991, 1992, 1993, 1996, 1997, 1998,
- 2000, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "config.h"
-#include "system.h"
-#include "flags.h"
-#include "tree.h"
-#include "rtl.h"
-#include "toplev.h"
-#include "output.h"
-#include "tm_p.h"
-
-/* Make everything that used to go in the text section really go there. */
-
-int flag_no_mach_text_sections = 0;
-
-#define OPT_STRCMP(opt) (!strncmp (opt, p, sizeof (opt)-1))
-
-/* 1 if handle_pragma has been called yet. */
-
-static int pragma_initialized;
-
-/* Initial setting of `optimize'. */
-
-static int initial_optimize_flag;
-
-/* Called from check_newline via the macro HANDLE_PRAGMA.
- FINPUT is the source file input stream.
- CH is the first character after `#pragma'.
- The result is 1 if the pragma was handled. */
-
-int
-handle_pragma (p_getc, p_ungetc, pname)
- int (* p_getc) PARAMS ((void)) ATTRIBUTE_UNUSED;
- void (* p_ungetc) PARAMS ((int)) ATTRIBUTE_UNUSED;
- const char *pname;
-{
- int retval = 0;
-
- /* Record initial setting of optimize flag, so we can restore it. */
- if (!pragma_initialized)
- {
- pragma_initialized = 1;
- initial_optimize_flag = optimize;
- }
-
- if (strcmp (pname, "CC_OPT_ON") == 0)
- {
- optimize = 1;
- warning ("optimization turned on");
- retval = 1;
- }
- else if (strcmp (pname, "CC_OPT_OFF") == 0)
- {
- optimize = 0;
- warning ("optimization turned off");
- retval = 1;
- }
- else if (strcmp (pname, "CC_OPT_RESTORE") == 0)
- {
- extern int initial_optimize_flag;
-
- if (optimize != initial_optimize_flag)
- optimize = initial_optimize_flag;
- warning ("optimization level restored");
- retval = 1;
- }
- else if (strcmp (pname, "CC_WRITABLE_STRINGS") == 0)
- flag_writable_strings = retval = 1;
- else if (strcmp (pname, "CC_NON_WRITABLE_STRINGS") == 0)
- flag_writable_strings = 0, retval = 1;
- else if (strcmp (pname, "CC_NO_MACH_TEXT_SECTIONS") == 0)
- flag_no_mach_text_sections = retval = 1;
-
- return retval;
-}
-
-void
-nextstep_asm_out_constructor (symbol, priority)
- rtx symbol;
- int priority ATTRIBUTE_UNUSED;
-{
- constructor_section ();
- assemble_align (POINTER_SIZE);
- assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
- fprintf (asm_out_file, ".reference .constructors_used\n");
-}
-
-void
-nextstep_asm_out_destructor (symbol, priority)
- rtx symbol;
- int priority ATTRIBUTE_UNUSED;
-{
- destructor_section ();
- assemble_align (POINTER_SIZE);
- assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
- fprintf (asm_out_file, ".reference .destructors_used\n");
-}
-
-void
-nextstep_select_section (exp, reloc, align)
- tree exp;
- int reloc;
- unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
-{
- if (TREE_CODE (exp) == STRING_CST)
- {
- if (flag_writable_strings)
- data_section ();
- else if (TREE_STRING_LENGTH (exp)
- != strlen (TREE_STRING_POINTER (exp)) + 1)
- readonly_data_section ();
- else
- cstring_section ();
- }
- else if (TREE_CODE (exp) == INTEGER_CST
- || TREE_CODE (exp) == REAL_CST)
- {
- tree size = TYPE_SIZE (TREE_TYPE (exp));
- HOST_WIDE_INT size_i;
-
- if (TREE_CODE (size) == INTEGER_CST)
- size_i = tree_low_cst (size, 1);
- else
- size_i = 0;
-
- if (size_i == 4)
- literal4_section ();
- else if (size_i == 8)
- literal8_section ();
- else
- readonly_data_section ();
- }
- else if (TREE_CODE (exp) == CONSTRUCTOR
- && TREE_TYPE (exp)
- && TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE
- && TYPE_NAME (TREE_TYPE (exp))
- && TREE_CODE (TYPE_NAME (TREE_TYPE (exp))) == IDENTIFIER_NODE
- && IDENTIFIER_POINTER (TYPE_NAME (TREE_TYPE (exp))))
- {
- if (!strcmp (IDENTIFIER_POINTER (TYPE_NAME (TREE_TYPE (exp))),
- "NXConstantString"))
- objc_string_object_section ();
- else if ((TREE_READONLY (exp) || TREE_CONSTANT (exp))
- && !TREE_SIDE_EFFECTS (exp))
- readonly_data_section ();
- else
- data_section ();
- }
- else if (TREE_CODE (exp) == VAR_DECL
- && DECL_NAME (exp)
- && TREE_CODE (DECL_NAME (exp)) == IDENTIFIER_NODE
- && IDENTIFIER_POINTER (DECL_NAME (exp))
- && !strncmp (IDENTIFIER_POINTER (DECL_NAME (exp)), "_OBJC_", 6))
- {
- const char *name = IDENTIFIER_POINTER (DECL_NAME (exp));
-
- if (!strncmp (name, "_OBJC_CLASS_METHODS_", 20))
- objc_cls_meth_section ();
- else if (!strncmp (name, "_OBJC_INSTANCE_METHODS_", 23))
- objc_inst_meth_section ();
- else if (!strncmp (name, "_OBJC_CATEGORY_CLASS_METHODS_", 20))
- objc_cat_cls_meth_section ();
- else if (!strncmp (name, "_OBJC_CATEGORY_INSTANCE_METHODS_", 23))
- objc_cat_inst_meth_section ();
- else if (!strncmp (name, "_OBJC_CLASS_VARIABLES_", 22))
- objc_class_vars_section ();
- else if (!strncmp (name, "_OBJC_INSTANCE_VARIABLES_", 25))
- objc_instance_vars_section ();
- else if (!strncmp (name, "_OBJC_CLASS_PROTOCOLS_", 22))
- objc_cat_cls_meth_section ();
- else if (!strncmp (name, "_OBJC_CLASS_NAME_", 17))
- objc_class_names_section ();
- else if (!strncmp (name, "_OBJC_METH_VAR_NAME_", 20))
- objc_meth_var_names_section ();
- else if (!strncmp (name, "_OBJC_METH_VAR_TYPE_", 20))
- objc_meth_var_types_section ();
- else if (!strncmp (name, "_OBJC_CLASS_REFERENCES", 22))
- objc_cls_refs_section ();
- else if (!strncmp (name, "_OBJC_CLASS_", 12))
- objc_class_section ();
- else if (!strncmp (name, "_OBJC_METACLASS_", 16))
- objc_meta_class_section ();
- else if (!strncmp (name, "_OBJC_CATEGORY_", 15))
- objc_category_section ();
- else if (!strncmp (name, "_OBJC_SELECTOR_REFERENCES", 25))
- objc_selector_refs_section ();
- else if (!strncmp (name, "_OBJC_SYMBOLS", 13))
- objc_symbols_section ();
- else if (!strncmp (name, "_OBJC_MODULES", 13))
- objc_module_info_section ();
- else if (!strncmp (name, "_OBJC_PROTOCOL_INSTANCE_METHODS_", 32))
- objc_cat_inst_meth_section ();
- else if (!strncmp (name, "_OBJC_PROTOCOL_CLASS_METHODS_", 29))
- objc_cat_cls_meth_section ();
- else if (!strncmp (name, "_OBJC_PROTOCOL_REFS_", 20))
- objc_cat_cls_meth_section ();
- else if (!strncmp (name, "_OBJC_PROTOCOL_", 15))
- objc_protocol_section ();
- else if ((TREE_READONLY (exp) || TREE_CONSTANT (exp))
- && !TREE_SIDE_EFFECTS (exp))
- readonly_data_section ();
- else
- data_section ();
- }
- else if (TREE_CODE (exp) == VAR_DECL)
- {
- if ((flag_pic && reloc)
- || !TREE_READONLY (exp) || TREE_SIDE_EFFECTS (exp)
- || !DECL_INITIAL (exp)
- || (DECL_INITIAL (exp) != error_mark_node
- && !TREE_CONSTANT (DECL_INITIAL (exp))))
- data_section ();
- else
- readonly_data_section ();
- }
- else
- readonly_data_section ();
-}
-
-void
-nextstep_select_rtx_section (mode, x, align)
- enum machine_mode mode;
- rtx x;
- unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
-{
- if (GET_MODE_SIZE (mode) == 8)
- literal8_section ();
- else if (GET_MODE_SIZE (mode) == 4
- && (GET_CODE (x) == CONST_INT
- || GET_CODE (x) == CONST_DOUBLE))
- literal4_section ();
- else
- const_section ();
-}
+++ /dev/null
-/* Operating system specific defines to be used when targeting GCC
- for NeXTSTEP.
- Copyright (C) 1989, 1990, 1991, 1992, 1993, 1996, 1997,
- 1999, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Use new NeXT include file search path.
- In a cross compiler with NeXT as target, don't expect
- the host to use Next's directory scheme. */
-
-#ifndef CROSS_COMPILE
-#undef INCLUDE_DEFAULTS
-#define INCLUDE_DEFAULTS \
- { \
- { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 }, \
- { LOCAL_INCLUDE_DIR, 0, 0, 1 }, \
- { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1 }, \
- { GCC_INCLUDE_DIR, "GCC", 0, 0 }, \
- /* These are for fixincludes-fixed ansi/bsd headers \
- which wouldn't be found otherwise. \
- (The use of string catenation here is OK since \
- NeXT's native compiler is derived from GCC.) */ \
- { GCC_INCLUDE_DIR "/ansi", 0, 0, 0 }, \
- { GCC_INCLUDE_DIR "/bsd", 0, 0, 0 }, \
- { "/NextDeveloper/Headers", 0, 0, 0 }, \
- { "/NextDeveloper/Headers/ansi", 0, 0, 0 }, \
- { "/NextDeveloper/Headers/bsd", 0, 0, 0 }, \
- { "/LocalDeveloper/Headers", 0, 0, 0 }, \
- { "/LocalDeveloper/Headers/ansi", 0, 0, 0 }, \
- { "/LocalDeveloper/Headers/bsd", 0, 0, 0 }, \
- { "/NextDeveloper/2.0CompatibleHeaders", 0, 0, 0 }, \
- { STANDARD_INCLUDE_DIR, 0, 0, 0 }, \
- { "/usr/include/bsd", 0, 0, 0 }, \
- { 0, 0, 0, 0 } \
- }
-#else /* CROSS_COMPILE */
-#undef INCLUDE_DEFAULTS
-#define INCLUDE_DEFAULTS \
- { \
- { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 }, \
- { GPLUSPLUS_INCLUDE_DIR, 0, 1, 1 }, \
- { GCC_INCLUDE_DIR, "GCC", 0, 0 }, \
- { GCC_INCLUDE_DIR "/ansi", 0, 0, 0 }, \
- { GCC_INCLUDE_DIR "/bsd", 0, 0, 0 }, \
- { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1 }, \
- { TOOL_INCLUDE_DIR "/ansi", 0, 0, 0 }, \
- { TOOL_INCLUDE_DIR "/bsd", 0, 0, 0 }, \
- { "/usr/include/bsd", 0, 0, 0 }, \
- { 0, 0, 0, 0 } \
- }
-#endif /* CROSS_COMPILE */
-
-#undef EXTRA_FORMAT_FUNCTIONS
-#define EXTRA_FORMAT_FUNCTIONS \
- "NXPrintf", FALSE, 2, FALSE, \
- "NXScanf", TRUE, 2, FALSE, \
- "NXVPrintf", FALSE, 2, TRUE, \
- "NXVScanf", TRUE, 2, TRUE, \
- "DPSPrintf", FALSE, 2, FALSE, \
- "bsd_sprintf", FALSE, 2, FALSE, \
- "bsd_vsprintf", FALSE, 2, TRUE,
-
-/* Make -fnext-runtime the default. */
-
-#define NEXT_OBJC_RUNTIME
-
-/* Enable recent gcc to compile under the old gcc in Next release 1.0. */
-
-#define __inline inline
-
-/* wchar_t is unsigned short */
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE (BITS_PER_WORD / 2)
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
- we want to retain compatibility with older gcc versions. */
-
-#undef DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* These compiler options take n arguments. */
-
-#undef WORD_SWITCH_TAKES_ARG
-#define WORD_SWITCH_TAKES_ARG(STR) \
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) ? 1 : \
- !strcmp (STR, "segalign") ? 1 : \
- !strcmp (STR, "seg1addr") ? 1 : \
- !strcmp (STR, "segaddr") ? 2 : \
- !strcmp (STR, "sectobjectsymbols") ? 2 : \
- !strcmp (STR, "segprot") ? 3 : \
- !strcmp (STR, "sectcreate") ? 3 : \
- !strcmp (STR, "sectalign") ? 3 : \
- !strcmp (STR, "segcreate") ? 3 : \
- !strcmp (STR, "sectorder") ? 3 : \
- !strcmp (STR, "siff-mask") ? 1 : \
- !strcmp (STR, "siff-filter") ? 1 : \
- !strcmp (STR, "siff-warning") ? 1 : \
- !strcmp (STR, "arch") ? 1 : \
- !strcmp (STR, "pagezero_size") ? 1 : \
- 0)
-
-#undef WORD_SWITCH
-#define WORD_SWITCH(STR) \
- (WORD_SWITCH_TAKES_ARG (STR) \
- || !strcmp (STR, "bsd") \
- || !strcmp (STR, "object") \
- || !strcmp (STR, "ObjC") \
- || !strcmp (STR, "all_load"))
-
-/* Machine dependent ccp options. */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posixstrict:-D_POSIX_SOURCE} \
- %{!posixstrict:%{bsd:-D__STRICT_BSD__} \
- %{posix:-D_POSIX_SOURCE} \
- %{!ansi:-D_NEXT_SOURCE}} \
- %{MD:-MD %M} %{MMD:-MMD %M}"
-
-/* Machine dependent ld options. */
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{Z} %{M} \
-%{execute*} %{preload*} %{fvmlib*} \
-%{segalign*} %{seg1addr*} %{segaddr*} %{segprot*} \
-%{pagezero_size*} \
-%{seglinkedit*} %{noseglinkedit*} \
-%{sectcreate*} %{sectalign*} %{sectobjectsymbols}\
-%{segcreate*} %{Mach*} %{whyload} %{w} \
-%{sectorder*} %{whatsloaded} %{ObjC} %{all_load} %{object}"
-
-/* Machine dependent libraries. */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{!posix*:-lsys_s} %{posix*:-lposix}"
-
-/* We specify crt0.o as -lcrt0.o so that ld will search the library path. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{!posix*:%{pg:-lgcrt0.o}%{!pg: \
- %{p:%e-p profiling is no longer supported. Use -pg instead} \
- %{!p:-lcrt0.o}}}\
- %{posix*:%{pg:-lgposixcrt0.o}%{!pg: \
- %{p:%e-p profiling is no longer supported. Use -pg instead} \
- %{!p:-lposixcrt0.o}}} \
- -lcrtbegin.o"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
- "-lcrtend.o"
-
-/* Allow #sscs (but don't do anything). */
-
-#define SCCS_DIRECTIVE
-
-/* We use Dbx symbol format. */
-
-#undef SDB_DEBUGGING_INFO
-#undef XCOFF_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-/* This saves a fair amount of space. */
-
-#undef DBX_CONTIN_LENGTH
-#define DBX_CONTIN_LENGTH 0
-
-/* These screw up NeXT's gdb at the moment, so don't use them. */
-
-#undef DBX_OUTPUT_MAIN_SOURCE_DIRECTORY
-#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(FILE, FILENAME)
-
-/* These come from bsd386.h, but are specific to sequent, so make sure
- they don't bite us. */
-
-#undef DBX_NO_XREFS
-#undef DBX_CONTIN_LENGTH
-
-/* gdb needs a null N_SO at the end of each file for scattered loading. */
-
-#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \
- fprintf (FILE, \
- "\t.text\n\t.stabs \"%s\",%d,0,0,Letext\nLetext:\n", \
- "" , N_SO)
-
-/* Define our object format type for crtstuff.c */
-#define OBJECT_FORMAT_MACHO
-
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP
-#undef INVOKE__main
-
-#define TARGET_ASM_CONSTRUCTOR nextstep_asm_out_constructor
-#define TARGET_ASM_DESTRUCTOR nextstep_asm_out_destructor
-
-#define TARGET_ASM_EXCEPTION_SECTION nextstep_exception_section
-
-#define TARGET_ASM_EH_FRAME_SECTION nextstep_eh_frame_section
-
-/* Don't output a .file directive. That is only used by the assembler for
- error reporting. */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)
-
-#undef ASM_FILE_END
-#define ASM_FILE_END(FILE) \
- do { \
- if (strcmp (lang_hooks.name, "GNU C++") == 0) \
- { \
- constructor_section (); \
- destructor_section (); \
- ASM_OUTPUT_ALIGN (FILE, 1); \
- } \
- } while (0)
-
-/* How to parse #pragma's */
-
-#undef HANDLE_PRAGMA
-#define HANDLE_PRAGMA(GETC, UNGETC, NAME) handle_pragma (GETC, UNGETC, NAME)
-
-/* Give methods pretty symbol names on NeXT. */
-
-#undef OBJC_GEN_METHOD_LABEL
-#define OBJC_GEN_METHOD_LABEL(BUF,IS_INST,CLASS_NAME,CAT_NAME,SEL_NAME,NUM) \
- do { if (CAT_NAME) \
- sprintf (BUF, "%c[%s(%s) %s]", (IS_INST) ? '-' : '+', \
- (CLASS_NAME), (CAT_NAME), (SEL_NAME)); \
- else \
- sprintf (BUF, "%c[%s %s]", (IS_INST) ? '-' : '+', \
- (CLASS_NAME), (SEL_NAME)); \
- } while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* Wrap new method names in quotes so the assembler doesn't gag.
- Make Objective-C internal symbols local. */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE,NAME) \
- do { if (NAME[0] == '+' || NAME[0] == '-') fprintf (FILE, "\"%s\"", NAME); \
- else if (!strncmp (NAME, "_OBJC_", 6)) fprintf (FILE, "L%s", NAME); \
- else if (!strncmp (NAME, ".objc_class_name_", 17)) \
- fprintf (FILE, "%s", NAME); \
- else asm_fprintf (FILE, "%U%s", NAME); } while (0)
-
-#undef ALIGN_ASM_OP
-#define ALIGN_ASM_OP "\t.align\t"
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG) != 0) \
- fprintf (FILE, "%s%d\n", ALIGN_ASM_OP, (LOG))
-
-/* Ensure correct alignment of bss data. */
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
-( fputs (".lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u,%u\n", (SIZE), floor_log2 ((ALIGN) / BITS_PER_UNIT)))
-
-/* Output #ident as a .ident. */
-
-#undef ASM_OUTPUT_IDENT
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* The maximum alignment which the object file format can support.
- For NeXT's Mach-O format, this is 2^15. */
-
-#undef MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 0x8000
-
-/* Create new Mach-O sections. */
-
-#undef SECTION_FUNCTION
-#define SECTION_FUNCTION(FUNCTION, SECTION, DIRECTIVE, WAS_TEXT, OBJC) \
-extern void FUNCTION PARAMS ((void)); \
-void \
-FUNCTION () \
-{ \
- extern int flag_no_mach_text_sections; \
- \
- if (WAS_TEXT && flag_no_mach_text_sections) \
- text_section (); \
- else if (in_section != SECTION) \
- { \
- if (OBJC) \
- objc_section_init (); \
- fprintf (asm_out_file, "%s\n", DIRECTIVE); \
- in_section = SECTION; \
- } \
-} \
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS \
- in_const, in_cstring, in_literal4, in_literal8, \
- in_constructor, in_destructor, \
- in_nextstep_exception, in_nextstep_eh_frame, \
- in_objc_class, in_objc_meta_class, in_objc_category, \
- in_objc_class_vars, in_objc_instance_vars, \
- in_objc_cls_meth, in_objc_inst_meth, \
- in_objc_cat_cls_meth, in_objc_cat_inst_meth, \
- in_objc_selector_refs, \
- in_objc_symbols, in_objc_module_info, \
- in_objc_protocol, in_objc_string_object, \
- in_objc_class_names, in_objc_meth_var_names, \
- in_objc_meth_var_types, in_objc_cls_refs
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS \
-extern void objc_section_init PARAMS ((void)); \
-SECTION_FUNCTION (const_section, \
- in_const, \
- ".const", 1, 0) \
-SECTION_FUNCTION (cstring_section, \
- in_cstring, \
- ".cstring", 1, 0) \
-SECTION_FUNCTION (literal4_section, \
- in_literal4, \
- ".literal4", 1, 0) \
-SECTION_FUNCTION (literal8_section, \
- in_literal8, \
- ".literal8", 1, 0) \
-SECTION_FUNCTION (constructor_section, \
- in_constructor, \
- ".constructor", 0, 0) \
-SECTION_FUNCTION (destructor_section, \
- in_destructor, \
- ".destructor", 0, 0) \
-SECTION_FUNCTION (nextstep_exception_section, \
- in_nextstep_exception, \
- ".section __TEXT,__gcc_except_tab,regular", 0, 0) \
-SECTION_FUNCTION (nextstep_eh_frame_section, \
- in_nextstep_eh_frame, \
- ".section __TEXT,__eh_frame,regular", 0, 0) \
-SECTION_FUNCTION (objc_class_section, \
- in_objc_class, \
- ".objc_class", 0, 1) \
-SECTION_FUNCTION (objc_meta_class_section, \
- in_objc_meta_class, \
- ".objc_meta_class", 0, 1) \
-SECTION_FUNCTION (objc_category_section, \
- in_objc_category, \
- ".objc_category", 0, 1) \
-SECTION_FUNCTION (objc_class_vars_section, \
- in_objc_class_vars, \
- ".objc_class_vars", 0, 1) \
-SECTION_FUNCTION (objc_instance_vars_section, \
- in_objc_instance_vars, \
- ".objc_instance_vars", 0, 1) \
-SECTION_FUNCTION (objc_cls_meth_section, \
- in_objc_cls_meth, \
- ".objc_cls_meth", 0, 1) \
-SECTION_FUNCTION (objc_inst_meth_section, \
- in_objc_inst_meth, \
- ".objc_inst_meth", 0, 1) \
-SECTION_FUNCTION (objc_cat_cls_meth_section, \
- in_objc_cat_cls_meth, \
- ".objc_cat_cls_meth", 0, 1) \
-SECTION_FUNCTION (objc_cat_inst_meth_section, \
- in_objc_cat_inst_meth, \
- ".objc_cat_inst_meth", 0, 1) \
-SECTION_FUNCTION (objc_selector_refs_section, \
- in_objc_selector_refs, \
- ".objc_message_refs", 0, 1) \
-SECTION_FUNCTION (objc_symbols_section, \
- in_objc_symbols, \
- ".objc_symbols", 0, 1) \
-SECTION_FUNCTION (objc_module_info_section, \
- in_objc_module_info, \
- ".objc_module_info", 0, 1) \
-SECTION_FUNCTION (objc_protocol_section, \
- in_objc_protocol, \
- ".objc_protocol", 0, 1) \
-SECTION_FUNCTION (objc_string_object_section, \
- in_objc_string_object, \
- ".objc_string_object", 0, 1) \
-SECTION_FUNCTION (objc_class_names_section, \
- in_objc_class_names, \
- ".objc_class_names", 0, 1) \
-SECTION_FUNCTION (objc_meth_var_names_section, \
- in_objc_meth_var_names, \
- ".objc_meth_var_names", 0, 1) \
-SECTION_FUNCTION (objc_meth_var_types_section, \
- in_objc_meth_var_types, \
- ".objc_meth_var_types", 0, 1) \
-SECTION_FUNCTION (objc_cls_refs_section, \
- in_objc_cls_refs, \
- ".objc_cls_refs", 0, 1) \
- \
-void \
-objc_section_init () \
-{ \
- static int been_here = 0; \
- \
- if (been_here == 0) \
- { \
- been_here = 1; \
- objc_class_section (); \
- objc_meta_class_section (); \
- objc_cat_cls_meth_section (); \
- objc_cat_inst_meth_section (); \
- objc_cls_meth_section (); \
- objc_inst_meth_section (); \
- objc_selector_refs_section (); \
- objc_symbols_section (); \
- objc_category_section (); \
- objc_protocol_section (); \
- objc_class_vars_section (); \
- objc_instance_vars_section (); \
- objc_module_info_section (); \
- objc_string_object_section (); \
- objc_class_names_section (); \
- objc_meth_var_names_section (); \
- objc_meth_var_types_section (); \
- objc_cls_refs_section (); \
- } \
-}
-
-#define READONLY_DATA_SECTION const_section
-
-#undef TARGET_ASM_SELECT_SECTION
-#define TARGET_ASM_SELECT_SECTION nextstep_select_section
-#undef TARGET_ASM_SELECT_RTX_SECTION
-#define TARGET_ASM_SELECT_RTX_SECTION nextstep_select_rtx_section
-
-#ifdef ASM_COMMENT_START
-# undef ASM_COMMENT_START
-#endif
-
-#define ASM_COMMENT_START ";#"
+++ /dev/null
-/* nextstep.h -- operating system specific defines to be used when
- targeting GCC for NeXTSTEP.
- Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* changed for NeXTStep 2.1, Ch. Kranz, 2/94, 3/94 */
-#include "nextstep.h"
-
-/* set flag_gnu_linker=0, use collect2 for linking */
-#undef USE_COLLECT2
-#define USE_COLLECT2
-
-/* use this until a newer gdb for NeXTStep21 is available */
-#define DEFAULT_GDB_EXTENSIONS 0
-
-/* we need the call to __main to start all global destructors and constructors
- correctly, so undef INIT_SECTION_ASM_OP, (see libgcc2.c line 1965)
- and define INVOKE_main */
-#undef INIT_SECTION_ASM_OP
-#define INVOKE__main
-
-/* We call the global destructors, constructors from __main */
-#undef TARGET_ASM_CONSTRUCTOR
-#undef TARGET_ASM_DESTRUCTOR
-
-#undef ASM_FILE_END
-#define ASM_FILE_END(FILE) \
- do { \
- if (strcmp (lang_hooks.name, "GNU C++") == 0) \
- { \
- ASM_OUTPUT_ALIGN (FILE, 1); \
- } \
- } while (0)
-/* deleted: destructor_section (); \ */
-/* deleted: constructor_section (); \ */
-
-/* Ensure correct alignment of bss data. */
-/* ASM_OUTPUT_ALIGNED_LOCAL not needed */
-/* need ASM_OUTPUT_LOCAL instead for old NeXT-as */
-/* look in varasm.c, line 1062 and 1476 */
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u\n", (ROUNDED)))
-
+++ /dev/null
-/* Definitions of target machine for GNU compiler. ENCORE NS32000 version.
- Copyright (C) 1988, 1993, 2000, 2001, 2002 Free Software Foundation, Inc.
- Adapted by Robert Brown (brown@harvard.harvard.edu) from the Sequent
- version by Michael Tiemann (tiemann@mcc.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-#define EXTERNAL_PREFIX '?'
-#define IMMEDIATE_PREFIX '$'
-
-#include "ns32k/ns32k.h"
-
-#define SDB_DEBUGGING_INFO
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Cause long-jump assembler to be used,
- since otherwise some files fail to be assembled right. */
-#define ASM_SPEC "-j"
-
-#undef ASM_FILE_START
-#undef ASM_GENERATE_INTERNAL_LABEL
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#undef ASM_OUTPUT_ALIGN
-#undef ASM_OUTPUT_ASCII
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#undef ASM_OUTPUT_LOCAL
-#undef CPP_PREDEFINES
-#undef FUNCTION_BOUNDARY
-#undef PRINT_OPERAND
-#undef PRINT_OPERAND_ADDRESS
-#undef TARGET_VERSION
-#undef FUNCTION_PROFILER
-
-#define TARGET_DEFAULT 9 /* 32332 with 32081. */
-#define TARGET_VERSION fprintf (stderr, " (32000, Encore syntax)");
-/* Note Encore does not standardly do -Dencore. */
-/* budd: should have a -ns32332 (or -apc) switch! but no harm for now */
-#define CPP_PREDEFINES "-Dns32000 -Dn16 -Dns16000 -Dns32332 -Dunix -Asystem=unix -Acpu=ns32k -Amachine=ns32k"
-
-/* Ignore certain cpp directives used in header files on sysV. */
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident. */
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* The .file command should always begin the output. */
-#define ASM_FILE_START(FILE) \
-output_file_directive ((FILE), main_input_filename)
-
-#define FUNCTION_BOUNDARY 128 /* speed optimization */
-
-/*
- * The Encore assembler uses ".align 2" to align on 2-byte boundaries.
- */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-/* The Encore assembler doesn't seem to accept the usual second argument
- and warns that .align may not work in the text section if optimization
- is on. */
-#undef LABEL_ALIGN_AFTER_BARRIER
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0
-
-/*
- * Internal labels are prefixed with a period.
- */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, "*.%s%ld", PREFIX, (long)(NUM))
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\t.double .L%d-.LI%d\n", VALUE, REL)
-
-/*
- * Different syntax for integer constants, double constants, and
- * uninitialized locals.
- */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.bss ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%u,%u\n", (SIZE), (ROUNDED)))
-
- /*
- * Encore assembler can't handle huge string constants like the one in
- * gcc.c. If the default routine in varasm.c were more conservative, this
- * code could be eliminated. It starts a new .ascii directive every 40
- * characters.
- */
-
-#define ASM_OUTPUT_ASCII(file, p, size) \
-do { \
- size_t i, limit = (size); \
- for (i = 0; i < limit; i++) \
- { \
- register int c = (p)[i]; \
- if ((i / 40) * 40 == i) \
- { \
- if (i == 0) \
- fprintf ((file), "\t.ascii \""); \
- else \
- fprintf ((file), "\"\n\t.ascii \""); \
- } \
- if (c == '\"' || c == '\\') \
- putc ('\\', (file)); \
- if (c >= ' ' && c < 0177) \
- putc (c, (file)); \
- else \
- { \
- fprintf ((file), "\\%o", c); \
- if (i < limit - 1 && ISDIGIT ((p)[i + 1])) \
- fprintf ((file), "\"\n\t.ascii \""); \
- } \
- } \
- fprintf ((file), "\"\n"); \
-} while (0)
-
-/* Modify syntax of jsr instructions. */
-#define CALL_MEMREF_IMPLICIT
-
-#define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR)
-\f
-/* Change the way in which data is allocated and initialized on the
- encore so that both private and shared data are supported. Shared data
- that is initialized must be contained in the ".shrdata" section
- of the program. This is accomplished by defining the SHARED_SECTION_ASM_OP
- macro. Share data that is simply allocated, and not initialized must
- be prefixed with the ".shrcomm" or ".shrbss" pseudo op, for common or
- local data respectively. This is accomplished by redefining the
- ASM_OUTPUT_COMMON and ASM_OUTPUT_LOCAL macros. */
-
-/* Assembler pseudo-op for shared data segment. */
-
-#define SHARED_SECTION_ASM_OP "\t.shrdata"
-
-/* This says how to output an assembler line
- to define a shared common symbol. */
-
-#define ASM_OUTPUT_SHARED_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".shrcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (ROUNDED)))
-
-/* This says how to output an assembler line
- to define a shared local symbol. */
-
-#define ASM_OUTPUT_SHARED_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.shrbss ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d,%d\n", (SIZE), (ROUNDED)))
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\taddr .LP%d,r0\n\tjsr mcount\n", (LABELNO))
-
-#define ENCORE_ASM
+++ /dev/null
-/* Definitions of target machine for GNU compiler. MERLIN NS32000 version.
- Copyright (C) 1990, 1994, 2000 Free Software Foundation, Inc.
- By Mark Mason (mason@reed.bitnet, pyramid!unify!mason@uunet.uu.net).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Two flags to control how addresses are printed in assembler insns. */
-
-#define SEQUENT_ADDRESS_BUG 1
-#define SEQUENT_BASE_REGS
-
-#include "ns32k/ns32k.h"
-
-#define MERLIN_TARGET
-
-/* This is BSD, so it wants DBX format. */
-#define DBX_DEBUGGING_INFO
-
-/* Sequent has some changes in the format of DBX symbols. */
-#define DBX_NO_XREFS 1
-
-/* Don't split DBX symbols into continuations. */
-#define DBX_CONTIN_LENGTH 0
-
-#define TARGET_DEFAULT 1
-
-/* Print subsidiary information on the compiler version in use. */
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (32000, UTek syntax)");
-
-/* These control the C++ compiler somehow. */
-#define FASCIST_ASSEMBLER
-#define USE_COLLECT
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dns32000 -Dns32k -Dns16000 -Dmerlin -Dunix -DUtek -Dbsd \
- -Asystem=unix -Asystem=bsd -Acpu=ns32k -Amachine=ns32k"
-
-/* This is how to align the code that follows an unconditional branch.
- Don't define it, since it confuses the assembler (we hear). */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP "\t.shdata"
-
-/* %$ means print the prefix for an immediate operand. */
-
-#ifdef UTEK_ASM
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE) do { \
- if (CODE == '$') putc('$', FILE); \
- else if (CODE == '?'); \
- else if (GET_CODE (X) == CONST_INT) \
- fprintf(FILE, "$%d", INTVAL(X)); \
- else if (GET_CODE (X) == REG) \
- fprintf (FILE, "%s", reg_names[REGNO (X)]); \
- else if (GET_CODE (X) == MEM) \
- { \
- rtx xfoo; \
- xfoo = XEXP (X, 0); \
- switch (GET_CODE (xfoo)) \
- { \
- case MEM: \
- if (GET_CODE (XEXP (xfoo, 0)) == REG) \
- if (REGNO (XEXP (xfoo, 0)) == STACK_POINTER_REGNUM) \
- fprintf (FILE, "0(0(sp))"); \
- else fprintf (FILE, "0(0(%s))", \
- reg_names[REGNO (XEXP (xfoo, 0))]); \
- else \
- { \
- if (GET_CODE (XEXP (xfoo, 0)) == SYMBOL_REF \
- || GET_CODE (XEXP (xfoo, 0)) == CONST) \
- { \
- fprintf(FILE, "0("); \
- output_address(xfoo); \
- fprintf(FILE, "(sb))"); \
- } \
- else \
- { \
- fprintf (FILE, "0("); \
- output_address (xfoo); \
- putc (')', FILE); \
- } \
- } \
- break; \
- case REG: \
- fprintf (FILE, "0(%s)", reg_names[REGNO (xfoo)]); \
- break; \
- case PRE_DEC: \
- case POST_INC: \
- fprintf (FILE, "tos"); \
- break; \
- case CONST_INT: \
- fprintf (FILE, "$%d", INTVAL (xfoo)); \
- break; \
- default: \
- output_address (xfoo); \
- break; \
- } \
- } \
- else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode) \
- { \
- char buf[50]; \
- REAL_VALUE_TYPE rval; \
- REAL_VALUE_FROM_CONST_DOUBLE(rval, XV); \
- REAL_VALUE_TO_DECIMAL (rval, "%.20e", buf); \
- if (GET_MODE (XV) == SFmode) \
- fprintf (FILE, "$0e%s", buf); \
- else if (GET_MODE (XV) == DFmode) \
- fprintf (FILE, "$0d%s", buf); \
- else \
- abort(); \
- } \
- else output_addr_const (FILE, X); \
-} while (0)
-
-#endif /* UTEK_ASM */
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR)
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- PC532 with National 32532, running Mach 3.0.
- Copyright (C) 1992, 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "ns32k/pc532.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dns32532 -DPC532 -DMACH=1 -Asystem=unix -Asystem=mach -Acpu=ns32k -Amachine=ns32k"
-
-/* There's a bug in the setjmp implementation that strikes
- if the caller of setjmp doesn't have a frame pointer. */
-#undef FRAME_POINTER_REQUIRED
-#define FRAME_POINTER_REQUIRED current_function_calls_setjmp
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- PC532 with National 32532, running Minix.
- Works with pc532 Minix 1.5hybrid.
- Copyright (C) 1990, 1999 Free Software Foundation, Inc.
-
- Derived from SEQUENT NS32000, written originally
- by Bruce Culbertson <culberts@hplabs.hp.com>,
- hacked for easier fit in gcc by Jyrki Kuoppala <jkp@cs.hut.fi>.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "ns32k/pc532.h"
-
-/* Minix has crtso.o instead of crt0.o */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{pg:gcrtso.o%s}%{!pg:%{p:mcrtso.o%s}%{!p:crtso.o%s}}"
-
-/* our setjmp doesn't save registers, so we must tell gcc to save
- call-saved-regs in a function calling setjmp */
-
-#define NON_SAVING_SETJMP (current_function_calls_setjmp)
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- PC532 with National 32532.
- Copyright (C) 1990, 1994 Free Software Foundation, Inc.
- Contributed by Jukka Virtanen <jtv@hut.fi>, Jyrki Kuoppala <jkp@cs.hut.fi>,
- Tatu Yl|nen <ylo@ngs.fi>, Johannes Helander <jvh@cs.hut.fi>.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "ns32k/ns32k.h"
-
-/* Compile for the floating point unit & 32532 by default;
- also presume SB is zero and no bitfield instructions */
-
-#define TARGET_DEFAULT (1 + 24 + 64)
-
-/* Write DBX debugging info for gdb to read */
-
-#define DBX_DEBUGGING_INFO
-
-/* Use the re-entrant and potentially faster method */
-
-#undef PCC_STATIC_STRUCT_RETURN
-
-/* 32-bit alignment for efficiency */
-#undef POINTER_BOUNDARY
-#define POINTER_BOUNDARY 32
-
-/* 32-bit alignment for efficiency */
-#undef FUNCTION_BOUNDARY
-#define FUNCTION_BOUNDARY 32
-
-/* 32532 spec says it can handle any alignment. Rumor from tm-ns32k.h
- tells this might not be actually true (but it's for 32032, perhaps
- National has fixed the bug for 32532). You might have to change this
- if the bug still exists. */
-
-#undef STRICT_ALIGNMENT
-#define STRICT_ALIGNMENT 0
-
-/* Maybe someone needs to know which processor we're running on */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dns32000 -Dns32532 -Dpc532 -Dunix -Asystem=unix -Acpu=ns32k -Amachine=ns32k"
-
-/* Use pc relative addressing whenever possible,
- it's more efficient than absolute (ns32k.c)
- You have to fix a bug in gas 1.38.1 to make this work with gas,
- patch available from jkp@cs.hut.fi. */
-
-#define PC_RELATIVE
-
-/* Operand of bsr or jsr should be just the address. */
-
-#define CALL_MEMREF_IMPLICIT
-
-/* movd insns may have floating point constant operands. */
-
-#define MOVD_FLOAT_OK
+++ /dev/null
-/* Definitions of target machine for GNU compiler. SEQUENT NS32000 version.
- Copyright (C) 1987, 2000 Free Software Foundation, Inc.
- Contributed by Michael Tiemann (tiemann@mcc.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include "ns32k/ns32k.h"
-
-/* This is BSD, so it wants DBX format. */
-#define DBX_DEBUGGING_INFO
-
-/* Sequent has some changes in the format of DBX symbols. */
-#define DBX_NO_XREFS 1
-
-/* Don't split DBX symbols into continuations. */
-#define DBX_CONTIN_LENGTH 0
-
-#define TARGET_DEFAULT 9 /* 32332 with 32081 (guessing). */
-
-/* Print subsidiary information on the compiler version in use. */
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (32000, Sequent syntax)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dns32000 -Dsequent -Dunix -Asystem=unix -Asystem=bsd -Acpu=ns32k -Amachine=ns32k"
-
-/* Link with libg.a when debugging, for dbx's sake. */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* gcc should find libgcc.a itself, not ask linker to do so. */
-
-#define LINK_LIBGCC_SPECIAL
-
-/* GCC must match what sys/types.h uses for size_t. */
-
-#define SIZE_TYPE "int"
-
-/* This is how to align the code that follows an unconditional branch.
- Don't define it, since it confuses the assembler (we hear). */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP "\t.shdata"
-
-/* Control how stack adjust insns are output. */
-#define SEQUENT_ADJUST_STACK
-
-#define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC
-
-#define IMMEDIATE_PREFIX 0
-
-#define SEQUENT_ASM
-
-/* Operand of bsr or jsr should be just the address. */
-
-#define CALL_MEMREF_IMPLICIT
-
-/* Output a reg as an index rather than a base if we have the choice. */
-
-#define INDEX_RATHER_THAN_BASE
+++ /dev/null
-/* Definitions of target machine for GNU compiler.
- Generic Tektronix 6000 series NS32000 version.
- See ns32k/tek6100.h and ns32k/tek6200.h, which include this file.
- Copyright (C) 1990, 2000 Free Software Foundation, Inc.
- Created by Snoopy (sopwith.uucp!snoopy).
- Based on work by Mark Mason (mason@reed.bitnet,
- pyramid!unify!mason@uunet.uu.net) and Keith Packard.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Generate syntax for the UTek assembler. */
-#ifndef UTEK_ASM
-#define UTEK_ASM
-#endif
-
-/* Two flags to control how addresses are printed in assembler insns. */
-
-/* The way PUT_ABSOLUTE_PREFIX in ns32k.h works, setting it to 0 will
- * turn it off. Define ABSOLUTE_PREFIX before including ns32k.h.
- */
-#define ABSOLUTE_PREFIX 0
-#define IMMEDIATE_PREFIX '$'
-
-#include "ns32k/ns32k.h"
-
-/* Define these after ns32k.c so we will notice if gcc tries to
- * output external mode addressing. UTek's as and ld do not support
- * external mode addressing, according to Daryl McDaniel (illian.uucp!darylm).
- * Hopefully the UTek assembler will complain if gcc feeds it this stuff.
- * They don't seem to do anything, I think that gcc is not actually
- * trying to generate external mode operands.
- */
-#undef PUT_EXTERNAL_PREFIX
-#define PUT_EXTERNAL_PREFIX(arg) fprintf(arg, " Should not be using external mode under UTek. ")
-#define EXTERNAL_PREFIX '%'
-
-/* Used in ns32k.c to control syntax. */
-#define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC
-#define NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
-
-/* Used in ns32k.md to specify syntax of bsr/jsr operand. */
-#define CALL_MEMREF_IMPLICIT
-
-/* #define PC_RELATIVE */ /* Seems to break things. */
-#define BASE_REG_NEEDED /* Seems to fix problem where external mode
- * syntax was being generated.
- */
-
-/* ------------ Debugging Support ----------------------------- */
-
-/* The sdb support does not yet work with UTek. Need to teach gcc
- * how to create sdb type stabs as well as dbx style stabs.
- */
-#define DBX_DEBUGGING_INFO
-/* #define SDB_DEBUGGING_INFO */
-
-/* Act the same as the UTek complier: -g for dbx, -go for sdb.
- * This is used in toplev.c.
- */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define CC1_SPEC "{go:-gcoff}"
-#define CC1PLUS_SPEC "{go:-gcoff}"
-
-/* Sequent has some changes in the format of DBX symbols. */
-#define DBX_NO_XREFS 1
-
-/* Don't split DBX symbols into continuations. */
-#define DBX_CONTIN_LENGTH 0
-
-/* ------------------------------------------- */
-
-#define TARGET_DEFAULT 1
-
-/* These control the C++ compiler somehow. */
-#define FASCIST_ASSEMBLER
-#define USE_COLLECT
-
-/* Print subsidiary information on the compiler version in use. */
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (ns32k, UTek syntax)");
-
-/* The tek6100.h and tek6200.h files add stratos or merlin respectively. */
-
-#define CPP_PREDEFINES_Tek6000 \
- "-Dns16000 -Dns32000 -Dns32k -Dns32016 -DUTek -DUTEK -Dbsd -DBSD \
- -Asystem=unix -Asystem=bsd -Acpu=ns32k -Amachine=ns32k"
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES CPP_PREDEFINES_Tek6000
-
-/* This is how to align the code that follows an unconditional branch.
- Don't define it, since it confuses the assembler (we hear). */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP "\t.shdata"
-
-#ifdef UTEK_ASM
-
-/* UTek assembler needs "ret $0", not "ret 0". */
-#undef TRANSFER_FROM_TRAMPOLINE
-#define TRANSFER_FROM_TRAMPOLINE \
-void \
-__transfer_from_trampoline () \
-{ \
- asm ("___trampoline:"); \
- asm ("movd 16(r2),tos"); \
- asm ("movd 12(r2),r2"); \
- asm ("ret $0"); \
-}
-
-#endif /* UTEK_ASM */
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR)
-
-/* The UTek library supplies bcopy() and friends, not memcpy(). */
-#ifdef TARGET_MEM_FUNCTIONS
-#undef TARGET_MEM_FUNCTIONS
-#endif
+++ /dev/null
-#include "ns32k/tek6000.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dns32000 -Dns32k -Dns16000 -Dns32016 -DUTek -DUTEK -Dbsd -DBSD -Dstratos \
- -Asystem=unix -Asystem=bsd -Acpu=ns32k -Amachine=ns32k"
-
+++ /dev/null
-#include "ns32k/tek6000.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dns32000 -Dns32k -Dns16000 -Dns32016 -DUTek -DUTEK -Dbsd -DBSD -Dmerlin \
- -Asystem=unix -Asystem=bsd -Acpu=ns32k -Amachine=ns32k"
-
+++ /dev/null
-! lib1funcs.S for picoJava.
-! Copyright (C) 2000, 2001 Free Software Foundation, Inc.
-!
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-!
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file into combinations with other programs,
-! and to distribute those combinations without any restriction coming
-! from the use of this file. (The General Public License restrictions
-! do apply in other respects; for example, they cover modification of
-! the file, and distribution when not linked into a combine
-! executable.)
-!
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-! General Public License for more details.
-!
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING. If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-!
-
-
-#ifdef Lvhelper
-
-! The vhelper copies unnamed args in a varargs function from the
-! opstack onto the aggregate stack. It is a bit tricky since the
-! opstack does not exist in real memory, so can not have its address taken,
-! and since the opstack is being played with, there is nowhere to stick
-! the temporaries.
-
- .globl __vhelper
-__vhelper:
-
-
-! incoming
-! vars-> named0
-! named1
-! ...
-! unnamed0
-! unnamed1
-! ...
-! pc
-! vars
-! #named
-! return pc
-
- ! work out total size everything below the named args and
- ! allocate that space on the aggregate stack + 3 extra words
- ! for some temps.
- ! g0 = old g0
- ! g0+4 = vars
- ! g0+8 = pc
- ! g0+12 = last unnamed arg
- ! ....
-
- write_global1
- write_global2
-
- ! tos = #named args provided by callee.
-
- ! move down the aggstack to make room for all the unnamed args
- ! and the 12 bytes of extra stuff we have to pay attention to.
- ! g0 = old_g0 - ((vars - optop) + named_bytes + 12) - stuff we just pushed
-
- ! build new global0
- read_global0
- read_vars
- read_optop
- isub ! tos = vars - optop (# bytes in all args)
- bipush 4
- isub ! subtract out fudge for current stuff on stack.
- read_global2
- isub ! subtract out # words named.
- isub
-
- dup
- dup
- ! store old global0 in new global0 spot.
-
- read_global0
- swap
- store_word
-
- ! store new global0 value into global0
- write_global0
-
- ! work out address to stop copying, which is vars - #named args bytes
- ! but since we will have pushed stuff onto the stack when the comparison
- ! is made, adjust by the fudge factor.
- read_vars
- read_global2
- bipush 12
- iadd
- isub
-
- ! optop= finish, vars, pc, ...
- ! now pop off args from the opstack and copy to aggstack till all done.
- ! during the loop the opstack looks like
- ! (optop_finish_addr) (destination_addr) (named_n) (named_n-1) ....
- ! each iteration pops off one more element.
-
-
-again:
- dup_x2
- read_optop
- if_icmpeq done
- iconst_4
- iadd
- dup_x2
- store_word
- goto again
-
-done:
- dup2_x1 ; pop2 ; pop !leave pointer on top.
-
- ! return to caller with varargs pointer as
- ! the next argument and the restoring global0 as the next.
-
- read_global0 ; load_word
-
- ! restore returning pc and vars
- read_global0 ; bipush 8; iadd; load_word
- read_global0 ; bipush 4; iadd; load_word
-
- ! return to caller.
- read_global1
- write_pc
-#endif
-
-
-#ifdef __LITTLE_ENDIAN__
-#define AL iload_1
-#define AH iload_0
-#define BL iload_3
-#define BH iload_2
-#else
-#define AL iload_0
-#define AH iload_1
-#define BL iload_2
-#define BH iload_3
-#endif
-#ifdef Lpjucmpdi2
-
-! like ucmpdi2, but returns <0,0,>0 depending on comparison input.
-! and returns answer on the stack, not in global1. - much like an
-! actual lucmp instruction would do if there was one.
-! big little
-!
-! vars-> 0 a low high
-! 1 a high low
-! 2 b low high
-! 3 b high low
-!
-! compares a to b
-! a > b return 1
-! a = b return 0
-! a < b return -1
-
- .globl __pjucmpdi2
-__pjucmpdi2:
-
-! first see if we can compare the numbers using
-! the signed instruction.
-
- AH
- BH
- if_icmpne high_words_diff
- AL
- BL
- iucmp
- return1
-
-! and low word if high word is equal.
-
-high_words_diff:
- AH
- BH
- iucmp
- return1
-#endif
+++ /dev/null
-/* Definitions for a picoJava Linux-based GNU system.
- Copyright (C) 2000, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* contributed by Steve Chamberlain, of Transmeta. sac@pobox.com. */
-
-#define TARGET_LITTLE_ENDIAN_DEFAULT 1
-
-#undef CPP_PREDEFINES
-#undef STARTFILE_SPEC
-#undef ENDFILE_SPEC
-
-#define CPP_PREDEFINES "-D__ELF__ -Dunix -D__pj__ -D__gnu_linux__ -Dlinux -Asystem=posix"
-#define STARTFILE_SPEC "crt1.o%s crti.o%s crtbegin.o%s"
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-#undef WCHAR_TYPE_SIZE
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
+++ /dev/null
-/* Prototypes for pj.c functions used in the md file & elsewhere.
- Copyright (C) 2000 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-void pj_expand_prologue PARAMS ((void));
-void pj_expand_epilogue PARAMS ((void));
-void pj_asm_output_opcode PARAMS ((FILE *, const char *));
-
-#ifdef RTX_CODE
-extern rtx pj_cmp_op0;
-extern rtx pj_cmp_op1;
-extern enum machine_mode pj_cmp_mode;
-extern int pj_stuff_on_line;
-extern const char *pj_standard_float_constant PARAMS ((rtx));
-extern int pj_source_operand PARAMS ((rtx op, enum machine_mode mode));
-extern int pj_signed_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern int pj_unsigned_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern rtx pj_workout_arg_words PARAMS ((rtx, rtx));
-extern void pj_machine_dependent_reorg PARAMS ((rtx));
-extern void pj_print_operand PARAMS ((FILE * stream, rtx x, int code));
-extern const char *pj_output_addsi3 PARAMS ((rtx * operands));
-
-#ifdef TREE_CODE
-extern rtx pj_expand_builtin_va_arg PARAMS ((tree valist, tree type));
-extern rtx pj_function_incoming_arg PARAMS ((CUMULATIVE_ARGS * args_so_far,
- enum machine_mode promote_mode,
- tree passed_type,
- int named_arg));
-#endif
-#endif
+++ /dev/null
-/* Output routines for GCC for picoJava II
- Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Contributed by Steve Chamberlain (sac@pobox.com), of Transmeta. */
-
-/* The picoJava architecture doesn't have general registers, it has an
- operand stack. Any of the first 256 words on the operand stack between
- the locations indicated by the vars register and the optop register
- are accessible with one instruction, almost as if they were registers.
- The opstack isn't aliased into memory, so deferecencing address of
- something on the opstack is impossible.
-
- Small scalar incoming arguments to a function arrive on the operand
- stack, large scalars and aggregates arrive in the `aggregate'
- stack. The aggregate stack lives in normal memory.
-
-
- just before a call after the call insn and frame setup.
-
- vars-> ....
-
- arg-5 vars->arg-5
- arg-4 arg-4
- arg-3 arg-3
- arg-2 arg-2
- arg-1 arg-1
- arg-0 arg-0
- target-addr old-vars
- #arg words old-pc
- optop-> saved globals
- local-0
- local-1
- ....
- optop->
-
- This port generates code for a machine with 32 general purpose
- registers, and on output changes the references to the fake registers
- into offsets from the vars register. Because the opstack grows
- downwards and all indexes are negated, some care has to be taken here
- to deal with endian problems; for example after a call on a little endian
- machine, an incoming DImode argument of value 0x1122334455667788 in
- `register 0', would live on the opstack like this:
-
- vars - 0 0x11223344
- vars - 4 0x55667788
- vars - 8 old-vars
- vars - 12 old-pc
-
- The picoJava instructon to read and put that onto the opstack as a
- DImode value is `lload 0', yet the least significant word lives at
- vars - 4, for which the instruction is `iload 1'. The incoming
- argument code remembers which arguments arrive swapped in the
- CUMULATIVE_ARGS structure. The information is used to fill in
- pj_si_vars_offset_vec and pj_di_vars_offset_vec during the prologue
- printing.
-
- Outgoing arguments are collected in fake `outgoing' registers, or
- in the aggregate stack. The emitted code to write into an outgoing
- register does nothing, which leaves the expression to be written on
- the top of the opstack. GCC always evaluates arguments in the right
- order, so nothing more needs to be done. */
-
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "tree.h"
-#include "tm_p.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "except.h"
-#include "function.h"
-#include "recog.h"
-#include "expr.h"
-#include "optabs.h"
-#include "toplev.h"
-#include "basic-block.h"
-#include "ggc.h"
-#include "target.h"
-#include "target-def.h"
-
-/* Compare insns in pj.md store the information needed to generate
- branch instructions here. */
-rtx pj_cmp_op0;
-rtx pj_cmp_op1;
-enum machine_mode pj_cmp_mode;
-
-static void pj_output_rval PARAMS ((rtx, enum machine_mode, rtx));
-static void pj_output_store_into_lval PARAMS ((enum machine_mode mode, rtx op));
-static void pj_output_push_int PARAMS ((int));
-static void pj_output_load PARAMS ((enum machine_mode, int));
-static void pj_output_inc PARAMS ((rtx, int));
-static void pj_output_cnv_op PARAMS ((enum insn_code, rtx));
-static char mode_to_char PARAMS ((enum machine_mode));
-static void pj_output_varidx PARAMS ((enum machine_mode, int, int));
-static void pj_print_cond PARAMS ((enum rtx_code));
-static rtx *unique_src_operand PARAMS ((rtx *, rtx));
-
-/* These vectors turn a register number into an offset from the vars
- pointer register. */
-short pj_si_vars_offset_vec[FIRST_PSEUDO_REGISTER];
-short pj_di_vars_offset_vec[FIRST_PSEUDO_REGISTER];
-short pj_debugreg_renumber_vec[FIRST_PSEUDO_REGISTER];
-
-/* Number of fake registers in the frame, used by prologue and epilogue
- code. */
-static int nfakes;
-
-/* Whether anything has been printed to the current assembly output
- line. */
-int pj_stuff_on_line;
-\f
-/* Initialize the GCC target structure. */
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* printf to the asm_out_file, with special format control characters
- for decoding operands.
-
- %* - start of opcode
- %d,%x,%c,%s - as printf
- %X - address constant.
- %<alpha><digit> - operand <digit> passed to pj_print_operand with code <alpha>. */
-
-static void
-pj_printf VPARAMS ((const char *template, ...))
-{
- register int c;
- int ops_read = 0;
- rtx operands[10];
-
- VA_OPEN (argptr, template);
- VA_FIXEDARG (argptr, const char *, template);
-
- while ((c = *template++))
- {
- int was_stuff_on_line = pj_stuff_on_line;
- pj_stuff_on_line = 1;
- switch (c)
- {
- case '\n':
- putc (c, asm_out_file);
- pj_stuff_on_line = 0;
- break;
- default:
- putc (c, asm_out_file);
- break;
- case '%':
- {
- switch (*template)
- {
- case '%':
- putc ('%', asm_out_file);
- template++;
- pj_stuff_on_line = 1;
- break;
- case '*':
- /* Marks start of opcode, tab out. */
- if (was_stuff_on_line)
- fprintf (asm_out_file, "; ");
- template++;
- break;
- case 'd':
- template++;
- fprintf (asm_out_file, "%d", va_arg (argptr, int));
- break;
- case 'x':
- template++;
- fprintf (asm_out_file, "%x", va_arg (argptr, int));
- break;
- case 'c':
- template++;
- fprintf (asm_out_file, "%c", va_arg (argptr, int));
- break;
- case 's':
- template++;
- fputs (va_arg (argptr, const char *), asm_out_file);
- break;
- case 'X':
- template++;
- output_addr_const (asm_out_file, va_arg (argptr, rtx));
- break;
- default:
- {
- int code = 0;
- rtx send;
-
- if (ISALPHA (*template))
- code = *template++;
- if (ISDIGIT (*template))
- {
- int num = atoi (template);
- template++;
- while (ops_read <= num)
- operands[ops_read++] = va_arg (argptr, rtx);
- send = operands[num];
- }
- else
- send = va_arg (argptr, rtx);
-
- /* A null means leave the word on the stack, so there's
- no need to do anything for that. */
-
- if (send)
- pj_print_operand (asm_out_file, send, code);
- }
- }
- }
- }
- }
- VA_CLOSE (argptr);
-}
-
-/* Output code to efficiently push a single word integer constant onto
- the opstack. */
-
-static void
-pj_output_push_int (val)
- int val;
-{
- int low = ((val & 0x8000) ? ~0xffff : 0) | (val & 0xffff);
-
- if (low == -1)
- pj_printf ("%*iconst_m1");
- else if (low >= 0 && low <= 5)
- pj_printf ("%*iconst_%d", low);
- else if (low >= -128 && low < 128)
- pj_printf ("%*bipush %d", low);
- else
- pj_printf ("%*sipush %d", low);
-
- if ((low & 0xffff0000) != (val & 0xffff0000))
- pj_printf ("%*sethi 0x%x", (val >> 16) & 0xffff);
-}
-
-/* Output code to add a constant to the value on the top of the
- opstack. */
-
-static void
-pj_output_print_add_k (int size)
-{
- if (size >= 0)
- {
- pj_output_push_int (size);
- pj_printf ("%*iadd");
- }
- else
- {
- pj_output_push_int (-size);
- pj_printf ("%*isub");
- }
-}
-
-/* Output code to load the value pointed to by the top of stack onto
- the stack. */
-
-static void
-pj_output_load (mode, uns)
- enum machine_mode mode;
- int uns;
-{
- int i;
- switch (GET_MODE_SIZE (mode))
- {
- case 1:
- pj_printf (uns ? "%*load_ubyte" : "%*load_byte");
- break;
- case 2:
- pj_printf (uns ? "%*load_char" : "%*load_short");
- break;
- case 8:
- if (TARGET_TM_EXTENSIONS)
- {
- pj_printf ("%*tm_load_long");
- break;
- }
- /* Fall through. */
- default:
- for (i = GET_MODE_SIZE (mode); i > 4; i -= 4)
- {
- pj_printf ("%*dup");
- pj_output_print_add_k (i - 4);
- pj_printf ("%*load_word");
- pj_printf ("%*swap");
- }
- pj_printf ("%*load_word");
- }
-}
-
-/* Output code to increment the provided lval operand. */
-
-static void
-pj_output_inc (op, size)
- rtx op;
- int size;
-{
- if (STACK_REG_RTX_P (op))
- pj_printf ("%*iinc %d,%d", pj_si_vars_offset_vec[REGNO (op)], size);
- else
- {
- pj_output_rval (op, SImode, 0);
- pj_output_push_int (size);
- pj_printf ("%*iadd");
- pj_output_store_into_lval (SImode, op);
- }
-}
-
-/* Output the text for a conversion operator. */
-
-static void
-pj_output_cnv_op (e, op)
- enum insn_code e;
- rtx op;
-{
- pj_printf ((const char *) insn_data[(int) e].output, 0, XEXP (op, 0));
-}
-
-/* Turn a machine_mode into an opcode modifier chararacter. */
-
-static char
-mode_to_char (mode)
- enum machine_mode mode;
-{
- switch (mode)
- {
- case QImode:
- case HImode:
- case SImode:
- return 'i';
- break;
- case DImode:
- return 'l';
- break;
- case DFmode:
- return 'd';
- break;
- case SFmode:
- return 'f';
- break;
- default:
- abort ();
- }
-}
-
-/* Output an index off the var register. If we're moving an 8 byte
- value then reduce the index, since the picoJava instruction loading
- the value uses the index of the highest part of the register as
- it's name. */
-
-static void
-pj_output_varidx (mode, do_store, idx)
- enum machine_mode mode;
- int do_store;
- int idx;
-{
- pj_printf ("%*%c%s%c%d",
- mode_to_char (mode),
- do_store ? "store" : "load",
- (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
- && idx <= 3 ? '_' : ' ', idx);
-}
-
-/* Output an rvalue expression. */
-
-static void
-pj_output_rval (op, mode, outer_op)
- rtx op;
- enum machine_mode mode;
- rtx outer_op;
-{
- enum rtx_code code = GET_CODE (op);
-
- optab tab;
-
- if (code == DIV && GET_MODE_CLASS (mode) == MODE_INT)
- tab = sdiv_optab;
- else
- tab = code_to_optab[code];
-
- if (code == PLUS)
- {
- pj_output_rval (XEXP (op, 0), mode, op);
- pj_output_rval (XEXP (op, 1), mode, op);
- pj_printf ("%*%cadd", mode_to_char (mode));
- }
- else if (tab && tab->handlers[mode].insn_code != CODE_FOR_nothing)
- {
- const char *const template =
- (const char *) insn_data[tab->handlers[mode].insn_code].output;
- if (code == NEG)
- pj_printf (template, 0, XEXP (op, 0));
- else
- pj_printf (template, 0, XEXP (op, 0), XEXP (op, 1));
- }
- else
- switch (GET_CODE (op))
- {
- case PC:
- fprintf (asm_out_file, " pc ");
- break;
-
- case CONST:
- pj_output_rval (XEXP (op, 0), mode, op);
- break;
-
- case MEM:
- pj_output_rval (XEXP (op, 0), Pmode, op);
- pj_output_load (mode, 0);
- break;
-
- case SYMBOL_REF:
- pj_printf ("%*ipush %X", op);
- break;
-
- case REG:
- switch (mode)
- {
- case SImode:
- case SFmode:
- case HImode:
- case QImode:
- if (pj_si_vars_offset_vec[REGNO (op)] >= 0)
- pj_output_varidx (mode, 0, pj_si_vars_offset_vec[REGNO (op)]);
- else
- pj_printf ("%*read_%s", reg_names[REGNO (op)]);
- break;
- case DImode:
- case DFmode:
- if (pj_di_vars_offset_vec[REGNO (op)] >= 0)
- pj_output_varidx (mode, 0, pj_di_vars_offset_vec[REGNO (op)]);
- else
- switch (REGNO (op))
- {
- case G1_REG:
- pj_printf ("%*read_global2");
- pj_printf ("%*read_global1");
- break;
-
- /* A 64 bit read of global0 gives global0 and
- optop. */
- case G0_REG:
- pj_printf ("%*read_optop");
- pj_printf ("%*read_global0");
- break;
-
- default:
- abort ();
- }
- break;
- default:
- abort ();
- }
- break;
-
- case CONST_DOUBLE:
- pj_printf (pj_standard_float_constant (op));
- break;
-
- case CONST_INT:
- if (mode == SImode || mode == HImode || mode == QImode)
- pj_output_push_int (INTVAL (op));
- else if (mode == DImode)
- {
- int v = INTVAL (op);
- if (v == 1)
- pj_printf ("%*lconst_1", 0);
- else if (v == 0)
- pj_printf ("%*lconst_0", 0);
- else
- {
- rtx hi = GEN_INT (v < 0 ? -1 : 0);
- rtx lo = op;
- pj_output_rval (TARGET_LITTLE_ENDIAN ? hi : lo, SImode, op);
- pj_output_rval (TARGET_LITTLE_ENDIAN ? lo : hi, SImode, op);
- }
- }
- else
- abort ();
- break;
-
- case FLOAT_TRUNCATE:
- pj_printf ("%S0%*d2f", XEXP (op, 0));
- break;
- case LABEL_REF:
- pj_printf ("%*ipush %X", XEXP (op, 0));
- break;
-
- case SUBREG:
- pj_output_rval (alter_subreg (&op), mode, outer_op);
- break;
-
- case POST_INC:
- pj_output_rval (XEXP (op, 0), mode, op);
- pj_output_inc (XEXP (op, 0), GET_MODE_SIZE (GET_MODE (outer_op)));
- break;
-
- case POST_DEC:
- pj_output_rval (XEXP (op, 0), mode, op);
- pj_output_inc (XEXP (op, 0), -GET_MODE_SIZE (GET_MODE (outer_op)));
- break;
-
- case PRE_INC:
- pj_output_inc (XEXP (op, 0), GET_MODE_SIZE (GET_MODE (outer_op)));
- pj_output_rval (XEXP (op, 0), mode, op);
- break;
-
- case PRE_DEC:
- if (OPTOP_REG_RTX_P (XEXP (op, 0)))
- pj_output_rval (XEXP (op, 0), mode, op);
- else if (STACK_REG_RTX_P (XEXP (op, 0)))
- {
- pj_output_inc (XEXP (op, 0),
- -GET_MODE_SIZE (GET_MODE (outer_op)));
- pj_output_rval (XEXP (op, 0), mode, op);
- }
- else
- {
- pj_printf ("%S0", XEXP (op, 0));
- pj_output_print_add_k (-GET_MODE_SIZE (GET_MODE (outer_op)));
- pj_printf ("%*dup%R0", XEXP (op, 0));
- }
- break;
-
- case FIX:
- pj_output_cnv_op (fixtrunctab[GET_MODE (XEXP (op, 0))][mode][0], op);
- break;
-
- case FLOAT:
- if (mode == DFmode && GET_CODE (XEXP (op, 0)) == CONST_INT)
- pj_output_cnv_op (floattab[mode][SImode][0], op);
- else
- pj_output_cnv_op (floattab[mode][GET_MODE (XEXP (op, 0))][0], op);
- break;
-
- case FLOAT_EXTEND:
- case SIGN_EXTEND:
- /* Sign extending from a memop to register is automatic. */
- if (mode == SImode && GET_CODE (XEXP (op, 0)) == MEM)
- pj_output_rval (XEXP (op, 0), GET_MODE (XEXP (op, 0)), op);
- else
- pj_output_cnv_op (extendtab[mode][GET_MODE (XEXP (op, 0))][0], op);
- break;
-
- case ZERO_EXTEND:
- pj_output_cnv_op (extendtab[mode][GET_MODE (XEXP (op, 0))][1], op);
- break;
-
- default:
- abort ();
- break;
- }
-}
-
-/* Store the top of stack into the lval operand OP. */
-
-static void
-pj_output_store_into_lval (mode, op)
- enum machine_mode mode;
- rtx op;
-{
- if (GET_CODE (op) == REG)
- {
- int rn = REGNO (op);
-
- /* Outgoing values are left on the stack and not written
- anywhere. */
- if (!OUTGOING_REG_RTX_P (op))
- {
- switch (GET_MODE (op))
- {
- case SImode:
- case QImode:
- case HImode:
- case SFmode:
- if (pj_si_vars_offset_vec[rn] >= 0)
- pj_output_varidx (mode, 1, pj_si_vars_offset_vec[rn]);
- else
- pj_printf ("%*write_%s", reg_names[rn]);
- break;
- case DImode:
- case DFmode:
- if (pj_di_vars_offset_vec[rn] >= 0)
- pj_output_varidx (mode, 1, pj_di_vars_offset_vec[rn]);
- else
- switch (rn)
- {
- case G1_REG:
- pj_printf ("%*write_global1");
- pj_printf ("%*write_global2");
- break;
- default:
- abort ();
- }
- break;
- default:
- abort ();
- }
- }
- }
- else
- {
- pj_output_rval (XEXP (op, 0), Pmode, op);
-
- switch (GET_MODE_SIZE (mode))
- {
- case 1:
- pj_printf ("%*store_byte", 0);
- break;
- case 2:
- pj_printf ("%*store_short", 0);
- break;
- case 8:
- if (TARGET_TM_EXTENSIONS)
- {
- pj_printf ("%*tm_store_long");
- break;
- }
- /* Fall through. */
- default:
- {
- int i;
- for (i = GET_MODE_SIZE (mode); i > 4; i -= 4)
- {
- pj_printf ("%*dup_x1", 0);
- pj_printf ("%*store_word", 0);
- pj_printf ("%*iconst_4", 0);
- pj_printf ("%*iadd", 0);
- }
- }
- pj_printf ("%*store_word", 0);
- break;
- }
- }
-}
-
-/* Print a condition, unsigned and signed have the same text because
- the unsigned operands have been run through icmp first. */
-
-static void
-pj_print_cond (code)
- enum rtx_code code;
-{
- switch (code)
- {
- case EQ:
- fputs ("eq", asm_out_file);
- break;
- case NE:
- fputs ("ne", asm_out_file);
- break;
- case GT:
- case GTU:
- fputs ("gt", asm_out_file);
- break;
- case GE:
- case GEU:
- fputs ("ge", asm_out_file);
- break;
- case LT:
- case LTU:
- fputs ("lt", asm_out_file);
- break;
- case LE:
- case LEU:
- fputs ("le", asm_out_file);
- break;
- default:
- abort ();
- }
-}
-/* Print operand X (an rtx) in assembler syntax to file STREAM
- according to modifier CODE.
-
- C emit the first part of a Check_call pseudop.
- D emit operand, if no mode, assume DImode.
- E emit the second part of a check_call pseudop.
- I print the XEXP (X, 0) Inside of the operand.
- J print Just the integer or register part of an operand, for iinc.
- P emit source is SI padded to DI with 0, used for unsigned mod and divide.
- R emit the operand as an lval Result.
- S emit Source operand, if no mode, assume SImode.
- X nan choice suffix for floating point comparision.
- Y condition name from op.
- Z Y, reversed.
- * marks start of opcode. */
-
-void
-pj_print_operand (stream, x, code)
- FILE *stream;
- rtx x;
- int code;
-{
- static int last_call_known;
- switch (code)
- {
- case 'C':
- if (GET_CODE (x) == SYMBOL_REF)
- {
- last_call_known = 1;
- pj_printf ("%*.check_call %0", x);
- }
- else
- last_call_known = 0;
- break;
-
- case 'D':
- pj_output_rval (x,
- GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x),
- NULL_RTX);
- break;
-
- case 'E':
- if (last_call_known)
- pj_printf (",%d", INTVAL (x));
- break;
-
- case 'I':
- pj_output_rval (XEXP (x, 0), GET_MODE (XEXP (x, 0)), NULL_RTX);
- break;
-
- case 'J':
- if (GET_CODE (x) == CONST_INT)
- pj_printf ("%d", INTVAL (x));
- else if (GET_CODE (x) == REG)
- pj_printf ("%d", pj_si_vars_offset_vec[REGNO (x)]);
- else
- abort ();
- break;
-
- case 'P':
- if (TARGET_LITTLE_ENDIAN)
- pj_printf ("%*iconst_0", 0);
- pj_output_rval (x,
- GET_MODE (x) == VOIDmode ? SImode : GET_MODE (x),
- NULL_RTX);
- if (!TARGET_LITTLE_ENDIAN)
- pj_printf ("%*iconst_0", 0);
- break;
-
- case 'R':
- pj_output_store_into_lval (GET_MODE (x), x);
- break;
-
- case 'S':
- pj_output_rval (x,
- GET_MODE (x) == VOIDmode ? SImode : GET_MODE (x),
- NULL_RTX);
- break;
-
- case 'X':
- fputc (GET_CODE (x) == LT || GET_CODE (x) == LE ? 'g' : 'l', stream);
- break;
-
- case 'Y':
- pj_print_cond (GET_CODE (x));
- break;
-
- case 'Z':
- pj_print_cond (reverse_condition (GET_CODE (x)));
- break;
-
- case '*':
- pj_printf ("%*");
- break;
-
- default:
- output_addr_const (stream, x);
- break;
- }
-}
-\f
-/* Return in an rtx the number of words pushed onto the optop to be
- used as the word count in a call insn. (NEXT_ARG_REG is NULL when
- called from expand_builtin_apply). */
-
-rtx
-pj_workout_arg_words (stack_size, next_arg_reg)
- rtx stack_size ATTRIBUTE_UNUSED;
- rtx next_arg_reg;
-{
- return GEN_INT ((next_arg_reg ? REGNO (next_arg_reg) - O0_REG : 0) + 2);
-}
-
-/* Handle the INCOMING_FUNCTION_ARG macro.
- Determine where to put an argument to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis). */
-
-rtx
-pj_function_incoming_arg (cum, mode, passed_type, named_arg)
- CUMULATIVE_ARGS *cum;
- enum machine_mode mode;
- tree passed_type ATTRIBUTE_UNUSED;
- int named_arg ATTRIBUTE_UNUSED;
-{
- int arg_words = PJ_ARG_WORDS (mode);
-
- /* If the whole argument will fit into registers, return the first
- register needed. Also fill in the arg_adjust information so that
- we can work out the right offset to use when looking at the
- insides of a DI or DF value. */
-
- if (cum->total_words + arg_words <= ARGS_IN_REGS)
- {
- int i;
- if (mode == DImode || mode == DFmode)
- {
- cum->arg_adjust[cum->total_words + 0] = 1;
- cum->arg_adjust[cum->total_words + 1] = -1;
- }
- else
- for (i = 0; i < arg_words; i++)
- cum->arg_adjust[cum->total_words + i] = 0;
-
- return gen_rtx (REG, mode, I0_REG + cum->total_words);
- }
- return NULL_RTX;
-}
-
-/* Output code to add two SImode values. Deals carefully with the the common
- case of moving the optop. */
-
-const char *
-pj_output_addsi3 (operands)
- rtx *operands;
-{
- if (OPTOP_REG_RTX_P (operands[0]) && OPTOP_REG_RTX_P (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) >= -32 && INTVAL (operands[2]) <= 32)
- {
- static struct
- {
- const char *two;
- const char *one;
- }
- name[2] =
- {
- { "pop2", "pop"},
- { "lconst_0", "iconst_0"}
- };
- int size = INTVAL (operands[2]);
- int d = 0;
-
- if (size < 0)
- {
- d = 1;
- size = -size;
- }
-
- for (; size >= 8; size -= 8)
- output_asm_insn (name[d].two, 0);
-
-
- if (size > 0)
- output_asm_insn (name[d].one, 0);
-
- return "";
- }
-
- if (STACK_REG_RTX_P (operands[0])
- && rtx_equal_p (operands[0], operands[1])
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) <= 127)
- {
- return "iinc %J0,%J2";
- }
-
- return "%S1%S2%*iadd%R0";
-}
-\f
-/* Generate rtl for the prologue of the current function. */
-
-void
-pj_expand_prologue ()
-{
- int i;
- int off = 0;
- int arg_words = current_function_args_info.named_words;
-
- memset (pj_si_vars_offset_vec, -1, sizeof (pj_si_vars_offset_vec));
- memset (pj_di_vars_offset_vec, -1, sizeof (pj_di_vars_offset_vec));
-
- /* Work out the register numbers of the named arguments. */
- for (i = 0; i < current_function_args_info.named_words; i++)
- {
- pj_debugreg_renumber_vec[I0_REG + i]
- = off + R0_REG + current_function_args_info.arg_adjust[i];
- pj_si_vars_offset_vec[I0_REG + i]
- = off + current_function_args_info.arg_adjust[i];
- pj_di_vars_offset_vec[I0_REG + i] = off;
- off++;
- }
-
- if (current_function_varargs || current_function_stdarg)
- {
- /* If the function is varadic we need to call the vhelper
- function. vhelper pops off the unnamed argument words from
- the opstack and puts them onto the the aggregate stack. The
- unnamed words are replacedwith two extra arguments, a pointer
- to the aggreagate stack for the first vararg and the original
- global0 value. */
-
- emit_insn (gen_varargs (GEN_INT (arg_words * 4)));
- pj_si_vars_offset_vec[VA_REG] = off++;
- off++;
- arg_words += 2;
- }
-
- /* Skip over the return pc and old vars in the frame. */
- off += 2;
-
- /* Work out the register numbers and offsets from the var pointer
- for the normal registers. */
- nfakes = 0;
-
- for (i = LAST_I_REG; i >= R0_REG; i--)
- if (regs_ever_live[i] && pj_si_vars_offset_vec[i] == -1)
- {
- nfakes++;
- pj_si_vars_offset_vec[i] = off;
- pj_di_vars_offset_vec[i] = off - 1;
- pj_debugreg_renumber_vec[i] = off + R0_REG;
- off++;
- }
-
- if (TARGET_TEST)
- {
- fprintf (asm_out_file, "\n\t! args %d, size %d, fakes %d\n",
- arg_words,
- get_frame_size () / 4,
- nfakes);
-
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (pj_si_vars_offset_vec[i] >= 0)
- fprintf (asm_out_file, "\t!vars - %d %d: %s\n",
- pj_si_vars_offset_vec[i],
- pj_di_vars_offset_vec[i],
- reg_names[i]);
- }
-
- /* Make room on the opstack for the fake registers. */
- if (TARGET_TM_EXTENSIONS)
- RTX_FRAME_RELATED_P (emit_insn (gen_tm_frame (GEN_INT (arg_words),
- GEN_INT (nfakes)))) = 1;
- else
- RTX_FRAME_RELATED_P (emit_insn
- (gen_addsi3
- (gen_rtx_REG (SImode, OPTOP_REG),
- gen_rtx_REG (SImode, OPTOP_REG),
- GEN_INT (-nfakes * 4)))) = 1;
-
-
- if (frame_pointer_needed)
- emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
-
- if (get_frame_size ())
- RTX_FRAME_RELATED_P (emit_insn (gen_addsi3 (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT
- (-get_frame_size ())))) = 1;
-
- emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, OPTOP_REG)));
-}
-
-/* Generate rtl for the epilogue of the current function. */
-
-void
-pj_expand_epilogue ()
-{
- if (frame_pointer_needed)
- emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
- else if (get_frame_size ())
- emit_insn (gen_addsi3 (stack_pointer_rtx,
- stack_pointer_rtx, GEN_INT (get_frame_size ())));
- if (nfakes)
- emit_insn (gen_addsi3 (gen_rtx_REG (SImode, OPTOP_REG),
- gen_rtx_REG (SImode, OPTOP_REG),
- GEN_INT (nfakes * 4)));
-
-
- /* If this is a varargs function, then global0 is stashed away on
- the top of the optop stack as the last secret argument by the
- __vhelper. Pop off the va pointer provided too. */
-
- if (current_function_varargs || current_function_stdarg)
- emit_insn (gen_varargs_finish
- (GEN_INT (current_function_args_info.named_words + 1)));
-
- emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, OPTOP_REG)));
-}
-
-/* Return the opcode name for an instruction to load a standard
- floating point constant, or NULL. */
-
-const char *
-pj_standard_float_constant (op)
- rtx op;
-{
- REAL_VALUE_TYPE r;
- enum machine_mode mode = GET_MODE (op);
-
- if (GET_CODE (op) != CONST_DOUBLE || (mode != DFmode && mode != SFmode))
- return NULL;
-
- REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-
- if (REAL_VALUES_EQUAL (r, dconst0) && !REAL_VALUE_MINUS_ZERO (r))
- return mode == DFmode ? "%*dconst_0" : "%*fconst_0";
-
- if (REAL_VALUES_EQUAL (r, dconst1))
- return mode == DFmode ? "%*dconst_1" : "%*fconst_1";
-
- if (REAL_VALUES_EQUAL (r, dconst2))
- return mode == DFmode ? 0 : "%*fconst_2";
-
- return NULL;
-}
-
-/* Read the value at the current address, and decrement by the size.
- The function is interesting because we're reading from high memory to low memory
- and have to adjust the addresses of reads of 8 byte values
- accordingly. */
-
-rtx
-pj_expand_builtin_va_arg (valist, type)
- tree valist;
- tree type;
-{
- tree addr_tree, t;
- HOST_WIDE_INT align;
- HOST_WIDE_INT rounded_size;
- rtx addr;
-
- /* Compute the rounded size of the type. */
- align = PARM_BOUNDARY / BITS_PER_UNIT;
- rounded_size = (((int_size_in_bytes (type) + align - 1) / align) * align);
-
- /* Get AP. */
- addr_tree = valist;
- addr = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
- addr = copy_to_reg (addr);
-
- /* Aggregates and large scalars are passed by reference. */
- if (AGGREGATE_TYPE_P (type) || rounded_size > 8)
- {
- addr = gen_rtx_MEM (Pmode, addr);
- rounded_size = 4;
- }
-
- /* adjust address to cope with double word sizes */
- if (rounded_size > 4)
- addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (-4));
-
- /* Compute new value for AP; AP = AP - SIZE */
- t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
- build (MINUS_EXPR, TREE_TYPE (valist), valist,
- build_int_2 (rounded_size, 0)));
-
- TREE_SIDE_EFFECTS (t) = 1;
-
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
-
- return addr;
-}
-\f
-/* Return nonzero if the operand is valid as a source operand; it's
- general and it's not an outgoing argument register. */
-
-int
-pj_source_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- return !OUTGOING_REG_RTX_P (op) && general_operand (op, mode);
-}
-
-/* Return nonzero if the operator is a signed compare. */
-
-int
-pj_signed_comparison_operator (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- if (mode != GET_MODE (op))
- return 0;
-
- switch (GET_CODE (op))
- {
- case EQ:
- case NE:
- case LE:
- case LT:
- case GE:
- case GT:
- return 1;
- default:
- return 0;
- }
-}
-
-/* Return nonzero if the operator is an unsigned compare. */
-
-int
-pj_unsigned_comparison_operator (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- if (mode != GET_MODE (op))
- return 0;
-
- switch (GET_CODE (op))
- {
- case GTU:
- case GEU:
- case LTU:
- case LEU:
- return 1;
- default:
- return 0;
- }
-}
-\f
-/* Helper function for pj_machine_dependent_reorg. Find the one
- instance of register OP in the source part of PAT. If there are no
- copies return NULL, if there are more than one, return NOT_UNIQUE. */
-
-#define NOT_UNIQUE (&const0_rtx)
-
-static rtx *
-unique_src_operand (pat, reg)
- rtx *pat;
- rtx reg;
-{
- register rtx *result = 0;
- register const char *fmt;
- register int i;
- register int j;
-
- if (GET_CODE (*pat) == SET)
- {
- if (GET_CODE (XEXP (*pat, 0)) == MEM)
- result = unique_src_operand (&XEXP (SET_DEST (*pat), 0), reg);
- pat = &SET_SRC (*pat);
- }
-
- if (GET_CODE (*pat) == REG && REGNO (*pat) == REGNO (reg))
- return pat;
-
- fmt = GET_RTX_FORMAT (GET_CODE (*pat));
- for (i = GET_RTX_LENGTH (GET_CODE (*pat)) - 1; i >= 0; i--)
- {
- if (fmt[i] == 'e')
- {
- rtx *new_result = unique_src_operand (&XEXP (*pat, i), reg);
-
- if (new_result)
- {
- if (result)
- return NOT_UNIQUE;
- result = new_result;
- }
- }
- else if (fmt[i] == 'E')
- {
- for (j = XVECLEN (*pat, i) - 1; j >= 0; j--)
- {
- rtx *new_result =
- unique_src_operand (&XVECEXP (*pat, i, j), reg);
-
- if (new_result)
- {
- if (result)
- return NOT_UNIQUE;
- result = new_result;
- }
- }
- }
- }
- return result;
-}
-
-/* Clean up the instructions to remove unneeded loads and stores.
-
- For example, rewrite
-
- iload a; iload b; iadd; istore z
- iload z; iload c; iadd; istore z
-
- as
-
- iload a; iload b; iadd ; iload c; iadd; istore z
-
- This function moves a cursor over each instruction, inspecting the
- LOG_LINKS. Each of the cursor's LOG_LINK incoming instructions are
- inspected, any which have a simple register destination which is
- also used as a source in the cursor instruction, and aren't used
- again between the the incoming instruction and the cursor, and
- which become dead or set after the cursor get their sources
- substituted into the position of the source register in the cursor
- instruction. */
-
-void
-pj_machine_dependent_reorg (insns)
- rtx insns;
-{
- rtx cursor;
-
- if (!optimize || !TARGET_REORG)
- return;
-
- for (cursor = insns; cursor; cursor = NEXT_INSN (cursor))
- {
- rtx links;
- rtx cursor_pat;
-
- /* We only care about INSNs, JUMP_INSNs. Ignore any special USE insns. */
-
- if ((GET_CODE (cursor) != INSN && GET_CODE (cursor) != JUMP_INSN)
- || GET_CODE (cursor_pat = PATTERN (cursor)) == USE
- || GET_CODE (cursor_pat) == CLOBBER
- || GET_CODE (cursor_pat) == ADDR_VEC
- || GET_CODE (cursor_pat) == ADDR_DIFF_VEC)
- continue;
-
- for (links = LOG_LINKS (cursor); links; links = XEXP (links, 1))
- {
- rtx prev = XEXP (links, 0);
- rtx prev_pat;
- rtx prev_dest;
- rtx prev_src;
- rtx *dst_place;
-
- if (GET_CODE (prev) == INSN
- && GET_CODE (prev_pat = PATTERN (prev)) == SET
- && GET_CODE (prev_dest = SET_DEST (prev_pat)) == REG
- && dead_or_set_p (cursor, prev_dest)
- && !reg_used_between_p (prev_dest, prev, cursor)
- && no_labels_between_p (prev, cursor)
- && no_jumps_between_p (prev, cursor)
- && !modified_between_p ((prev_src = SET_SRC (prev_pat)), prev,
- cursor)
- && (dst_place = unique_src_operand (&cursor_pat, prev_dest))
- && dst_place != NOT_UNIQUE
- && REGNO (prev_dest) != OPTOP_REG
- && GET_MODE (prev_dest) != XFmode
- && GET_MODE (*dst_place) == GET_MODE (SET_DEST (prev_pat)))
- {
- *dst_place = SET_SRC (prev_pat);
- PUT_CODE (prev, NOTE);
- NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
- }
- }
- }
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler for picoJava
- Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). */
-
-
-#define TARGET_VERSION fputs ("(picoJava)", stderr);
-
-/* We support two different default configurations. */
-#undef ASM_SPEC
-#ifdef TARGET_LITTLE_ENDIAN_DEFAULT
-#define CPP_SPEC "%{mb:-D__BIG_ENDIAN__ }%{!mb:-D__LITTLE_ENDIAN__ }"
-#define ASM_SPEC "%{mb:-EB }%{!mb:-EL }"
-#else
-#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__ }%{!ml:-D__BIG_ENDIAN__}"
-#define ASM_SPEC "%{ml:-EL } %{!ml:-EB }"
-#endif
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ELF__ -D__pj__ -Asystem=posix"
-#endif
-\f
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
-#define LITTLE_ENDIAN_BIT (1<<0)
-#define EXTENSIONS_BIT (1<<1)
-#define PJ_TEST_BIT (1<<2)
-#define REORG_BIT (1<<3)
-
-/* Nonzero if generating code for a little endian pico java. */
-
-#define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
-
-/* Nonzero to turn on internal tests. */
-
-#define TARGET_TEST (target_flags & PJ_TEST_BIT)
-
-/* Nonzero to turn on picoJava extensions. */
-
-#define TARGET_TM_EXTENSIONS (target_flags & EXTENSIONS_BIT)
-
-/* Nonzero to turn on the reorganization pass. */
-
-#define TARGET_REORG (target_flags & REORG_BIT)
-
-#ifdef TARGET_LITTLE_ENDIAN_DEFAULT
-#define TARGET_DEFAULT (LITTLE_ENDIAN_BIT|EXTENSIONS_BIT|REORG_BIT)
-#else
-#define TARGET_DEFAULT REORG_BIT
-#endif
-
-#define TARGET_SWITCHES \
-{ {"l", LITTLE_ENDIAN_BIT, \
- N_("Generate little endian data") }, \
- {"b", -LITTLE_ENDIAN_BIT, \
- N_("Generate big endian data") }, \
- {"t", PJ_TEST_BIT, \
- N_("Turn on maintainer testing code") }, \
- {"ext", EXTENSIONS_BIT, \
- N_("Enable Transmeta picoJava extensions") }, \
- {"no-ext", -EXTENSIONS_BIT, \
- N_("Disable Transmeta picoJava extensions") }, \
- {"no-reorg", -REORG_BIT, \
- N_("Disable reorganization pass") }, \
- {"", TARGET_DEFAULT, 0 }}
-
-/* Sometimes certain combinations of command options do not make
- sense on a particular target machine. You can define a macro
- `OVERRIDE_OPTIONS' to take account of this. This macro, if
- defined, is executed once just after all the command options have
- been parsed.
-
- Don't use this macro to turn on various extra optimizations for
- `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
-
- We take this chance to register the global variables with the garbage
- collector. */
-
-#define OVERRIDE_OPTIONS \
- do { \
- ggc_add_rtx_root (&pj_cmp_op0, 1); \
- ggc_add_rtx_root (&pj_cmp_op1, 1); \
- } while (0)
-
-/* Define this to change the optimizations performed by default. */
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
- do { \
- if (optimize) \
- flag_force_addr = 1; \
- } while (0)
-\f
-/* Target machine storage layout. */
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields. */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
-
-/* Define this if most significant word of a multiword number is the lowest
- numbered. */
-#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
-
-/* Define this to set the endianness to use in libgcc2.c, which can
- not depend on target_flags. */
-#if defined(TARGET_LITTLE_ENDIAN_DEFAULT)
-#define LIBGCC2_WORDS_BIG_ENDIAN 0
-#else
-#define LIBGCC2_WORDS_BIG_ENDIAN 1
-#endif
-
-#define MAX_BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 4
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 8
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this. */
-#define BIGGEST_ALIGNMENT 32
-
-/* The best alignment to use in cases where we have a choice. */
-#define FASTEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster. */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- ((TREE_CODE (EXP) == STRING_CST \
- && (ALIGN) < FASTEST_ALIGNMENT) \
- ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons. */
-#define DATA_ALIGNMENT(TYPE, ALIGN) \
- (TREE_CODE (TYPE) == ARRAY_TYPE \
- && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
- && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Set this non-zero if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 1
-\f
-
-/* Standard register usage. */
-
-/* Enumerate the hardware registers. */
-
-enum
-{
- R0_REG, R1_REG, R2_REG, R3_REG,
- R4_REG, R5_REG, R6_REG, R7_REG,
- R8_REG, R9_REG, R10_REG, R11_REG,
- R12_REG, R13_REG, R14_REG, R15_REG,
-
- R16_REG, R17_REG, R18_REG, R19_REG,
- R20_REG, R21_REG, R22_REG, R23_REG,
- R24_REG, R25_REG, R26_REG, R27_REG,
- R28_REG, R29_REG, R30_REG, R31_REG,
-
- I0_REG, I1_REG, I2_REG, I3_REG,
- I4_REG, I5_REG, I6_REG, I7_REG,
- I8_REG, I9_REG, I10_REG, I11_REG,
- I12_REG, I13_REG, I14_REG, I15_REG,
-
- I16_REG, I17_REG, I18_REG, I19_REG,
- I20_REG, I21_REG, I22_REG, I23_REG,
- I24_REG, I25_REG, I26_REG, I27_REG,
- I28_REG, I29_REG, I30_REG, ISC_REG,
-
- G0_REG, G1_REG, G2_REG, G3_REG,
- G4_REG, G5_REG, G6_REG, G7_REG,
- VARS_REG, OPTOP_REG, SC_REG, PC_REG,
- TICKS_REG, SLOW_REG, VA_REG, D3_REG,
-
- D4_REG, D5_REG, D6_REG, D7_REG,
- Q0_REG, Q1_REG, Q2_REG, Q3_REG,
- P0_REG, P1_REG, P2_REG, P3_REG,
- P4_REG, P5_REG, P6_REG, P7_REG,
-
- O0_REG, O1_REG, O2_REG, O3_REG,
- O4_REG, O5_REG, O6_REG, O7_REG,
- O8_REG, O9_REG, O10_REG, O11_REG,
- O12_REG, O13_REG, O14_REG, O15_REG,
-
- O16_REG, O17_REG, O18_REG, O19_REG,
- O20_REG, O21_REG, O22_REG, O23_REG,
- O24_REG, O25_REG, O26_REG, O27_REG,
- O28_REG, O29_REG, O30_REG, OSC_REG,
-
- LAST_O_REG=OSC_REG,
- LAST_R_REG=R31_REG,
- LAST_I_REG=ISC_REG,
- LAST_S_REG=P7_REG
-
-};
-
-/* Useful predicates. */
-
-#define STACK_REGNO_P(REGNO) \
- (((unsigned) (REGNO)) <= LAST_I_REG)
-
-#define OUTGOING_REGNO_P(REGNO) \
- (((REGNO) >= O0_REG) && ((REGNO) <= LAST_O_REG))
-
-#define INCOMING_REGNO_P(REGNO) \
- (((REGNO) >= I0_REG) && ((REGNO) <= LAST_I_REG))
-
-#define STACK_REG_RTX_P(RTX) \
- (GET_CODE (RTX) == REG && STACK_REGNO_P (REGNO (RTX)))
-
-#define OUTGOING_REG_RTX_P(RTX) \
- (GET_CODE (RTX) == REG && OUTGOING_REGNO_P (REGNO (RTX)))
-
-#define OPTOP_REG_RTX_P(RTX) \
- (GET_CODE (RTX) == REG && REGNO (RTX) == OPTOP_REG)
-
-#define FIRST_PSEUDO_REGISTER 128
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator. */
-
-#define FIXED_REGISTERS \
- { \
- 0,0,0,0, 0,0,0,0, /* r0 .. r7 */ \
- 0,0,0,0, 0,0,0,0, /* r8 .. r15 */ \
- 0,0,0,0, 0,0,0,0, /* r16.. r23 */ \
- 0,0,0,0, 0,0,0,0, /* r24.. r31 */ \
- \
- 0,0,0,0, 0,0,0,0, /* i0 .. i7 */ \
- 0,0,0,0, 0,0,0,0, /* i8 .. i15 */ \
- 0,0,0,0, 0,0,0,0, /* i16.. i23 */ \
- 0,0,0,0, 0,0,0,0, /* i24.. i31 */ \
- \
- 1,0,0,1, 1,1,1,1, /* g0 .. g7 */ \
- 1,1,1,1, 1,1,1,1, /* vars, optop, sc, pc, ticks, slow, va, sgo */ \
- 1,1,1,1, 1,1,1,1, /* d4 d5 d6 ap p0 p1 p2 p3 */ \
- 1,1,1,1, 1,1,1,1, /* q1 .. q7 */ \
- \
- 0,0,0,0, 0,0,0,0, /* o0 .. o7 */ \
- 0,0,0,0, 0,0,0,0, /* o8 .. o15 */ \
- 0,0,0,0, 0,0,0,0, /* o16.. o23 */ \
- 0,0,0,0, 0,0,0,0 } /* o24.. o31 */
-
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like.
-
- We pretend that some standard registers are call clobbered so the
- exception handler code has somewhere to play. */
-
-#define CALL_USED_REGISTERS \
- { \
- 0,0,0,0, 0,0,0,0, /* r0 ..r7 */ \
- 0,0,0,0, 0,0,0,0, /* r8 ..r15 */ \
- 0,0,0,0, 1,1,1,1, /* r16..r23 */ \
- 1,1,1,1, 1,1,1,1, /* r24..r31 */ \
- \
- 0,0,0,0, 0,0,0,0, /* i0 ..i7 */ \
- 0,0,0,0, 0,0,0,0, /* i8 ..i15 */ \
- 0,0,0,0, 0,0,0,0, /* i16..i23 */ \
- 0,0,0,0, 0,0,0,0, /* i24..i31 */ \
- \
- 1,1,1,1, 0,0,0,0, /* g0 ..g7 */ \
- 1,1,1,1, 1,1,1,1, /* vars, optop, sc, pc, ticls, slow, va, sgo */ \
- 1,1,1,1, 1,1,1,1, /* d4 d5 d6 ap p0..p3*/ \
- 1,1,1,1, 1,1,1,1, /* q0..q7 */ \
- \
- 1,1,1,1, 1,1,1,1, /* o0 ..o7 */ \
- 1,1,1,1, 1,1,1,1, /* o8 ..o15 */ \
- 1,1,1,1, 1,1,1,1, /* o16..o23 */ \
- 1,1,1,1, 1,1,1,1 } /* o24..o31 */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers. */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-
- We can allow any mode in the general register or the result
- register. It's only safe to put up to 4 bytes values elsewhere. */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (((REGNO) <= LAST_R_REG || (REGNO) == G1_REG || GET_MODE_SIZE(MODE) <= 4 ) && !OUTGOING_REGNO_P(REGNO))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) 1
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-/* Define this if the program counter is overloaded on a register. */
-#define PC_REGNUM PC_REG
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM G0_REG
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM R31_REG
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM R30_REG
-
-/* Register in which the static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM G1_REG
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms may be
- accessed via the stack pointer) in functions that seem suitable. */
-#define FRAME_POINTER_REQUIRED 0
-
-/* This is an array of structures. Each structure initializes one pair
- of eliminable registers. The "from" register number is given first,
- followed by "to". Eliminations of the same "from" register are listed
- in order of preference. */
-
-#define ELIMINABLE_REGS \
- { { VA_REG, STACK_POINTER_REGNUM }, \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
- { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM } }
-
-/* Given FROM and TO register numbers, say whether this elimination
- is allowed. */
-#define CAN_ELIMINATE(FROM, TO) 1
-
-/* Define the offset between two registers, one to be eliminated, and the other
- its replacement, at the start of a routine. */
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
- OFFSET = (((FROM) == FRAME_POINTER_REGNUM) ? get_frame_size() : 0)
-
-/* For picoJava we have to save 12 bytes of information for a non local
- jump. */
-
-#define STACK_SAVEAREA_MODE(x) ((x)==SAVE_NONLOCAL ? XFmode : Pmode)
-
-/* If the structure value address is not passed in a register, define
- `STRUCT_VALUE' as an expression returning an RTX for the place
- where the address is passed. If it returns 0, the address is
- passed as an "invisible" first argument. */
-#define STRUCT_VALUE 0
-
-/* A C expression which can inhibit the returning of certain function
- values in registers, based on the type of value. A nonzero value
- says to return the function value in memory, just as large
- structures are always returned. Here TYPE will be a C expression
- of type `tree', representing the data type of the value.
-
- Note that values of mode `BLKmode' must be explicitly handled by
- this macro. Also, the option `-fpcc-struct-return' takes effect
- regardless of this macro. On most systems, it is possible to
- leave the macro undefined; this causes a default definition to be
- used, whose value is the constant 1 for `BLKmode' values, and 0
- otherwise.
-
- Do not use this macro to indicate that structures and unions
- should always be returned in memory. You should instead use
- `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
-#define RETURN_IN_MEMORY(TYPE) \
- ((TYPE_MODE (TYPE) == BLKmode) || int_size_in_bytes (TYPE) > 8)
-
-/* Don't default to pcc-struct-return, because we have already specified
- exactly how to return structures in the RETURN_IN_MEMORY macro. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-\f
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
-enum reg_class
-{
- NO_REGS,
- OUT_REGS, /* Registers for passing outgoing parameters. */
- STD_REGS, /* Standard registers, on opstack. */
- ARG_REGS, /* Incoming argument registers. */
- SRC_REGS, /* All registers valid as a source. */
- DST_REGS, /* All registers valid as a destination. */
- ALL_REGS,
- LIM_REG_CLASSES
-};
-
-#define GENERAL_REGS SRC_REGS
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump files. */
-#define REG_CLASS_NAMES \
-{ \
- "NO_REGS", \
- "OUT_REGS", \
- "STD_REGS", \
- "ARG_REGS", \
- "SRC_REGS", \
- "DST_REGS", \
- "ALL_REGS" \
-}
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. */
-
-#define REG_CLASS_CONTENTS \
-{ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* OUT_REGS */ \
- { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* STD_REGS */ \
- { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* ARG_REGS */ \
- { 0xffffffff, 0xffffffff, 0x000fff0f, 0x00000000 }, /* SRC_REGS */ \
- { 0xffffffff, 0xffffffff, 0x000fff0f, 0xffffffff }, /* DST_REGS */ \
- { 0xffffffff, 0xffffffff, 0x000fff0f, 0xffffffff }, /* ALL_REGS */ \
-}
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-#define REGNO_REG_CLASS(REGNO) \
- ( ((REGNO) <= LAST_R_REG) ? STD_REGS \
- : ((REGNO) <= LAST_I_REG) ? ARG_REGS \
- : ((REGNO) <= LAST_S_REG) ? SRC_REGS \
- : OUT_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine
- description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
- ( (C) == 'S' ? SRC_REGS \
- : (C) == 'D' ? DST_REGS \
- : NO_REGS)
-\f
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- I: arithmetic operand -127..128, as used in inc.
- K: 0.
- */
-
-#define CONST_OK_FOR_I(VALUE) \
- (((HOST_WIDE_INT)(VALUE))>= -128 && ((HOST_WIDE_INT)(VALUE)) <= 127)
-
-#define CONST_OK_FOR_K(VALUE) ((VALUE)==0)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
- : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
- : 0)
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-
-#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS.
-
- With picoJava this is the size of MODE in words. */
-
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-
-/* A C expression whose value is nonzero if pseudos that have been
- assigned to registers of class CLASS would likely be spilled
- because registers of CLASS are needed for spill registers.
-
- For picoJava, something that isn't an incoming argument or a normal
- register is going to be very hard to get at. */
-
-#define CLASS_LIKELY_SPILLED_P(X) ((X) != STD_REGS && (X) != ARG_REGS)
-\f
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-
-#define STACK_GROWS_DOWNWARD 1
-
-/* Define this macro if successive arguments to a function occupy
- decreasing addresses on the stack. */
-
-#define ARGS_GROW_DOWNWARD 1
-
-/* Define this macro if the addresses of local variable slots are at
- negative offsets from the frame pointer. */
-
-#define FRAME_GROWS_DOWNWARD 1
-
-/* Offset from the frame pointer to the first local variable slot to
- be allocated. */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by. */
-
-/* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
- When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
- do correct alignment. */
-
-#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
-
-/* Offset of first parameter from the argument pointer register value. */
-
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of byte of arguments automatically
- popped when returning from a subroutine call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name.
- SIZE is the number of bytes of arguments passed on the stack. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), G1_REG)
-
-/* 1 if N is a possible register number for a function value
- as seen by the caller. */
-
-#define FUNCTION_VALUE_REGNO_P(N) \
- ((N) == G1_REG)
-
-/* 1 if N is a possible register number for function argument passing. */
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG (MODE, G1_REG)
-
-/* Define this macro to be a nonzero value if the location where a
- function argument is passed depends on whether or not it is a
- named argument. */
-
-#define STRICT_ARGUMENT_NAMING 1
-
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go.
-
- For picoJava this is a struct which remembers the number of
- arguments named, the total number of words passed and an adjustment
- factor to use if accessing a double word argument with a single
- word memop. See the comments at the head pj.c for more information */
-
-#define ARGS_IN_REGS 32
-
-struct pj_args
-{
- int named_words;
- int total_words;
- int arg_count;
- int arg_adjust[ARGS_IN_REGS];
-};
-
-#define CUMULATIVE_ARGS struct pj_args
-
-#define FUNCTION_INCOMING_ARG(asf,pmode,passtyped,named) \
- pj_function_incoming_arg(&asf,pmode,passtyped,named)
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0.
- */
-
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
- (CUM).named_words = 0; \
- (CUM).total_words = 0; \
- (CUM).arg_count = 0;
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
-
- picoJava only ever sends scalars as arguments. Aggregates are sent
- by reference. */
-
-#define PJ_ARG_WORDS(MODE) \
- ((GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-{ \
- (CUM).total_words += PJ_ARG_WORDS (MODE); \
- if (NAMED) \
- (CUM).named_words += PJ_ARG_WORDS (MODE); \
- (CUM).arg_count++; \
-}
-
-/* Define where to put the arguments to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis).
-
- For picoJava scalar arguments are normally in registers. */
-
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
- ( ((CUM).total_words + PJ_ARG_WORDS (MODE) < ARGS_IN_REGS) \
- ? gen_rtx (REG, MODE, O0_REG + (CUM).total_words) \
- : NULL_RTX)
-
-
-/* A C expression that indicates when an argument must be passed by
- reference. If nonzero for an argument, a copy of that argument is
- made in memory and a pointer to the argument is passed instead of
- the argument itself. The pointer is passed in whatever way is
- appropriate for passing a pointer to that type. */
-
-/* All aggregates and arguments larger than 8 bytes are passed this way. */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
- (TYPE && (AGGREGATE_TYPE_P (TYPE) || int_size_in_bytes (TYPE) > 8))
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 0
-\f
-/* Trampoline support. */
-
-/* A picoJava trampoline looks like:
-
- 0000 11DEAD sipush %lo16(static)
- 0003 EDDEAD sethi %hi16(static)
- 0006 FF7D write_global1
- 0008 11DEAD sipush %lo16(fn)
- 000b EDDEAD sethi %hi16(fn)
- 000e FF60 write_pc
-*/
-
-/* Length in units of the trampoline for entering a nested function. */
-#define TRAMPOLINE_SIZE 16
-
-/* Alignment required for a trampoline in bits . */
-#define TRAMPOLINE_ALIGNMENT 32
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
- fprintf (FILE, "\tsipush 0xdead\n"); \
- fprintf (FILE, "\tsethi 0xdead\n"); \
- fprintf (FILE, "\twrite_global1\n"); \
- fprintf (FILE, "\tsipush 0xdead\n"); \
- fprintf (FILE, "\tsethi 0xdead\n"); \
- fprintf (FILE, "\twrite_pc\n");
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- static const int off[4] = { 1, 0, 4, 3 }; \
- int i; \
- \
- /* Move the FNADDR and CXT into the instruction stream. Do this byte \
- by byte to make sure it works for either endianness. */ \
- \
- for (i = 0; i < 4; i++) \
- emit_move_insn \
- (gen_rtx_MEM (QImode, \
- plus_constant (tramp, off[i] + 1)), \
- gen_rtx_TRUNCATE (QImode, \
- expand_shift (RSHIFT_EXPR, SImode, \
- CXT, size_int (i * 8), 0, 1))); \
- \
- for (i = 0; i < 4; i++) \
- emit_move_insn \
- (gen_rtx_MEM (QImode, \
- plus_constant (tramp, off[i] + 9)), \
- gen_rtx_TRUNCATE (QImode, \
- expand_shift (RSHIFT_EXPR, SImode, \
- FNADDR, size_int (i * 8), 0, 1))); \
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tsipush %%lo16(.LP%d)\n", (LABELNO)); \
- fprintf (FILE, "\tsethi %%hi16(.LP%d)\n", (LABELNO)); \
- fprintf (FILE, "\tsipush %%lo16(_mcount)\n"); \
- fprintf (FILE, "\tsethi %%hi16(_mcount)\n"); \
- fprintf (FILE, "\ticonst_3\n"); \
- fprintf (FILE, "\tcall\n");
-
-\f
-/* Addressing modes, and classification of registers for them. */
-
-#define HAVE_POST_INCREMENT 1
-#define HAVE_PRE_INCREMENT 1
-#define HAVE_POST_DECREMENT 1
-#define HAVE_PRE_DECREMENT 1
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
-
-/* Any register is OK for a base or an index. As is something that has
- been spilled to memory. */
-
-#define REGNO_OK_FOR_BASE_P(REGNO) 1
-#define REGNO_OK_FOR_INDEX_P(REGNO) 1
-
-/* Maximum number of registers that can appear in a valid memory
- address.
-
- Arbitarily limited to 20. */
-
-#define MAX_REGS_PER_ADDRESS 20
-
-/* Recognize any constant value that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
-
-/* Nonzero if the constant value X is a legitimate general operand. */
-
-#define LEGITIMATE_CONSTANT_P(X) \
- (GET_CODE (X) == CONST_DOUBLE ? (pj_standard_float_constant (X)!=0) : 1)
-
-/* Letters in the range `Q' through `U' in a register constraint string
- may be defined in a machine-dependent fashion to stand for arbitrary
- operand types.
-
- For picoJava, `S' handles a source operand. */
-
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'S' ? pj_source_operand (OP, GET_MODE (OP)) : 0)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and
- check its validity for a certain class. */
-
-#define REG_OK_FOR_BASE_P(X) 1
-#define REG_OK_FOR_INDEX_P(x) 0
-
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- We may have arbitrarily complex addressing modes, but we get better
- cse of address expressions if we generate code with simple
- addressing modes and clean up redundant register operations later
- in the machine dependent reorg pass. */
-
-#define SRC_REG_P(X) \
- (REG_P(X) && !OUTGOING_REG_RTX_P (X))
-
-#define SIMPLE_ADDRESS(X) \
- (SRC_REG_P(X) || CONSTANT_ADDRESS_P(X))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
- if (SIMPLE_ADDRESS(X)) goto LABEL; \
- if ((GET_CODE (X) == POST_INC \
- || GET_CODE (X) == PRE_INC \
- || GET_CODE (X) == POST_DEC \
- || GET_CODE (X) == PRE_DEC) && SRC_REG_P(XEXP (X, 0))) goto LABEL; \
-
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
-{ \
- if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC \
- || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_DEC) \
- goto LABEL; \
-}
-\f
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table. */
-
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* 'char' is signed by default. */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* The type of size_t unsigned int. */
-#define SIZE_TYPE "unsigned int"
-
-/* Don't cse the address of the function being compiled. */
-
-#define NO_RECURSIVE_FUNCTION_CSE (!optimize_size)
-
-/* Max number of bytes we can move from memory to memory
- in one reasonably fast instruction. */
-
-#define MOVE_MAX 4
-
-/* Max number of bytes we want move_by_pieces to be able to copy
- efficiently. */
-
-#define MOVE_MAX_PIECES 4
-
-/* Define if operations between registers always perform the operation
- on the full register even if a narrower mode is specified. */
-/*#define WORD_REGISTER_OPERATIONS*/
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
- will either zero-extend or sign-extend. The value of this macro should
- be the code that says which one of the two operations is implicitly
- done, NIL if none. */
-
-#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
-
-/* We assume that the store-condition-codes instructions store 0 for false
- and some other value for true. This is the value stored for true. */
-
-#define STORE_FLAG_VALUE 1
-
-/* Define if loading short immediate values into registers sign extends. */
-
-#define SHORT_IMMEDIATES_SIGN_EXTEND
-
-/* Nonzero if access to memory by bytes is no faster than for words. */
-#define SLOW_BYTE_ACCESS 1
-
-#define INT_TYPE_SIZE 32
-
-/* A C expression that is nonzero if on this machine the number of
- bits actually used for the count of a shift operation is equal to the
- number of bits needed to represent the size of the object being
- shifted. */
-
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* All integers have the same format so truncation is easy. */
-
-#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
-
-/* Define this if addresses of constant functions
- shouldn't be put through pseudo regs where they can be cse'd.
- Desirable on machines where ordinary constants are expensive
- but a CALL with constant address is cheap. */
-
-#define NO_FUNCTION_CSE (!optimize_size)
-
-/* Chars and shorts should be passed as ints. */
-
-#define PROMOTE_PROTOTYPES 1
-
-/* The machine modes of pointers and functions. */
-
-#define Pmode SImode
-#define FUNCTION_MODE Pmode
-
-\f
-/* A part of a C `switch' statement that describes the relative costs
- of constant RTL expressions. It must contain `case' labels for
- expression codes `const_int', `const', `symbol_ref', `label_ref'
- and `const_double'. Each case must ultimately reach a `return'
- statement to return the relative cost of the use of that kind of
- constant value in an expression. The cost may depend on the
- precise value of the constant, which is available for examination
- in X, and the rtx code of the expression in which it is contained,
- found in OUTER_CODE.
-
- CODE is the expression code--redundant, since it can be obtained
- with `GET_CODE (X)'. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST_INT: \
- return INTVAL (RTX) >= -1 && INTVAL (RTX) <= 5 ? 1 \
- : INTVAL (RTX) >= -32768 && INTVAL (RTX) <= 32767 ? 2 \
- : 3; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 3; \
- case CONST_DOUBLE: \
- return pj_standard_float_constant (RTX) ? 1 : 4; \
-
-/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
- This can be used, for example, to indicate how costly a multiply
- instruction is. In writing this macro, you can use the construct
- `COSTS_N_INSNS (N)' to specify a cost equal to N fast
- instructions. OUTER_CODE is the code of the expression in which X
- is contained. */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE) \
- case MULT: \
- if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
- { \
- unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
- int nbits = 0; \
- \
- while (value != 0) \
- { \
- nbits++; \
- value >>= 1; \
- } \
- \
- total = COSTS_N_INSNS (nbits); \
- } \
- else \
- total = COSTS_N_INSNS (10); \
- break;
-
-/* Compute extra cost of moving data between one register class and
- another. */
-
-#define REGISTER_MOVE_COST(MODE, SRC_CLASS, DST_CLASS) \
- ((SRC_CLASS == STD_REGS || SRC_CLASS == ARG_REGS)? 2 : 10)
-
-\f
-/* Assembler output control. */
-
-/* A C string constant describing how to begin a comment in the target
- assembler language. The compiler assumes that the comment will end at
- the end of the line. */
-#define ASM_COMMENT_START "!"
-
-/* The text to go at the start of the assembler file. */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
- do { \
- fputs ("\t.file\t", FILE); \
- output_quoted_string (FILE, main_input_filename); \
- fprintf (FILE,"\t! %s\n", TARGET_LITTLE_ENDIAN ? ".little" : ".big"); \
- fprintf (FILE,"\t.align 4\n"); \
- } while (0)
-
-#define ASM_APP_ON ""
-#define ASM_APP_OFF ""
-#define FILE_ASM_OP "\t.file\n"
-
-#define SET_ASM_OP "\t.set\t"
-
-/* How to change between sections. */
-
-#define TEXT_SECTION_ASM_OP "\t.text"
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* This special macro is used to output the asm pseduo op which allows
- the linker to fixup broken calling conentions. */
-
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \
-do { fputs (current_function_varargs || current_function_stdarg \
- ? "\t.varargs_words_needed\t" : "\t.words_needed\t", \
- FILE); \
- assemble_name (FILE, FNNAME); \
- fprintf (FILE, ", %d\n", current_function_args_info.named_words); \
- } while (0)
-
-/* If defined, a C expression whose value is a string containing the
- assembler operation to identify the following data as
- uninitialized G data. If not defined, and neither
- `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
- uninitialized global data will be output in the data section if
- `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
- used. */
-
-#define BSS_SECTION_ASM_OP "\t.section\t.bss"
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
- separate, explicit argument. If you define this macro, it is used
- in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
- handling the required alignment of the variable. The alignment is
- specified as the number of bits.
-
- Try to use function `asm_output_aligned_bss' defined in file
- `varasm.c' when defining this macro. */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
- asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-
-
-/* Define this so that jump tables go in same section as the current function,
- which could be text or it could be a user defined section. */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* The assembler's names for the registers. */
-
-#define REGISTER_NAMES \
-{ \
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "r8", "r9", "r10", "r11", "r12", "r13", "r14","r15", \
- "r16","r17", "r18", "r19", "r20", "r21", "r22","r23", \
- "r24","r25", "r26", "r27", "r28", "r29", "r30","r31", \
- \
- "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", \
- "i8", "i9", "i10", "i11", "i12", "i13", "i14","i15", \
- "i16","i17", "i18", "i19", "i20", "i21", "i22","i23", \
- "i24","i25", "i26", "i27", "i28", "i29", "i30","i31", \
- \
- "global0", "global1", "global2", "global3", \
- "global4", "global5", "global6", "global7", \
- "vars", "optop", "sc", "pc", \
- "ticks", "slow", "va", "d3", \
- "d4", "d5", "d6", "ap", \
- "p0", "p1", "p2", "p3", \
- "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", \
- \
- "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", \
- "o8", "o9", "o10", "o11", "o12", "o13", "o14","o15", \
- "o16","o17", "o18", "o19", "o20", "o21", "o22","o23", \
- "o24","o25", "o26", "o27", "o28", "o29", "o30","o31"} \
-
-
-/* Output a label definition. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0)
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG) != 0) \
- fprintf ((FILE), "\t.align %d\n", (LOG))
-
-/* Output a globalising directive for a label. */
-
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
- (fprintf ((STREAM), "\t.global\t"), \
- assemble_name ((STREAM), (NAME)), \
- fputc ('\n', (STREAM)))
-
-/* After an opcode has been printed, there's nothing on the line any
- more. */
-
-#define ASM_OUTPUT_OPCODE(STREAM, P) \
- pj_stuff_on_line = 0;
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* The prefix to add to an internally generated label. */
-
-#define LOCAL_LABEL_PREFIX "."
-
-/* Make an internal label into a string. */
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
- sprintf ((STRING), "*%s%s%ld", LOCAL_LABEL_PREFIX, (PREFIX), (long)(NUM))
-
-/* Output an internal label definition. */
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM))
-
-/* Construct a private name. */
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
- ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
- sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
-
-/* Output a relative address table. */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
- asm_fprintf ((STREAM), "\t.long\t.L%d-.L%di\n", (VALUE),(REL));
-
-#define ADDR_VEC_ALIGN(VEC) 0
-
-/* Output various types of constants. */
-
-/* This is how to output an assembler line
- that says to advance the location counter by SIZE bytes. */
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf ((FILE), "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* We don't want the default switch handling. */
-#undef ASM_OUTPUT_BEFORE_CASE_LABEL
-#undef ASM_OUTPUT_CASE_LABEL
-\f
-/* Print operand X (an rtx) in assembler syntax to file FILE.
- CODE is a letter or star or 0 if no letter was specified.
- For `%' followed by punctuation, CODE is the punctuation and X is null. */
-
-#define PRINT_OPERAND(STREAM, X, CODE) pj_print_operand ((STREAM), (X), (CODE))
-
-/* Print a memory address as an operand to reference that memory location. */
-
-#define PRINT_OPERAND_ADDRESS(STREAM,X) output_addr_const (STREAM, X)
-
-/* Punctuation valid for print_operand. */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '*')
-\f
-
-/* Define this macro if it is advisable to hold scalars in registers
- in a wider mode than that declared by the program. In such cases,
- the value is constrained to be within the bounds of the declared
- type, but kept valid in the wider mode. The signedness of the
- extension may differ from that of the type.
-
- Since picoJava doesn't have unsigned compares, prefer signed
- arithmetic. */
-
-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
- if (GET_MODE_CLASS (MODE) == MODE_INT \
- && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
- { \
- (MODE) = SImode; \
- (UNSIGNEDP) = 0; \
- }
-
-/* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
- extensions applied to char/short functions arguments. Defining
- PROMOTE_FUNCTION_RETURN does the same for function returns. */
-#define PROMOTE_FUNCTION_ARGS
-
-\f
-/* We can debug without a frame pointer. */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* How to renumber registers for dbx and gdb. */
-extern short pj_debugreg_renumber_vec[FIRST_PSEUDO_REGISTER];
-
-#define DBX_REGISTER_NUMBER(REG) (pj_debugreg_renumber_vec[REG])
-
-#define DONT_USE_BUILTIN_SETJMP
-
-/* We prefer to use dwarf2. */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-#define DWARF2_UNWIND_INFO 1
-
-\f
-/* varargs and stdarg builtins. */
-
-#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
-do { \
- tree t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, \
- make_tree (ptr_type_node, gen_rtx_REG (Pmode, VA_REG))); \
- TREE_SIDE_EFFECTS (t) = 1; \
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); \
- } while (0)
-
-
-#define EXPAND_BUILTIN_VA_ARG(valist, type) \
- pj_expand_builtin_va_arg(valist, type)
-
-#define EXPAND_BUILTIN_NEXT_ARG(OFFSET) \
- gen_rtx_MEM (Pmode, \
- plus_constant (gen_rtx_REG (SImode, VARS_REG), \
- (INTVAL (offset) + 1) * -4));
-
-/* Before the prologue, the return address is just above optop. */
-#define INCOMING_RETURN_ADDR_RTX \
- plus_constant (gen_rtx_REG (Pmode, OPTOP_REG), 4)
-
-/* Rewrite the rtl to use take advantage of the opstack. */
-#define MACHINE_DEPENDENT_REORG(INSNS) pj_machine_dependent_reorg(INSNS)
-
-
-/* Define the codes that are matched by predicates in pj.c. */
-#define PREDICATE_CODES \
- {"pj_dest_operand", {SUBREG, REG, MEM}}, \
- {"pj_signed_comparison_operator", {EQ, NE, LE, LT, GE,GT}}, \
- {"pj_unsigned_comparison_operator", {LEU, LTU, GEU, GTU}}, \
- {"pj_source_operand", {CONST_INT, CONST_DOUBLE, CONST, \
- SYMBOL_REF, LABEL_REF, SUBREG, \
- REG, MEM}},
-
-/* Generate calls to memcpy, memcmp and memset. */
-#define TARGET_MEM_FUNCTIONS
+++ /dev/null
-;; Machine description for GNU compiler, picoJava Version
-;; Copyright (C) 2000 Free Software Foundation, Inc.
-;; Contributed by Steve Chamberlain, of Transmeta (sac@pobox.com).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; Move instructions.
-
-(define_insn "movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (match_operand:SI 1 "pj_source_operand" "gS"))]
- ""
- "%S1%R0")
-
-(define_insn "movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=gD")
- (match_operand:HI 1 "pj_source_operand" "gS"))]
- ""
- "%S1%R0")
-
-(define_insn "movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=gD")
- (match_operand:QI 1 "pj_source_operand" "gS"))]
- ""
- "%S1%R0")
-
-(define_insn "movdi"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (match_operand:DI 1 "pj_source_operand" "gS"))]
- ""
- "%D1%*%R0")
-
-(define_insn "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (match_operand:DF 1 "pj_source_operand" "gS"))]
- ""
- "%D1%R0")
-
-(define_insn "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (match_operand:SF 1 "pj_source_operand" "gS"))]
- ""
- "%S1%R0")
-
-\f
-;; Arithmetic.
-
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (plus:SI (match_operand:SI 1 "pj_source_operand" "%gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "* return pj_output_addsi3 (operands);")
-
-(define_insn "adddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (plus:DI (match_operand:DI 1 "pj_source_operand" "%gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*ladd%R0")
-
-(define_insn "addsf3"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (plus:SF (match_operand:SF 1 "pj_source_operand" "%gS")
- (match_operand:SF 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*fadd%R0")
-
-(define_insn "adddf3"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (plus:DF (match_operand:DF 1 "pj_source_operand" "%gS")
- (match_operand:DF 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*dadd%R0")
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (neg:SI (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*ineg%R0")
-
-(define_insn "negdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (neg:DI (match_operand:DI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*lneg%R0")
-
-(define_insn "negsf2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (neg:SF (match_operand:SF 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*fneg%R0")
-
-(define_insn "negdf2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (neg:DF (match_operand:DF 1 "pj_source_operand" "gS")))]
- ""
- "%D1%*dneg%R0")
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (minus:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*isub%R0")
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (minus:DI (match_operand:DI 1 "pj_source_operand" "gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*lsub%R0")
-
-(define_insn "subsf3"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (minus:SF (match_operand:SF 1 "pj_source_operand" "gS")
- (match_operand:SF 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*fsub%R0")
-
-(define_insn "subdf3"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (minus:DF (match_operand:DF 1 "pj_source_operand" "gS")
- (match_operand:DF 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*dsub%R0")
-
-(define_insn "divsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (div:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*idiv%R0")
-
-(define_insn "divdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (div:DI (match_operand:DI 1 "pj_source_operand" "gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*ldiv%R0")
-
-(define_insn "divsf3"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (div:SF (match_operand:SF 1 "pj_source_operand" "gS")
- (match_operand:SF 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*fdiv%R0")
-
-(define_insn "divdf3"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (div:DF (match_operand:DF 1 "pj_source_operand" "gS")
- (match_operand:DF 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*ddiv%R0")
-
-(define_insn "udivsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (udiv:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%P1%P2%*ldiv%*l2i%R0")
-
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (mult:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*imul%R0")
-
-(define_insn "muldi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (mult:DI (match_operand:DI 1 "pj_source_operand" "gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*lmul%R0")
-
-(define_insn "muldf3"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (mult:DF (match_operand:DF 1 "pj_source_operand" "%gS")
- (match_operand:DF 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*dmul%R0")
-
-(define_insn "mulsf3"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (mult:SF (match_operand:SF 1 "pj_source_operand" "%gS")
- (match_operand:SF 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*fmul%R0")
-
-(define_insn "modsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (mod:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*irem%R0")
-
-(define_insn "moddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (mod:DI (match_operand:DI 1 "pj_source_operand" "gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*lrem%R0")
-
-(define_insn "moddf3"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (mod:DF (match_operand:DF 1 "pj_source_operand" "gS")
- (match_operand:DF 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*drem%R0")
-
-(define_insn "modsf3"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (mod:SF (match_operand:SF 1 "pj_source_operand" "gS")
- (match_operand:SF 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*frem%R0")
-
-(define_insn "umodsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (umod:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%P1%P2%*lrem%*l2i%R0")
-
-\f
-;; Logical operations.
-
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (and:SI (match_operand:SI 1 "pj_source_operand" "%gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*iand%R0")
-
-(define_insn "anddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (and:DI (match_operand:DI 1 "pj_source_operand" "%gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*land%R0")
-
-(define_insn "iorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (ior:SI (match_operand:SI 1 "pj_source_operand" "%gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*ior%R0")
-
-(define_insn "iordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (ior:DI (match_operand:DI 1 "pj_source_operand" "%gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*lor%R0")
-
-(define_insn "xorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (xor:SI (match_operand:SI 1 "pj_source_operand" "%gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*ixor%R0")
-
-(define_insn "xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (xor:DI (match_operand:DI 1 "pj_source_operand" "%gS")
- (match_operand:DI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%D2%*lxor%R0")
-
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (not:SI (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*iconst_m1%*ixor%R0")
-
-(define_insn "one_cmpldi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (not:DI (match_operand:DI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*iconst_m1%*iconst_m1%*lxor%R0")
-
-\f
-;; Shift instructions.
-
-(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (ashift:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*ishl%R0")
-
-
-(define_insn "ashldi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (ashift:DI (match_operand:DI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%S2%*lshl%R0")
-
-(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (ashiftrt:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*ishr%R0")
-
-(define_insn "ashrdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (ashiftrt:DI (match_operand:DI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%S2%*lshr%R0")
-
-(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (lshiftrt:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%S1%S2%*iushr%R0")
-
-(define_insn "lshrdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (lshiftrt:DI (match_operand:DI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "pj_source_operand" "gS")))]
- ""
- "%D1%S2%*lushr%R0")
-
-\f
-;; Comparisons.
-
-(define_expand "cmpsi"
- [(set (cc0) (compare (match_operand:SI 0 "pj_source_operand" "gS")
- (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "{
- pj_cmp_op0 = operands[0];
- pj_cmp_op1 = operands[1];
- pj_cmp_mode = SImode;
- DONE;
- }")
-
-(define_expand "cmpdi"
- [(set (cc0) (compare (match_operand:DI 0 "pj_source_operand" "gS")
- (match_operand:DI 1 "pj_source_operand" "gS")))]
- ""
- "{
- pj_cmp_op0 = operands[0];
- pj_cmp_op1 = operands[1];
- pj_cmp_mode = DImode;
- DONE;
- }")
-
-(define_expand "cmpsf"
- [(set (cc0) (compare (match_operand:SF 0 "pj_source_operand" "gS")
- (match_operand:SF 1 "pj_source_operand" "gS")))]
- ""
- "{
- pj_cmp_op0 = operands[0];
- pj_cmp_op1 = operands[1];
- pj_cmp_mode = SFmode;
- DONE;
- }")
-
-(define_expand "cmpdf"
- [(set (cc0) (compare (match_operand:DF 0 "pj_source_operand" "gS")
- (match_operand:DF 1 "pj_source_operand" "gS")))]
- ""
- "{
- pj_cmp_op0 = operands[0];
- pj_cmp_op1 = operands[1];
- pj_cmp_mode = DFmode;
- DONE;
- }")
-
-\f
-;; Conversions.
-
-(define_insn "truncsiqi2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=gD")
- (truncate:QI (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*%R0")
-
-(define_insn "truncsihi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=gD")
- (truncate:HI (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*i2c%R0")
-
-(define_insn "truncdisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (truncate:SI (match_operand:DI 1 "pj_source_operand" "gS")))]
- ""
- "%D1%*l2i%R0")
-
-(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (fix:SI (match_operand:SF 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*f2i%R0")
-
-(define_insn "fix_truncsfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (fix:DI (match_operand:SF 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*f2l%R0")
-
-(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (float_truncate:SF (match_operand:DF 1 "pj_source_operand" "gS")))]
- ""
- "%D1%*d2f%R0")
-
-(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (fix:SI (match_operand:DF 1 "pj_source_operand" "gS")))]
- ""
- "%D1%*d2i%R0")
-
-(define_insn "fix_truncdfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (fix:DI (match_operand:DF 1 "pj_source_operand" "gS")))]
- ""
- "%D1%*d2l%R0")
-
-(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (float:SF (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*i2f%R0")
-
-(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (float:DF (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*i2d%R0")
-
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=gD")
- (float:SF (match_operand:DI 1 "pj_source_operand" "gS")))]
- ""
- "%D1%*l2f%R0")
-
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (float:DF (match_operand:DI 1 "pj_source_operand" "gS")))]
- ""
- "%D1%*l2d%R0")
-
-\f
-;; Zero-extend move instructions.
-
-(define_insn "zero_extendsidi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (zero_extend:DI (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%P1%R0")
-
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (zero_extend:SI (match_operand:HI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*i2c%R0")
-
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (zero_extend:SI (match_operand:QI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*sipush 0xff%*iand%R0")
-
-\f
-;; Conditional branch instructions.
-
-(define_expand "beq"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (EQ, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "bne"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (NE, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "bgt"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (GT, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "blt"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (LT, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "bge"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (GE, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "ble"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (LE, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "bgtu"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (GTU, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "bltu"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (LTU, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "bgeu"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (GEU, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_expand "bleu"
- [(set (pc) (if_then_else (match_op_dup 3 [(match_dup 1) (match_dup 2)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[3] = gen_rtx (LEU, pj_cmp_mode);
- operands[1] = pj_cmp_op0;
- operands[2] = pj_cmp_op1;")
-
-(define_insn "*bop"
- [(set (pc) (if_then_else (match_operand:SI 0 "pj_source_operand" "gS")
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- ""
- "%S0%*ifne %1")
-
-(define_insn "*rev_bop"
- [(set (pc) (if_then_else (match_operand:SI 0 "pj_source_operand" "gS")
- (pc)
- (label_ref (match_operand 1 "" ""))))]
-
- ""
- "%S0%*ifeq %1")
-
-(define_insn "*blopsi"
- [(set (pc)
- (if_then_else
- (match_operator:SI 3 "pj_signed_comparison_operator"
- [(match_operand:SI 0 "pj_source_operand" "gS,gS")
- (match_operand:SI 1 "pj_source_operand" "K,gS")])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "@
- %S0%*if%Y3 %2
- %S0%S1%*if_icmp%Y3 %2")
-
-(define_insn "*rev_blopsi"
- [(set (pc)
- (if_then_else
- (match_operator:SI 3 "pj_signed_comparison_operator"
- [(match_operand:SI 0 "pj_source_operand" "gS,gS")
- (match_operand:SI 1 "pj_source_operand" "K,gS")])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "@
- %S0%*if%Z3 %2
- %S0%S1%*if_icmp%Z3 %2")
-
-(define_insn "*bluopsi"
- [(set (pc)
- (if_then_else
- (match_operator:SI 3 "pj_unsigned_comparison_operator"
- [(match_operand:SI 0 "pj_source_operand" "gS")
- (match_operand:SI 1 "pj_source_operand" "gS")])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "%S0%S1%*iucmp%*if%Y3 %2")
-
-(define_insn "*rev_bluopsi"
- [(set (pc)
- (if_then_else
- (match_operator:SI 3 "pj_unsigned_comparison_operator"
- [(match_operand:SI 0 "pj_source_operand" "gS")
- (match_operand:SI 1 "pj_source_operand" "gS")])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "%S0%S1%*iucmp%*if%Z3 %2")
-
-(define_insn "*blopdi"
- [(set (pc)
- (if_then_else
- (match_operator:DI 3 "pj_signed_comparison_operator"
- [(match_operand:DI 0 "pj_source_operand" "gS")
- (match_operand:DI 1 "pj_source_operand" "gS")])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "%D0%D1%*lcmp%*if%Y3 %2")
-
-(define_insn "*rev_blopdi"
- [(set (pc)
- (if_then_else
- (match_operator:DI 3 "pj_signed_comparison_operator"
- [(match_operand:DI 0 "pj_source_operand" "gS")
- (match_operand:DI 1 "pj_source_operand" "gS")])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "%D0%D1%*lcmp%*if%Z3 %2")
-
-(define_insn "*bluopdi"
- [(set (pc)
- (if_then_else
- (match_operator:DI 3 "pj_unsigned_comparison_operator"
- [(match_operand:DI 0 "pj_source_operand" "gS")
- (match_operand:DI 1 "pj_source_operand" "gS")])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "%D0%D1%*ipush __pjucmpdi2%*bipush 6%*call%*if%Y3 %2")
-
-(define_insn "*rev_bluopdi"
- [(set (pc)
- (if_then_else
- (match_operator:DI 3 "pj_unsigned_comparison_operator"
- [(match_operand:DI 0 "pj_source_operand" "gS")
- (match_operand:DI 1 "pj_source_operand" "gS")])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "%D0%D1%*ipush __pjucmpdi2%*bipush 6%*call%*if%Z3 %2")
-
-(define_insn "*blopsf"
- [(set (pc)
- (if_then_else
- (match_operator:SF 3 "comparison_operator"
- [(match_operand:SF 0 "pj_source_operand" "gS")
- (match_operand:SF 1 "pj_source_operand" "gS")])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "%S0%S1%*fcmp%X3%*if%Y3 %2")
-
-(define_insn "*rev_bluopsf"
- [(set (pc)
- (if_then_else
- (match_operator:SF 3 "comparison_operator"
- [(match_operand:SF 0 "pj_source_operand" "gS")
- (match_operand:SF 1 "pj_source_operand" "gS")])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "%S0%S1%*fcmp%X3%*if%Z3 %2")
-
-(define_insn "*blopdf"
- [(set (pc)
- (if_then_else
- (match_operator:DF 3 "comparison_operator"
- [(match_operand:DF 0 "pj_source_operand" "gS")
- (match_operand:DF 1 "pj_source_operand" "gS")])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "%D0%D1%*dcmp%X3%*if%Y3 %2")
-
-(define_insn "*rev_bluopdf"
- [(set (pc)
- (if_then_else
- (match_operator:DF 3 "comparison_operator"
- [(match_operand:DF 0 "pj_source_operand" "gS")
- (match_operand:DF 1 "pj_source_operand" "gS")])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "%D0%D1%*dcmp%X3%*if%Z3 %2")
-
-\f
-;; call instructions
-
-(define_insn "pj_call"
- [(call (mem:QI (match_operand:SI 0 "pj_source_operand" "gS"))
- (match_operand:SI 1 "immediate_operand" "i"))]
- ""
- "%C0%E1%S0%S1%*call")
-
-(define_insn "pj_call_value"
- [(set (match_operand 0 "nonimmediate_operand" "=gD")
- (call (mem:QI (match_operand:SI 1 "pj_source_operand" "gS"))
- (match_operand:SI 2 "immediate_operand" "i")))]
-
- ""
- "%C1%E2%S1%S2%*call")
-
-(define_expand "call"
- [(call (match_operand:SI 0 "pj_source_operand" "gS")
- (match_operand:SI 1 "immediate_operand" "i"))
- (use (match_operand:SI 2 "register_operand" "r"))
- (use (match_operand:SI 3 "" ""))]
- ""
- "{
- emit_call_insn (gen_pj_call (XEXP (operands[0], 0),
- pj_workout_arg_words (operands[1],
- operands[2])));
- DONE;
- }")
-
-(define_expand "call_value"
- [(set (match_operand:SI 0 "nonimmediate_operand" "gS")
- (call (match_operand:SI 1 "pj_source_operand" "gS")
- (match_operand:SI 2 "immediate_operand" "i")))
- (use (match_operand:SI 3 "register_operand" "r"))
- (use (match_operand:SI 4 "" ""))]
- ""
- "{
- emit_call_insn (gen_pj_call_value (operands[0],
- XEXP (operands[1], 0),
- pj_workout_arg_words (operands[2],
- operands[3])));
- DONE;
- }")
-
-\f
-;; No-op instruction.
-
-(define_insn "nop"
- [(const_int 0)]
- ""
- "nop")
-
-\f
-;; Jump instructions
-
-(define_insn "jump"
- [(set (pc) (label_ref (match_operand 0 "" "")))]
- ""
- "%*goto %l0")
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:SI 0 "pj_source_operand" "gS"))]
- ""
- "%S0%*write_pc")
-
-(define_insn "casesi"
- [(set (pc)
- (if_then_else
- (leu (minus:SI (match_operand:SI 0 "pj_source_operand" "gS")
- (match_operand:SI 1 "immediate_operand" "i"))
- (match_operand:SI 2 "immediate_operand" "i"))
- (plus:SI (sign_extend:SI
- (mem:SI
- (plus:SI (pc)
- (mult:SI (minus:SI (match_dup 0)
- (match_dup 1))
- (const_int 4)))))
- (label_ref (match_operand 3 "" "")))
- (label_ref (match_operand 4 "" ""))))]
- ""
- "%S0\\n%3i:%*tableswitch\\n\\t%*.align 2%*.long %4-%3i%*.long %1%*.long %1+%2")
-\f
-;; Sign-extend move instructions.
-
-(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=gD")
- (float_extend:DF (match_operand:SF 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*f2d%R0")
-
-(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (sign_extend:SI (match_operand:HI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*bipush 16%*ishl%*bipush 16%*ishr%R0")
-
-(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (sign_extend:SI (match_operand:QI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*bipush 24%*ishl%*bipush 24%*ishr%R0")
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=gD")
- (sign_extend:HI (match_operand:QI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*bipush 24%*ishl%*bipush 24%*ishr%R0")
-
-(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=gD")
- (sign_extend:DI (match_operand:SI 1 "pj_source_operand" "gS")))]
- ""
- "%S1%*i2l%R0")
-
-\f
-;; non local control flow.
-
-(define_expand "save_stack_nonlocal"
- [(set (match_operand 0 "nonimmediate_operand" "=gD")
- (match_operand 1 "pj_source_operand" "gS"))]
- ""
- "{
- rtx reg = force_reg (Pmode, XEXP (operands[0], 0));
- rtx addr0 = gen_rtx_MEM (SImode,reg);
- rtx addr1 = gen_rtx_MEM (SImode, gen_rtx_PRE_INC (SImode, reg));
- rtx addr2 = gen_rtx_MEM (SImode, gen_rtx_PRE_INC (SImode, reg));
-
- emit_move_insn (addr0, gen_rtx_REG (SImode, 64));
- emit_move_insn (addr1, gen_rtx_REG (SImode, 72));
- emit_move_insn (addr2, gen_rtx_REG (SImode, 73));
-
- DONE;
- }")
-
-(define_insn "restore_stack_nonlocal_helper"
- [(set (reg:SI 64) (mem:SI (match_operand:SI 0 "register_operand" "r")))
- (set (reg:SI 72) (mem:SI (pre_inc:SI (match_dup 0))))
- (set (reg:SI 73) (mem:SI (pre_inc:SI (match_dup 0))))]
- ""
- "%S0%*load_word%*write_global0%*iinc %J0,4%S0%*load_word%*iinc %J0,4%S0%*load_word%*write_vars%*write_optop")
-
-(define_expand "restore_stack_nonlocal"
- [(set (match_operand 0 "nonimmediate_operand" "=gD")
- (match_operand 1 "pj_source_operand" "gS"))]
- ""
- "{
- rtx reg = force_reg (Pmode, XEXP (operands[1], 0));
- emit_insn (gen_restore_stack_nonlocal_helper (reg));
- DONE;
- }")
-
-(define_insn "nonlocal_goto_helper"
- [(set (reg:SI 64) (mem:SI (match_operand:SI 0 "register_operand" "r")))
- (set (reg:SI 72) (mem:SI (pre_inc:SI (match_dup 0))))
- (set (reg:SI 73) (mem:SI (pre_inc:SI (match_dup 0))))
- (set (pc) (match_operand:SI 1 "pj_source_operand" "gS"))]
- ""
- "%S0%*load_word%*write_global0%*iinc %J0,4%*%S0%*load_word%*%S1%*iinc %J0,4%*%S0%*load_word%*iinc %J0,4%*write_vars%*return0")
-
-(define_expand "nonlocal_goto"
- [(match_operand:SI 0 "pj_source_operand" "")
- (match_operand:SI 1 "pj_source_operand" "")
- (match_operand:SI 2 "pj_source_operand" "")
- (match_operand:SI 3 "" "")]
- ""
- "{
- operands[2] = force_reg (Pmode, XEXP (operands[2], 0));
- emit_move_insn (hard_frame_pointer_rtx, operands[0]);
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- emit_insn (gen_nonlocal_goto_helper (operands[2], operands[1]));
- emit_barrier ();
- DONE;
- }")
-\f
-;; Function overhead.
-
-(define_expand "prologue"
- [(const_int 0)]
- ""
- "pj_expand_prologue (); DONE;")
-
-(define_expand "epilogue"
- [(return)]
- ""
- "pj_expand_epilogue();")
-
-(define_insn "return"
- [(return)]
- "reload_completed"
- "%*return0")
-
-(define_insn "tm_frame"
- [(use (match_operand:SI 0 "pj_source_operand" "gS"))
- (set (reg:SI 73)
- (minus:SI (reg:SI 73)
- (mult:SI (match_operand:SI 1 "pj_source_operand" "gS")
- (const_int 4))))]
-
- ""
- "%S0%S1%*tm_frame")
-
-(define_insn "varargs"
- [(unspec_volatile [(match_operand:SI 0 "pj_source_operand" "gS")] 10)]
- ""
- "%S0%*jsr_w __vhelper")
-
-(define_insn "varargs_finish"
- [(unspec_volatile [(match_operand:SI 0 "pj_source_operand" "gS")] 11)]
- ""
- "%*iload %J0%*write_global0")
-\f
-;; Extensions to picoJava.
-
-(define_insn "strlensi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
- (unspec:SI [(match_operand:BLK 1 "memory_operand" "gS")
- (match_operand:QI 2 "pj_source_operand" "gS")
- (match_operand:SI 3 "immediate_operand" "gS")] 0))
- (clobber (reg:SI 65))]
- "TARGET_TM_EXTENSIONS"
- "%I1%S2%S3%*iconst_0%*write_global1%*tm_strlensi%R0")
-
-(define_insn "movstrsi"
- [(set (match_operand:BLK 0 "memory_operand" "=gS")
- (match_operand:BLK 1 "memory_operand" "gS"))
- (use (match_operand:SI 2 "pj_source_operand" "gS"))
- (use (match_operand:SI 3 "pj_source_operand" "gS"))
- (clobber (reg:SI 65))]
- "TARGET_TM_EXTENSIONS"
- "%I0%I1%S2%S3%*iconst_0%*write_global1%*tm_movstrsi")
-
-(define_insn "clrstrsi"
- [(set (match_operand:BLK 0 "memory_operand" "=gS")
- (const_int 0))
- (use (match_operand:SI 1 "pj_source_operand" "gS"))
- (use (match_operand:SI 2 "pj_source_operand" "gS"))
- (clobber (reg:SI 65))]
- "TARGET_TM_EXTENSIONS"
- "%I0%*iconst_0%S1%S2%*iconst_0%*write_global1%*tm_memsetsi")
-
-(define_insn "cmpstrsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=gD")
- (compare:SI (match_operand:BLK 1 "memory_operand" "g")
- (match_operand:BLK 2 "memory_operand" "g")))
- (use (match_operand:SI 3 "pj_source_operand" "gS"))
- (use (match_operand:SI 4 "pj_source_operand" "gS"))
- (clobber (reg:SI 65))]
- "TARGET_TM_EXTENSIONS"
- "%I1%I2%S3%S4%*iconst_0%*write_global1%*tm_cmpstrsi%R0")
+++ /dev/null
-#define TARGET_LITTLE_ENDIAN_DEFAULT 1
+++ /dev/null
-LIB1ASMSRC = pj/lib1funcs.S
-LIB1ASMFUNCS = vhelper pjucmpdi2
-
-# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
-# end labels to the .ctors and .dtors section when we link using gcc.
-
-EXTRA_PARTS=crtbegin.o crtend.o
+++ /dev/null
-/* Definitions for rtems targeting a SPARC using a.out.
- Copyright (C) 1996, 1997, 2000, 2002 Free Software Foundation, Inc.
- Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Specify predefined symbols in preprocessor. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -D__GCC_NEW_VARARGS__ -D__rtems__ \
- -Asystem=rtems"
+++ /dev/null
-/* Definitions of target machine for GNU compiler. AT&T we32000 version.
- Copyright (C) 2000
- Free Software Foundation, Inc.
- Contributed by John Wehle (john@feith1.uucp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifdef RTX_CODE
-extern void output_move_double PARAMS ((rtx *));
-extern void output_push_double PARAMS ((rtx *));
-#endif /* RTX_CODE */
+++ /dev/null
-/* Subroutines for insn-output.c for AT&T we32000 Family.
- Copyright (C) 1991, 1992, 1997, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
- Contributed by John Wehle (john@feith1.uucp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-#include "config.h"
-#include "system.h"
-#include "insn-config.h"
-#include "rtl.h"
-#include "function.h"
-#include "real.h"
-#include "recog.h"
-#include "output.h"
-#include "regs.h"
-#include "tree.h"
-#include "expr.h"
-#include "hard-reg-set.h"
-#include "tm_p.h"
-#include "target.h"
-#include "target-def.h"
-
-static void we32k_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void we32k_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-\f
-/* Initialize the GCC target structure. */
-#undef TARGET_ASM_ALIGNED_HI_OP
-#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
-#undef TARGET_ASM_ALIGNED_SI_OP
-#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
-
-#undef TARGET_ASM_FUNCTION_PROLOGUE
-#define TARGET_ASM_FUNCTION_PROLOGUE we32k_output_function_prologue
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE we32k_output_function_epilogue
-
-struct gcc_target targetm = TARGET_INITIALIZER;
-\f
-/* Generate the assembly code for function entry. FILE is a stdio
- stream to output the code to. SIZE is an int: how many units of
- temporary storage to allocate.
-
- Refer to the array `regs_ever_live' to determine which registers to
- save; `regs_ever_live[I]' is nonzero if register number I is ever
- used in the function. This function is responsible for knowing
- which registers should not be saved even if used. */
-
-static void
-we32k_output_function_prologue (file, size)
- FILE *file;
- HOST_WIDE_INT size;
-{
- register int nregs_to_save;
- register int regno;
-
- nregs_to_save = 0;
- for (regno = 8; regno > 2; regno--)
- if (regs_ever_live[regno] && ! call_used_regs[regno])
- nregs_to_save = (9 - regno);
-
- fprintf (file, "\tsave &%d\n", nregs_to_save);
- if (size)
- fprintf (file, "\taddw2 &%d,%%sp\n", (size + 3) & ~3);
-}
-
-/* This function generates the assembly code for function exit.
- Args are as for output_function_prologue ().
-
- The function epilogue should not depend on the current stack
- pointer! It should use the frame pointer only. This is mandatory
- because of alloca; we also take advantage of it to omit stack
- adjustments before returning. */
-
-static void
-we32k_output_function_epilogue (file, size)
- FILE *file;
- HOST_WIDE_INT size ATTRIBUTE_UNUSED;
-{
- register int nregs_to_restore;
- register int regno;
-
- nregs_to_restore = 0;
- for (regno = 8; regno > 2; regno--)
- if (regs_ever_live[regno] && ! call_used_regs[regno])
- nregs_to_restore = (9 - regno);
-
- fprintf (file, "\tret &%d\n", nregs_to_restore);
-}
-
-void
-output_move_double (operands)
- rtx *operands;
-{
- rtx lsw_operands[2];
- rtx lsw_sreg = NULL;
- rtx msw_dreg = NULL;
-
- if (GET_CODE (operands[0]) == REG)
- {
- lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- msw_dreg = operands[0];
- }
- else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adjust_address (operands[0], SImode, 4);
- else
- abort ();
-
- if (GET_CODE (operands[1]) == REG)
- {
- lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- lsw_sreg = lsw_operands[1];
- }
- else if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
- {
- lsw_operands[1] = adjust_address (operands[1], SImode, 4);
- lsw_sreg = operands[1];
- for ( ; ; )
- {
- if (REG_P (lsw_sreg))
- break;
- if (CONSTANT_ADDRESS_P (lsw_sreg))
- {
- lsw_sreg = NULL;
- break;
- }
- if (GET_CODE (lsw_sreg) == MEM)
- {
- lsw_sreg = XEXP (lsw_sreg, 0);
- continue;
- }
- if (GET_CODE (lsw_sreg) == PLUS)
- {
- if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 1)))
- {
- lsw_sreg = XEXP (lsw_sreg, 0);
- continue;
- }
- else if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 0)))
- {
- lsw_sreg = XEXP (lsw_sreg, 1);
- continue;
- }
- }
- abort ();
- }
- }
- else if (GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
- operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
- }
- else if (GET_CODE (operands[1]) == CONST_INT)
- {
- lsw_operands[1] = operands[1];
- operands[1] = const0_rtx;
- }
- else
- abort ();
-
- if (!msw_dreg || !lsw_sreg || REGNO (msw_dreg) != REGNO (lsw_sreg))
- {
- output_asm_insn ("movw %1, %0", operands);
- output_asm_insn ("movw %1, %0", lsw_operands);
- }
- else
- {
- output_asm_insn ("movw %1, %0", lsw_operands);
- output_asm_insn ("movw %1, %0", operands);
- }
-}
-
-void
-output_push_double (operands)
- rtx *operands;
-{
- rtx lsw_operands[1];
-
- if (GET_CODE (operands[0]) == REG)
- lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adjust_address (operands[0], SImode, 4);
- else if (GET_CODE (operands[0]) == CONST_DOUBLE)
- {
- lsw_operands[0] = GEN_INT (CONST_DOUBLE_HIGH (operands[0]));
- operands[0] = GEN_INT (CONST_DOUBLE_LOW (operands[0]));
- }
- else if (GET_CODE (operands[0]) == CONST_INT)
- {
- lsw_operands[0] = operands[0];
- operands[0] = const0_rtx;
- }
- else
- abort ();
-
- output_asm_insn ("pushw %0", operands);
- output_asm_insn ("pushw %0", lsw_operands);
-}
+++ /dev/null
-/* Definitions of target machine for GNU compiler. AT&T we32000 version.
- Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
- 2001, 2002 Free Software Foundation, Inc.
- Contributed by John Wehle (john@feith1.uucp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define CPP_PREDEFINES "-Dwe32000 -Du3b2 -Dunix -Asystem=unix -Acpu=we32000 -Amachine=we32000"
-
-/* Print subsidiary information on the compiler version in use. */
-
-#define TARGET_VERSION fprintf (stderr, " (we32000)");
-
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags. */
-
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
- { { "", TARGET_DEFAULT, 0}}
-
-#define TARGET_DEFAULT 0
-
-\f
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields. */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-/* That is true on the we32000. */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword is lowest numbered. */
-/* For we32000 we can decide arbitrarily
- since there are no machine instructions for them. */
-#define WORDS_BIG_ENDIAN 1
-
-/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD 4
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned. */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure. */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this. */
-#define BIGGEST_ALIGNMENT 32
-
-/* Every structure's size must be a multiple of this. */
-#define STRUCTURE_SIZE_BOUNDARY 32
-
-/* Define this if move instructions will actually fail to work
- when given unaligned data. */
-#define STRICT_ALIGNMENT 1
-
-/* Define number of bits in most basic integer type.
- (If undefined, default is BITS_PER_WORD). */
-#define INT_TYPE_SIZE 32
-
-/* Integer bit fields should have the same size and alignment
- as actual integers */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Specify the size_t type. */
-#define SIZE_TYPE "unsigned int"
-\f
-/* Standard register usage. */
-
-/* Number of actual hardware registers.
- The hardware registers are assigned numbers for the compiler
- from 0 to just below FIRST_PSEUDO_REGISTER.
- All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator. */
-#define FIXED_REGISTERS \
- {0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 1, 1, 1, 1, 1, 1, 1, }
-
-/* 1 for registers not available across function calls.
- These must include the FIXED_REGISTERS and also any
- registers that can be used without being saved.
- The latter must include the registers where values are returned
- and the register where structure-value addresses are passed.
- Aside from that, you can include as many other registers as you like. */
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 0, 0, 0, 0, 0, \
- 0, 1, 1, 1, 1, 1, 1, 1, }
-
-/* Make sure everything's fine if we *don't* have a given processor.
- This assumes that putting a register in fixed_regs will keep the
- compilers mitt's completely off it. We don't bother to zero it out
- of register classes. */
-/* #define CONDITIONAL_REGISTER_USAGE */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
- to hold something of mode MODE.
- This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) 0
-
-/* Specify the registers used for certain standard purposes.
- The values of these macros are register numbers. */
-
-/* Register used for the program counter */
-#define PC_REGNUM 15
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM 12
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 9
-
-/* Value should be nonzero if functions must have frame pointers.
- Zero means the frame pointer need not be set up (and parms
- may be accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 10
-
-/* Register in which static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM 8
-
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM 2
-
-/* Order in which to allocate registers. */
-#define REG_ALLOC_ORDER \
- {0, 1, 8, 7, 6, 5, 4, 3}
-\f
-/* Define the classes of registers for register constraints in the
- machine description. Also define ranges of constants.
-
- One of the classes must always be named ALL_REGS and include all hard regs.
- If there is more than one class, another class must be named NO_REGS
- and contain no registers.
-
- The name GENERAL_REGS must be the name of a class (or an alias for
- another name such as ALL_REGS). This is the class of registers
- that is allowed by "g" or "r" in a register constraint.
- Also, registers outside this class are allocated only when
- instructions express preferences for them.
-
- The classes must be numbered in nondecreasing order; that is,
- a larger-numbered class must never be contained completely
- in a smaller-numbered class.
-
- For any two classes, it is very desirable that there be another
- class that represents their union. */
-
-enum reg_class { NO_REGS, GENERAL_REGS,
- ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file. */
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", "GENERAL_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
- This is an initializer for a vector of HARD_REG_SET
- of length N_REG_CLASSES. */
-
-#define REG_CLASS_CONTENTS \
-{ \
- {0}, /* NO_REGS */ \
- {0x000017ff}, /* GENERAL_REGS */ \
- {0x0000ffff}, /* ALL_REGS */ \
-}
-
-/* The same information, inverted:
- Return the class number of the smallest class containing
- reg number REGNO. This could be a conditional expression
- or could index an array. */
-
-#define REGNO_REG_CLASS(REGNO) \
- (((REGNO) < 11 || (REGNO) == 12) ? GENERAL_REGS : ALL_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.
- We do a trick here to modify the effective constraints on the
- machine description; we zorch the constraint letters that aren't
- appropriate for a specific target. This allows us to guarantee
- that a specific kind of register will not be used for a given target
- without fiddling with the register classes above. */
-
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'r' ? GENERAL_REGS : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C. */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) 0
-
-/*
- */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
-
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS. */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-\f
-/* Stack layout; function entry, exit and calling. */
-
-/* Define this if pushing a word on the stack
- makes the stack pointer a smaller address. */
-/* #define STACK_GROWS_DOWNWARD */
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- that is, each additional local variable allocated
- goes at a more negative offset in the frame. */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated. */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by. */
-#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
-
-/* Offset of first parameter from the argument pointer register value. */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is 1 if returning from a function call automatically
- pops the arguments described by the number-of-args field in the call.
- FUNDECL is the declaration node of the function (as a tree),
- FUNTYPE is the data type of the function (as a tree),
- or for a library call it is an identifier node for the subroutine name. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-
-/* On the we32000 the return value is in r0 regardless. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
- assuming the value has mode MODE. */
-
-/* On the we32000 the return value is in r0 regardless. */
-
-#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
-
-/* 1 if N is a possible register number for a function value.
- On the we32000, r0 is the only register thus used. */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* Define this if PCC uses the nonreentrant convention for returning
- structure and union values. */
-
-/* #define PCC_STATIC_STRUCT_RETURN */
-
-/* 1 if N is a possible register number for function argument passing.
- On the we32000, no registers are used in this way. */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-\f
-/* Define a data type for recording info about an argument list
- during the scan of that argument list. This data type should
- hold all necessary information about the function itself
- and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go.
-
- On the we32k, this is a single integer, which is a number of bytes
- of arguments scanned so far. */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
- for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0.
-
- On the we32k, the offset starts at 0. */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- (TYPE is null for libcalls where that information may not be available.) */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- ((CUM) += ((MODE) != BLKmode \
- ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
- : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
- Value is zero to push the argument on the stack,
- or a hard register in which to store the argument.
-
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- CUM is a variable of type CUMULATIVE_ARGS which gives info about
- the preceding args and about the function being called.
- NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis). */
-
-/* On the we32000 all args are pushed */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* For an arg passed partly in registers and partly in memory,
- this is the number of registers used.
- For args passed entirely in registers or entirely in memory, zero. */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
- for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tmovw &.LP%d,%%r0\n\tjsb _mcount\n", (LABELNO))
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
- the stack pointer does not matter. The value is tested only in
- functions that have frame pointers.
- No definition is equivalent to always zero. */
-
-#define EXIT_IGNORE_STACK 0
-
-/* Store in the variable DEPTH the initial difference between the
- frame pointer reg contents and the stack pointer reg contents,
- as of the start of the function body. This depends on the layout
- of the fixed parts of the stack frame and on how registers are saved.
-
- On the we32k, FRAME_POINTER_REQUIRED is always 1, so the definition of this
- macro doesn't matter. But it must be defined. */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0;
-
-/* Output assembler code for a block containing the constant parts
- of a trampoline, leaving space for the variable parts. */
-
-/* On the we32k, the trampoline contains two instructions:
- mov #STATIC,%r8
- jmp #FUNCTION */
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
-{ \
- assemble_aligned_integer (2, GEN_INT (0x844f)); \
- assemble_aligned_integer (2, const0_rtx); \
- assemble_aligned_integer (2, const0_rtx); \
- assemble_aligned_integer (1, GEN_INT (0x48)); \
- assemble_aligned_integer (2, GEN_INT (0x247f)); \
- assemble_aligned_integer (2, const0_rtx); \
- assemble_aligned_integer (2, const0_rtx); \
-}
-
-/* Length in units of the trampoline for entering a nested function. */
-
-#define TRAMPOLINE_SIZE 13
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
- FNADDR is an RTX for the address of the function's pure code.
- CXT is an RTX for the static chain value for the function. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 9)), FNADDR); \
-}
-\f
-/* Generate calls to memcpy() and memset() rather
- than bcopy() and bzero() */
-#define TARGET_MEM_FUNCTIONS
-\f
-/* Addressing modes, and classification of registers for them. */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) 0
-
-#define REGNO_OK_FOR_BASE_P(REGNO) \
- ((REGNO) < 11 || (REGNO) == 12 || \
- (unsigned)reg_renumber[REGNO] < 11 || (unsigned)reg_renumber[REGNO] == 12)
-\f
-/* Maximum number of registers that can appear in a valid memory address. */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address. */
-
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) 0
-
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) \
- (REGNO(X) < 11 || REGNO(X) == 12 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address. */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
-{ register rtx Addr = X; \
- if ((MODE) == QImode || (MODE) == HImode || \
- (MODE) == PSImode || (MODE) == SImode || (MODE) == SFmode) \
- if (GET_CODE(Addr) == MEM) \
- Addr = XEXP(Addr, 0); \
- if (CONSTANT_ADDRESS_P(Addr)) \
- goto LABEL; \
- if (REG_P(Addr) && REG_OK_FOR_BASE_P(Addr)) \
- goto LABEL; \
- if (GET_CODE(Addr) == PLUS && \
- ((REG_P(XEXP(Addr, 0)) && REG_OK_FOR_BASE_P(XEXP(Addr, 0)) && \
- CONSTANT_ADDRESS_P(XEXP(Addr, 1))) || \
- (REG_P(XEXP(Addr, 1)) && REG_OK_FOR_BASE_P(XEXP(Addr, 1)) && \
- CONSTANT_ADDRESS_P(XEXP(Addr, 0))))) \
- goto LABEL; \
-}
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
- to be legitimate. If we find one, return the new, valid address.
- This macro is used in only one place: `memory_address' in explow.c.
-
- OLDX is the address as it was before break_out_memory_refs was called.
- In some cases it is useful to look at this to decide what needs to be done.
-
- MODE and WIN are passed so that this macro can use
- GO_IF_LEGITIMATE_ADDRESS.
-
- It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) { }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
- has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) { }
-\f
-/* Specify the machine mode that this machine uses
- for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this as 1 if `char' should by default be signed; else as 0. */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Max number of bytes we can move from memory to memory
- in one reasonably fast instruction. */
-#define MOVE_MAX 4
-
-/* Nonzero if access to memory by bytes is slow and undesirable. */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
- few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
- and some other value for true. This is the value stored for true. */
-
-#define STORE_FLAG_VALUE (-1)
-
-/* When a prototype says `char' or `short', really pass an `int'. */
-#define PROMOTE_PROTOTYPES 1
-
-/* Specify the machine mode that pointers have.
- After generation of rtl, the compiler makes no further distinction
- between pointers and any other objects of this machine mode. */
-#define Pmode SImode
-
-/* A function address in a call instruction
- is a byte address (for indexing purposes)
- so give the MEM rtx a byte's mode. */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-#define CONST_COSTS(RTX,CODE, OUTER_CODE) \
- case CONST_INT: \
- if (INTVAL (RTX) >= -16 && INTVAL (RTX) <= 63) return 0; \
- if (INTVAL (RTX) >= -128 && INTVAL (RTX) <= 127) return 1; \
- if (INTVAL (RTX) >= -32768 && INTVAL (RTX) <= 32767) return 2; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 3; \
- case CONST_DOUBLE: \
- return 5;
-\f
-/* Tell final.c how to eliminate redundant test instructions. */
-
-/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ \
- { CC_STATUS_INIT; } \
-}
-\f
-/* Control the assembler format that we output. */
-
-/* Use crt1.o as a startup file and crtn.o as a closing file. */
-
-#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-#define ENDFILE_SPEC "crtn.o%s"
-
-/* The .file command should always begin the output. */
-
-#define ASM_FILE_START(FILE) output_file_directive ((FILE), main_input_filename)
-
-/* Output to assembler file text saying following lines
- may contain character constants, extra white space, comments, etc. */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
- no longer contain unusual constructs. */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output before code. */
-
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-/* Output before writable data. */
-
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* Read-only data goes in the data section because AT&T's assembler
- doesn't guarantee the proper alignment of data in the text section
- even if an align statement is used. */
-
-#define READONLY_DATA_SECTION data_section
-
-/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "r8", "fp", "ap", "psw", "sp", "pcbp", "isp", "pc" }
-
-/* Output SDB debugging info in response to the -g option. */
-
-#define SDB_DEBUGGING_INFO
-
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
- do { \
- fputs (".globl ", FILE); \
- assemble_name (FILE, NAME); \
- fputs ("\n", FILE); \
- } while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
- the symbol_ref name of an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class.
- This is suitable for output with `assemble_name'. */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, ".%s%d", PREFIX, NUM)
-
-/* This is how to output an internal numbered label which
- labels a jump table. */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
- do { \
- ASM_OUTPUT_ALIGN (FILE, 2); \
- ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
- } while (0)
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-do { \
- const unsigned char *s; \
- size_t i, limit = (LEN); \
- for (i = 0, s = (const unsigned char *)(PTR); i < limit; s++, i++) \
- { \
- if ((i % 8) == 0) \
- fprintf ((FILE),"%s\t.byte\t",(i?"\n":"")); \
- fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
- } \
- fputs ("\n", (FILE)); \
-} while (0)
-
-/* This is how to output an insn to push a register on the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tpushw %s\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
- It need not be very fast code. */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tPOPW %s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- fprintf (FILE, "\t.word .L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative. */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
- that says to advance the location counter
- to a multiple of 2**LOG bytes. */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG) != 0) \
- fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-/* This is how to output an assembler line
- that says to advance the location counter by SIZE bytes. */
-
-/* The `space' pseudo in the text segment outputs nop insns rather than 0s,
- so we must output 0s explicitly in the text segment. */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) do { \
- if (in_text_section ()) \
- { \
- int i; \
- for (i = 0; i < (SIZE) - 20; i += 20) \
- fprintf (FILE, "\t.byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n"); \
- if (i < (SIZE)) \
- { \
- fprintf (FILE, "\t.byte 0"); \
- i++; \
- for (; i < (SIZE); i++) \
- fprintf (FILE, ",0"); \
- fprintf (FILE, "\n"); \
- } \
- } \
- else \
- fprintf ((FILE), "\t.set .,.+%u\n", (SIZE)); } while (0)
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
- do { \
- data_section(); \
- fputs ("\t.comm ", (FILE)); \
- assemble_name ((FILE), (NAME)); \
- fprintf ((FILE), ",%u\n", (SIZE)); \
- } while (0)
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
- do { \
- data_section(); \
- ASM_OUTPUT_ALIGN ((FILE), 2); \
- ASM_OUTPUT_LABEL ((FILE), (NAME)); \
- fprintf ((FILE), "\t.zero %u\n", (SIZE)); \
- } while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Output #ident as a .ident. */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME)
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
- CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
- For `%' followed by punctuation, CODE is the punctuation and X is null. */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) 0
-
-#define PRINT_OPERAND(FILE, X, CODE) \
-{ if (GET_CODE (X) == REG) \
- fprintf (FILE, "%%%s", reg_names[REGNO (X)]); \
- else if (GET_CODE (X) == MEM) \
- output_address (XEXP (X, 0)); \
- else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
- { \
- REAL_VALUE_TYPE r; \
- long l; \
- \
- REAL_VALUE_FROM_CONST_DOUBLE (r, X); \
- REAL_VALUE_TO_TARGET_SINGLE (r, l); \
- fprintf (FILE, "&0x%lx", l); \
- } \
- else { putc ('&', FILE); output_addr_const (FILE, X); }}
-\f
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-{ register rtx Addr = ADDR; \
- rtx offset; \
- rtx reg; \
- if (GET_CODE (Addr) == MEM) { \
- putc ('*', FILE); \
- Addr = XEXP (Addr, 0); \
- if (GET_CODE (Addr) == REG) \
- putc ('0', FILE); \
- } \
- switch (GET_CODE (Addr)) \
- { \
- case REG: \
- fprintf (FILE, "(%%%s)", reg_names[REGNO (Addr)]); \
- break; \
- \
- case PLUS: \
- offset = NULL; \
- if (CONSTANT_ADDRESS_P (XEXP (Addr, 0))) \
- { \
- offset = XEXP (Addr, 0); \
- Addr = XEXP (Addr, 1); \
- } \
- else if (CONSTANT_ADDRESS_P (XEXP (Addr, 1))) \
- { \
- offset = XEXP (Addr, 1); \
- Addr = XEXP (Addr, 0); \
- } \
- else \
- abort(); \
- if (REG_P (Addr)) \
- reg = Addr; \
- else \
- abort(); \
- output_addr_const(FILE, offset); \
- fprintf(FILE, "(%%%s)", reg_names[REGNO(reg)]); \
- break; \
- \
- default: \
- if ( !CONSTANT_ADDRESS_P(Addr)) \
- abort(); \
- output_addr_const (FILE, Addr); \
- }}
-\f
-/*
-Local variables:
-version-control: t
-End:
-*/
+++ /dev/null
-;; Machine description for GNU compiler, AT&T we32000 Version
-;; Copyright (C) 1991, 1992, 1994, 1998, 1999, 2001
-;; Free Software Foundation, Inc.
-;; Contributed by John Wehle (john@feith1.uucp)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- instruction definitions
-
-;;- @@The original PO technology requires these to be ordered by speed,
-;;- @@ so that assigner will pick the fastest.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- When naming insn's (operand 0 of define_insn) be careful about using
-;;- names from other targets machine descriptions.
-\f
-;; move instructions
-
-(define_insn ""
- [(set (match_operand:DF 0 "push_operand" "=m")
- (match_operand:DF 1 "general_operand" "mrF"))]
- ""
- "*
- {
- output_push_double(&operands[1]);
-
- return \"\";
- }")
-
-(define_insn "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=mr")
- (match_operand:DF 1 "general_operand" "mrF"))]
- ""
- "*
- {
- output_move_double(operands);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (match_operand:SF 0 "push_operand" "=m")
- (match_operand:SF 1 "general_operand" "mrF"))]
- ""
- "pushw %1")
-
-(define_insn "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=mr")
- (match_operand:SF 1 "general_operand" "mrF"))]
- ""
- "movw %1, %0")
-
-(define_insn ""
- [(set (match_operand:DI 0 "push_operand" "=m")
- (match_operand:DI 1 "general_operand" "mriF"))]
- ""
- "*
- {
- output_push_double(&operands[1]);
-
- return \"\";
- }")
-
-(define_insn "movdi"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=mr")
- (match_operand:DI 1 "general_operand" "mriF"))]
- ""
- "*
- {
- output_move_double(operands);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (match_operand:SI 0 "push_operand" "=m")
- (match_operand:SI 1 "general_operand" "mri"))]
- ""
- "pushw %1")
-
-(define_insn "movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (match_operand:SI 1 "general_operand" "mri"))]
- ""
- "movw %1, %0")
-
-(define_insn "movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (match_operand:HI 1 "general_operand" "mri"))]
- ""
- "movh %1, %0")
-
-(define_insn "movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (match_operand:QI 1 "general_operand" "mri"))]
- ""
- "movb %1, %0")
-\f
-;; add instructions
-
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:DI 2 "general_operand" "oriF")))]
- ""
- "*
- {
- rtx label[1];
- rtx lsw_operands[3];
-
- if (GET_CODE (operands[0]) == REG)
- lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else
- if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adjust_address (operands[0], SImode, 4);
- else
- abort();
-
- if (GET_CODE (operands[2]) == REG)
- lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
- else
- if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adjust_address (operands[2], SImode, 4);
- else
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
- {
- lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
- operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
- }
- else
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- lsw_operands[2] = operands[2];
- operands[2] = const0_rtx;
- }
- else
- abort();
-
- label[0] = gen_label_rtx();
- LABEL_NUSES(label[0]) = 1;
-
- output_asm_insn(\"addw2 %2, %0\", operands);
- output_asm_insn(\"addw2 %2, %0\", lsw_operands);
- output_asm_insn(\"BCCB %l0\", label);
- output_asm_insn(\"INCW %0\", operands);
- output_asm_insn(\"%l0:\", label);
-
- return \"\";
- }")
-
-(define_insn "adddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
- (plus:DI (match_operand:DI 1 "general_operand" "oriF")
- (match_operand:DI 2 "general_operand" "oriF")))]
- ""
- "*
- {
- rtx label[1];
- rtx lsw_operands[3];
-
- if (GET_CODE (operands[0]) == REG)
- lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else
- if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adjust_address(operands[0], SImode, 4);
- else
- abort();
-
- if (GET_CODE (operands[1]) == REG)
- lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- else
- if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
- lsw_operands[1] = adjust_address (operands[1], SImode, 4);
- else
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
- operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
- }
- else
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- lsw_operands[1] = operands[1];
- operands[1] = const0_rtx;
- }
- else
- abort();
-
- if (GET_CODE (operands[2]) == REG)
- lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
- else
- if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adjust_address (operands[2], SImode, 4);
- else
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
- {
- lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
- operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
- }
- else
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- lsw_operands[2] = operands[2];
- operands[2] = const0_rtx;
- }
- else
- abort();
-
- label[0] = gen_label_rtx();
- LABEL_NUSES(label[0]) = 1;
-
- output_asm_insn(\"addw3 %2, %1, %0\", operands);
- output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands);
- output_asm_insn(\"BCCB %l0\", label);
- output_asm_insn(\"INCW %0\", operands);
- output_asm_insn(\"%l0:\", label);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "addw2 %2, %0")
-
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (plus:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "addw3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "addh2 %2, %0")
-
-(define_insn "addhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (plus:HI (match_operand:HI 1 "general_operand" "mri")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "addh3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "addb2 %2, %0")
-
-(define_insn "addqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (plus:QI (match_operand:QI 1 "general_operand" "mri")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "addb3 %2, %1, %0")
-\f
-;; subtract instructions
-
-(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:DI 2 "general_operand" "oriF")))]
- ""
- "*
- {
- rtx label[1];
- rtx lsw_operands[3];
-
- if (GET_CODE (operands[0]) == REG)
- lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else
- if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adjust_address (operands[0], SImode, 4);
- else
- abort();
-
- if (GET_CODE (operands[2]) == REG)
- lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
- else
- if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adjust_address (operands[2], SImode, 4);
- else
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
- {
- lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
- operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
- }
- else
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- lsw_operands[2] = operands[2];
- operands[2] = const0_rtx;
- }
- else
- abort();
-
- label[0] = gen_label_rtx();
- LABEL_NUSES(label[0]) = 1;
-
- output_asm_insn(\"subw2 %2, %0\", operands);
- output_asm_insn(\"subw2 %2, %0\", lsw_operands);
- output_asm_insn(\"BCCB %l0\", label);
- output_asm_insn(\"DECW %0\", operands);
- output_asm_insn(\"%l0:\", label);
-
- return \"\";
- }")
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
- (minus:DI (match_operand:DI 1 "general_operand" "oriF")
- (match_operand:DI 2 "general_operand" "oriF")))]
- ""
- "*
- {
- rtx label[1];
- rtx lsw_operands[3];
-
- if (GET_CODE (operands[0]) == REG)
- lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else
- if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
- lsw_operands[0] = adjust_address (operands[0], SImode, 4);
- else
- abort();
-
- if (GET_CODE (operands[1]) == REG)
- lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
- else
- if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
- lsw_operands[1] = adjust_address (operands[1], SImode, 4);
- else
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- {
- lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
- operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
- }
- else
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- lsw_operands[1] = operands[1];
- operands[1] = const0_rtx;
- }
- else
- abort();
-
- if (GET_CODE (operands[2]) == REG)
- lsw_operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
- else
- if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
- lsw_operands[2] = adjust_address (operands[2], SImode, 4);
- else
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
- {
- lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
- operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
- }
- else
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- lsw_operands[2] = operands[2];
- operands[2] = const0_rtx;
- }
- else
- abort();
-
- label[0] = gen_label_rtx();
- LABEL_NUSES(label[0]) = 1;
-
- output_asm_insn(\"subw3 %2, %1, %0\", operands);
- output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands);
- output_asm_insn(\"BCCB %l0\", label);
- output_asm_insn(\"DECW %0\", operands);
- output_asm_insn(\"%l0:\", label);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "subw2 %2, %0")
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (minus:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "subw3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "subh2 %2, %0")
-
-(define_insn "subhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (minus:HI (match_operand:HI 1 "general_operand" "mri")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "subh3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "subb2 %2, %0")
-
-(define_insn "subqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (minus:QI (match_operand:QI 1 "general_operand" "mri")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "subb3 %2, %1, %0")
-\f
-;; signed multiply instructions
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "mulw2 %2, %0")
-
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (mult:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "mulw3 %2, %1, %0")
-
-;; signed divide instructions
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (div:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "divw2 %2, %0")
-
-(define_insn "divsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (div:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "divw3 %2, %1, %0")
-
-;; signed modulus instruction
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (mod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "modw2 %2, %0")
-
-(define_insn "modsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (mod:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "modw3 %2, %1, %0")
-\f
-;; unsigned divide instruction
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "udivw2 %2, %0")
-
-(define_insn "udivsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (udiv:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "udivw3 %2, %1, %0")
-
-;; unsigned modulus instruction
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (umod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "umodw2 %2, %0")
-
-(define_insn "umodsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (umod:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "umodw3 %2, %1, %0")
-\f
-;; logical-and instructions
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "andw2 %2, %0")
-
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (and:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "andw3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (and:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "andh2 %2, %0")
-
-(define_insn "andhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (and:HI (match_operand:HI 1 "general_operand" "mri")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "andh3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (and:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "andb2 %2, %0")
-
-(define_insn "andqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (and:QI (match_operand:QI 1 "general_operand" "mri")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "andb3 %2, %1, %0")
-\f
-;; inclusive-or instructions
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "orw2 %2, %0")
-
-(define_insn "iorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (ior:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "orw3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (ior:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "orh2 %2, %0")
-
-(define_insn "iorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (ior:HI (match_operand:HI 1 "general_operand" "mri")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "orh3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (ior:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "orb2 %2, %0")
-
-(define_insn "iorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (ior:QI (match_operand:QI 1 "general_operand" "mri")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "orb3 %2, %1, %0")
-\f
-;; exclusive-or instructions
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "xorw2 %2, %0")
-
-(define_insn "xorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (xor:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "xorw3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (xor:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "xorh2 %2, %0")
-
-(define_insn "xorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (xor:HI (match_operand:HI 1 "general_operand" "mri")
- (match_operand:HI 2 "general_operand" "mri")))]
- ""
- "xorh3 %2, %1, %0")
-
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (xor:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "xorb2 %2, %0")
-
-(define_insn "xorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (xor:QI (match_operand:QI 1 "general_operand" "mri")
- (match_operand:QI 2 "general_operand" "mri")))]
- ""
- "xorb3 %2, %1, %0")
-\f
-;; arithmetic shift instructions
-
-(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (ashift:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "LLSW3 %2, %1, %0")
-
-(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (ashiftrt:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "ARSW3 %2, %1, %0")
-
-;; logical shift instructions
-
-(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (lshiftrt:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "LRSW3 %2, %1, %0")
-
-;; rotate instruction
-
-(define_insn "rotrsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (rotatert: SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "general_operand" "mri")))]
- ""
- "ROTW %2, %1, %0")
-\f
-;; negate instructions
-
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (neg:SI (match_operand:SI 1 "general_operand" "mri")))]
- ""
- "mnegw %1, %0")
-
-(define_insn "neghi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (neg:HI (match_operand:HI 1 "general_operand" "mri")))]
- ""
- "mnegh %1, %0")
-
-;; complement instructions
-
-(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (not:SI (match_operand:SI 1 "general_operand" "mri")))]
- ""
- "mcomw %1, %0")
-
-(define_insn "one_cmplhi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (not:HI (match_operand:HI 1 "general_operand" "mri")))]
- ""
- "mcomh %1, %0")
-
-(define_insn "one_cmplqi2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (not:QI (match_operand:QI 1 "general_operand" "mri")))]
- ""
- "mcomb %1, %0")
-\f
-;; test instruction
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information. Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
- [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "mr"))]
- ""
- "TSTW %0")
-
-(define_insn "tsthi"
- [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "mr"))]
- ""
- "TSTH %0")
-
-(define_insn "tstqi"
- [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "mr"))]
- ""
- "TSTB {sbyte}%0")
-
-;; compare instruction
-
-(define_insn "cmpsi"
- [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr")
- (match_operand:SI 1 "general_operand" "mri")))]
- ""
- "CMPW %1, %0")
-
-(define_insn "cmphi"
- [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr")
- (match_operand:HI 1 "general_operand" "mri")))]
- ""
- "*
- {
-
- if (GET_CODE (operands[1]) == CONST_INT &&
- ((unsigned long)INTVAL (operands[1]) & 0x8000L))
- operands[1] = GEN_INT (INTVAL (operands[1]) | 0xffff0000L);
-
- output_asm_insn(\"CMPH %1, %0\",operands);
-
- return \"\";
- }")
-
-(define_insn "cmpqi"
- [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "mr")
- (match_operand:QI 1 "general_operand" "mri")))]
- ""
- "*
- {
-
- if (GET_CODE (operands[1]) == CONST_INT &&
- ((unsigned long)INTVAL (operands[1]) & 0x80L))
- operands[1] = GEN_INT (INTVAL(operands[1]) | 0xffffff00L);
-
- output_asm_insn(\"CMPB {sbyte}%1, {sbyte}%0\",operands);
-
- return \"\";
- }")
-\f
-;; truncate instructions
-
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
- (clobber (reg:SI 1))
- (clobber (reg:SI 2))]
- "REGNO (operands[0]) == 0"
- "*
- {
- output_push_double(&operands[1]);
- output_asm_insn(\"call &2, _fdtos\", operands);
-
- return \"\";
- }")
-
-(define_expand "truncdfsf2"
- [(parallel [(set (reg:SF 0)
- (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
- (clobber (reg:SI 1))
- (clobber (reg:SI 2))])
- (set (match_operand:SF 0 "nonimmediate_operand" "=mr")
- (reg:SF 0))]
- ""
- "")
-
-(define_insn "truncsihi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (truncate:HI (match_operand:SI 1 "general_operand" "mri")))]
- ""
- "movtwh %1, %0")
-
-(define_insn "truncsiqi2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (truncate:QI (match_operand:SI 1 "general_operand" "mri")))]
- ""
- "movtwb %1, %0")
-
-(define_insn "trunchiqi2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
- (truncate:QI (match_operand:HI 1 "general_operand" "mri")))]
- ""
- "movthb %1, %0")
-\f
-;; sign-extend move instructions
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
- (clobber (reg:SI 2))]
- "REGNO (operands[0]) == 0"
- "*
- {
- output_asm_insn(\"pushw %1\", operands);
- output_asm_insn(\"call &1, _fstod\", operands);
-
- return \"\";
- }")
-
-(define_expand "extendsfdf2"
- [(parallel [(set (reg:DF 0)
- (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
- (clobber (reg:SI 2))])
- (set (match_operand:DF 0 "nonimmediate_operand" "=or")
- (reg:DF 0))]
- ""
- "")
-
-(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
- ""
- "movbhw %1, %0")
-
-(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
- ""
- "movbbw %1, %0")
-
-(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
- ""
- "movbbh %1, %0")
-
-;; zero-extend move instructions
-
-(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
- ""
- "movzhw %1, %0")
-
-(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
- ""
- "movzbw %1, %0")
-
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
- (zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
- ""
- "movzbh %1, %0")
-\f
-;; bit field instructions
-
-(define_insn "extzv"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (zero_extract:SI (match_operand:SI 1 "general_operand" "mri")
- (match_operand:SI 2 "immediate_operand" "i")
- (match_operand:SI 3 "general_operand" "mri")))]
- ""
- "*
- {
-
- operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
- output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (zero_extract:SI (match_operand:HI 1 "general_operand" "mri")
- (match_operand:SI 2 "immediate_operand" "i")
- (match_operand:SI 3 "general_operand" "mri")))]
- ""
- "*
- {
-
- operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
- output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (zero_extract:SI (match_operand:QI 1 "general_operand" "mri")
- (match_operand:SI 2 "immediate_operand" "i")
- (match_operand:SI 3 "general_operand" "mri")))]
- ""
- "*
- {
-
- operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
- output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands);
-
- return \"\";
- }")
-
-(define_insn "insv"
- [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr")
- (match_operand:SI 1 "immediate_operand" "i")
- (match_operand:SI 2 "general_operand" "mri"))
- (match_operand:SI 3 "general_operand" "mri"))]
- ""
- "*
- {
-
- operands[1] = GEN_INT (INTVAL (operands[1]) - 1);
- output_asm_insn(\"INSFW %1, %2, %3, %0\",operands);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr")
- (match_operand:SI 1 "immediate_operand" "i")
- (match_operand:SI 2 "general_operand" "mri"))
- (match_operand:SI 3 "general_operand" "mri"))]
- ""
- "*
- {
-
- operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
- output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands);
-
- return \"\";
- }")
-
-(define_insn ""
- [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr")
- (match_operand:SI 1 "immediate_operand" "i")
- (match_operand:SI 2 "general_operand" "mri"))
- (match_operand:SI 3 "general_operand" "mri"))]
- ""
- "*
- {
-
- operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
- output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands);
-
- return \"\";
- }")
-\f
-;; conditional branch instructions
-
-(define_insn "beq"
- [(set (pc) (if_then_else (eq (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "je %l0")
-
-(define_insn "bne"
- [(set (pc) (if_then_else (ne (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jne %l0")
-
-(define_insn "bgt"
- [(set (pc) (if_then_else (gt (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jg %l0")
-
-(define_insn "bgtu"
- [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jgu %l0")
-
-(define_insn "blt"
- [(set (pc) (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jl %l0")
-
-(define_insn "bltu"
- [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jlu %l0")
-
-(define_insn "bge"
- [(set (pc) (if_then_else (ge (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jge %l0")
-
-(define_insn "bgeu"
- [(set (pc) (if_then_else (geu (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jgeu %l0")
-
-(define_insn "ble"
- [(set (pc) (if_then_else (le (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jle %l0")
-
-(define_insn "bleu"
- [(set (pc) (if_then_else (leu (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "jleu %l0")
-\f
-;; reverse-conditional branch instructions
-
-(define_insn ""
- [(set (pc) (if_then_else (eq (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jne %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (ne (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "je %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (gt (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jle %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jleu %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (lt (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jge %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jgeu %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (ge (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jl %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (geu (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jlu %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (le (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jg %l0")
-
-(define_insn ""
- [(set (pc) (if_then_else (leu (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
- "jgu %l0")
-\f
-;; call instructions
-
-(define_insn "call"
- [(call (match_operand:QI 0 "memory_operand" "m")
- (match_operand:SI 1 "immediate_operand" "i"))]
- ""
- "call %1/4, %0")
-
-(define_insn "call_value"
- [(set (match_operand 0 "register_operand" "=r")
- (call (match_operand:QI 1 "memory_operand" "m")
- (match_operand:SI 2 "immediate_operand" "i")))]
- ""
- "call %2/4, %1")
-
-;; No-op instruction
-
-(define_insn "nop"
- [(const_int 0)]
- ""
- "NOP")
-
-;; jump through a dispatch table instruction
-
-(define_expand "casesi"
- [(use (match_operand:SI 0 "general_operand" "mri"))
- (set (cc0) (compare (match_dup 5)
- (match_operand:SI 1 "general_operand" "mri")))
- (set (pc) (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 4 "" ""))
- (pc)))
- (set (match_dup 5) (minus:SI (match_dup 5)
- (match_dup 1)))
- (set (cc0) (compare (match_dup 5)
- (match_operand:SI 2 "general_operand" "mri")))
- (set (pc) (if_then_else (gtu (cc0) (const_int 0))
- (label_ref (match_dup 4))
- (pc)))
- (set (match_dup 5) (ashift:SI (match_dup 5)
- (const_int 2)))
- (set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" ""))
- (match_dup 5))))]
- ""
- "
- {
- operands[5] = gen_reg_rtx(GET_MODE (operands[0]));
- emit_move_insn(operands[5], operands[0]);
- }")
-
-;; jump instructions
-
-(define_insn "indirect_jump"
- [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
- ""
- "jmp %a0")
-
-(define_insn "jump"
- [(set (pc) (label_ref (match_operand 0 "" "")))]
- ""
- "jmp %l0")
@ifhtml
@itemize
@item
-@uref{#1750a-*-*,,1750a-*-*}
-@item
-@uref{#a29k,,a29k}
-@item
-@uref{#a29k-*-bsd,,a29k-*-bsd}
-@item
@uref{#alpha*-*-*,,alpha*-*-*}
@item
@uref{#alpha*-dec-osf*,,alpha*-dec-osf*}
@item
@uref{#arm*-*-linux-gnu,,arm*-*-linux-gnu}
@item
-@uref{#arm-*-riscix,,arm-*-riscix}
-@item
@uref{#avr,,avr}
@item
@uref{#c4x,,c4x}
@item
@uref{#dsp16xx,,dsp16xx}
@item
-@uref{#elxsi-elxsi-bsd,,elxsi-elxsi-bsd}
-@item
@uref{#*-*-freebsd*,,*-*-freebsd*}
@item
@uref{#h8300-hms,,h8300-hms}
@item
@uref{#*-*-linux-gnu,,*-*-linux-gnu}
@item
-@uref{#ix86-*-linux*oldld,,i?86-*-linux*oldld}
-@item
@uref{#ix86-*-linux*aout,,i?86-*-linux*aout}
@item
@uref{#ix86-*-linux*,,i?86-*-linux*}
@item
@uref{#ix86-*-udk,,i?86-*-udk}
@item
-@uref{#ix86-*-isc,,i?86-*-isc}
-@item
@uref{#ix86-*-esix,,i?86-*-esix}
@item
-@uref{#ix86-ibm-aix,,i?86-ibm-aix}
-@item
-@uref{#ix86-sequent-bsd,,i?86-sequent-bsd}
-@item
-@uref{#ix86-sequent-ptx1*,,i?86-sequent-ptx1*, i?86-sequent-ptx2*, i?86-sequent-sysv3*}
-@item
-@uref{#i860-intel-osf*,,i860-intel-osf*}
-@item
@uref{#ia64-*-linux,,ia64-*-linux}
@item
@uref{#*-lynx-lynxos,,*-lynx-lynxos}
@item
@uref{#m6812-elf,,m6812-elf}
@item
-@uref{#m68k-altos,,m68k-altos}
-@item
-@uref{#m68k-apple-aux,,m68k-apple-aux}
-@item
@uref{#m68k-att-sysv,,m68k-att-sysv}
@item
-@uref{#m68k-bull-sysv,,m68k-bull-sysv}
-@item
@uref{#m68k-crds-unos,,m68k-crds-unos}
@item
@uref{#m68k-hp-hpux,,m68k-hp-hpux}
@item
-@uref{#m68k-*-nextstep*,,m68k-*-nextstep*}
-@item
@uref{#m68k-ncr-*,,m68k-ncr-*}
@item
@uref{#m68k-sun,,m68k-sun}
@item
@uref{#m68k-sun-sunos4.1.1,,m68k-sun-sunos4.1.1}
@item
-@uref{#m88k-*-svr3,,m88k-*-svr3}
-@item
-@uref{#m88k-*-dgux,,m88k-*-dgux}
-@item
-@uref{#m88k-tektronix-sysv3,,m88k-tektronix-sysv3}
-@item
@uref{#mips-*-*,,mips-*-*}
@item
-@uref{#mips-dec-*,,mips-dec-*}
-@item
-@uref{#mips-mips-bsd,,mips-mips-bsd}
-@item
-@uref{#mips-mips-riscos*,,mips-mips-riscos*}
-@item
-@uref{#mips-sgi-irix4,,mips-sgi-irix4}
-@item
@uref{#mips-sgi-irix5,,mips-sgi-irix5}
@item
@uref{#mips-sgi-irix6,,mips-sgi-irix6}
@item
-@uref{#mips-sony-sysv,,mips-sony-sysv}
-@item
-@uref{#ns32k-encore,,ns32k-encore}
-@item
-@uref{#ns32k-*-genix,,ns32k-*-genix}
-@item
-@uref{#ns32k-sequent,,ns32k-sequent}
-@item
-@uref{#ns32k-utek,,ns32k-utek}
-@item
@uref{#powerpc*-*-*,,powerpc*-*-*, powerpc-*-sysv4}
@item
@uref{#powerpc-*-darwin*,,powerpc-*-darwin*}
@item
@uref{#powerpcle-*-winnt,,powerpcle-*-winnt, powerpcle-*-pe}
@item
-@uref{#romp-*-aos,,romp-*-aos, romp-*-mach}
-@item
@uref{#s390-*-linux*}
@item
@uref{#s390x-*-linux*}
@item
@uref{#vax-dec-ultrix,,vax-dec-ultrix}
@item
-@uref{#we32k-*-*,,we32k-*-*}
-@item
@uref{#xtensa-*-elf,,xtensa-*-elf}
@item
@uref{#xtensa-*-linux*,,xtensa-*-linux*}
<!-- -------- host/target specific issues start here ---------------- -->
<hr>
@end html
-@heading @anchor{1750a-*-*}1750a-*-*
-MIL-STD-1750A processors. This target is obsoleted in GCC 3.1.
-
-The MIL-STD-1750A cross configuration produces output for
-@code{as1750}, an assembler/linker available under the GNU General Public
-License for the 1750A@. @code{as1750} can be obtained at
-@uref{ftp://ftp.fta-berlin.de/pub/crossgcc/1750gals/}.
-A similarly licensed simulator for
-the 1750A is available from same address.
-
-You should ignore a fatal error during the building of @samp{libgcc}
-(@samp{libgcc} is not yet implemented for the 1750A@.)
-
-The @code{as1750} assembler requires the file @file{ms1750.inc}, which is
-found in the directory @file{gcc/config/1750a}.
-
-GCC produced the same sections as the Fairchild F9450 C Compiler,
-namely:
-
-@table @code
-@item Normal
-The program code section.
-
-@item Static
-The read/write (RAM) data section.
-
-@item Konst
-The read-only (ROM) constants section.
-
-@item Init
-Initialization section (code to copy KREL to SREL)@.
-@end table
-
-The smallest addressable unit is 16 bits (@code{BITS_PER_UNIT} is 16). This
-means that type @code{char} is represented with a 16-bit word per character.
-The 1750A's ``Load/Store Upper/Lower Byte'' instructions are not used by
-GCC@.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{a29k}a29k
-AMD Am29k-family processors. These are normally used in embedded
-applications. This configuration corresponds to AMD's standard calling
-sequence and binary interface and is compatible with other 29k tools.
-
-AMD has abandoned this processor. All existing a29k targets are obsoleted
-in GCC 3.1.
-
-You may need to make a variant of the file @file{a29k.h} for your
-particular configuration.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{a29k-*-bsd}a29k-*-bsd
-AMD Am29050 used in a system running a variant of BSD Unix.
-
-@html
-</p>
-<hr>
-@end html
@heading @anchor{alpha*-*-*}alpha*-*-*
This section contains general configuration information for all
are running the DEC/Compaq Unix (DEC OSF/1, Digital UNIX, or Compaq
Tru64 UNIX) operating system, for example the DEC Alpha AXP systems.
-Support for versions before @code{alpha*-dec-osf4} is obsoleted in GCC
-3.1. (These are the versions which identify themselves as DEC OSF/1.)
+As of GCC 3.2, versions before @code{alpha*-dec-osf4} are no longer
+supported. (These are the versions which identify themselves as DEC
+OSF/1.)
In Tru64 UNIX V5.1, Compaq introduced a new assembler that does not
currently (2001-06-13) work with @command{mips-tfile}. As a workaround,
We require GNU binutils 2.10 or newer.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{arm-*-riscix}arm-*-riscix
-The ARM2 or ARM3 processor running RISC iX, Acorn's port of BSD Unix.
-This configuration is obsoleted in GCC 3.1.
-
-If you are running a version of RISC iX prior to 1.2 then you must
-specify the version number during configuration. Note that the
-assembler shipped with RISC iX does not support stabs debugging
-information; a new version of the assembler, with stabs support
-included, is now available from Acorn and via ftp
-@uref{ftp://ftp.acorn.com/pub/riscix/as+xterm.tar.Z}. To enable stabs
-debugging, pass @option{--with-gnu-as} to configure.
-
-You will need to install GNU @command{sed} before you can run configure.
-
@html
</p>
<hr>
otherwise specified in any per-architecture notes. However, binutils
2.12.1 or greater is known to improve overall testsuite results.
-For FreeBSD 1, FreeBSD 2 or any mutant a.out versions of FreeBSD 3: All
+FreeBSD 1 is no longer supported in GCC 3.2.
+
+For FreeBSD 2 or any mutant a.out versions of FreeBSD 3: All
configuration support and files as shipped with GCC 2.95 are still in
place. FreeBSD 2.2.7 has been known to bootstrap completely; however,
it is unknown which version of binutils was used (it is assumed that it
was the system copy in @file{/usr/bin}) and C++ EH failures were noted.
-Support for FreeBSD 1 is obsoleted in GCC 3.1.
-
For FreeBSD using the ELF file format: DWARF 2 debugging is now the
default for all CPU architectures. It had been the default on
FreeBSD/alpha since its inception. You may use @option{-gstabs} instead
Shared @file{libgcc_s.so} is now built and installed by default.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{elxsi-elxsi-bsd}elxsi-elxsi-bsd
-The Elxsi's C compiler has known limitations that prevent it from
-compiling GCC@. Please contact @email{mrs@@wrs.com} for more details.
-
-Support for this processor is obsoleted in GCC 3.1.
-
@html
</p>
<hr>
glibc 2.2.4 whether patches for GCC 3.0 are needed. You can use glibc
2.2.3 with GCC 3.0, just do not try to recompile it.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ix86-*-linux*oldld}i?86-*-linux*oldld
-Use this configuration to generate @file{a.out} binaries on Linux-based
-GNU systems if you do not have gas/binutils version 2.5.2 or later
-installed.
-
-This configuration is obsoleted in GCC 3.1.
-
@html
</p>
<hr>
have installed.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ix86-*-isc}i?86-*-isc
-This configuration is obsoleted in GCC 3.1.
-
-It may be a good idea to link with GNU malloc instead of the malloc that
-comes with the system.
-
-In ISC version 4.1, @command{sed} core dumps when building
-@file{deduced.h}. Use the version of @command{sed} from version 4.0.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ix86-ibm-aix}i?86-ibm-aix
-This configuration is obsoleted in GCC 3.1.
-
-You need to use GAS version 2.1 or later, and LD from
-GNU binutils version 2.2 or later.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ix86-sequent-bsd}i?86-sequent-bsd
-This configuration is obsoleted in GCC 3.1.
-
-Go to the Berkeley universe before compiling.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ix86-sequent-ptx1*}i?86-sequent-ptx1*, i?86-sequent-ptx2*, i?86-sequent-sysv3*
-This configuration is obsoleted in GCC 3.1.
-
-You must install GNU @command{sed} before running @command{configure}.
-
-The @code{fixproto} shell script may trigger a bug in the system shell.
-If you encounter this problem, upgrade your operating system or
-use @command{bash} (the GNU shell) to run @code{fixproto}.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{i860-intel-osf*}i860-intel-osf*
-All support for the i860 processor is obsoleted in GCC 3.1.
-
-On the Intel Paragon (an i860 machine), if you are using operating
-system version 1.0, you will get warnings or errors about redefinition
-of @code{va_arg} when you build GCC@.
-
-If this happens, then you need to link most programs with the library
-@file{iclib.a}. You must also modify @file{stdio.h} as follows: before
-the lines
-
-@example
-#if defined(__i860__) && !defined(_VA_LIST)
-#include <va_list.h>
-@end example
-
-@noindent
-insert the line
-
-@example
-#if __PGC__
-@end example
-
-@noindent
-and after the lines
-
-@example
-extern int vprintf(const char *, va_list );
-extern int vsprintf(char *, const char *, va_list );
-#endif
-@end example
-
-@noindent
-insert the line
-
-@example
-#endif /* __PGC__ */
-@end example
-
-These problems don't exist in operating system version 1.1.
-
@html
</p>
<hr>
Motorola 68HC12 family micro controllers. These are used in embedded
applications. There are no standard Unix configurations.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{m68k-altos}m68k-altos
-Altos 3068. This configuration is obsoleted in GCC 3.1.
-
-You must use the GNU assembler, linker and debugger.
-Also, you must fix a kernel bug.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{m68k-apple-aux}m68k-apple-aux
-Apple Macintosh running A/UX@.
-This configuration is obsoleted in GCC 3.1.
-
-You may configure GCC to use either the system assembler and
-linker or the GNU assembler and linker. You should use the GNU configuration
-if you can, especially if you also want to use G++. You enable
-that configuration with the @option{--with-gnu-as} and @option{--with-gnu-ld}
-options to @code{configure}.
-
-Note the C compiler that comes
-with this system cannot compile GCC@. You can find binaries of GCC
-for bootstrapping on @code{jagubox.gsfc.nasa.gov}.
-You will also a patched version of @file{/bin/ld} there that
-raises some of the arbitrary limits found in the original.
-
@html
</p>
<hr>
bootstrap. Binaries are available from the OSU-CIS archive, at
@uref{ftp://archive.cis.ohio-state.edu/pub/att7300/}.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{m68k-bull-sysv}m68k-bull-sysv
-Bull DPX/2 series 200 and 300 with BOS-2.00.45 up to BOS-2.01.
-This configuration is obsoleted in GCC 3.1.
-
-GCC works
-either with native assembler or GNU assembler. You can use
-GNU assembler with native COFF generation by providing @option{--with-gnu-as} to
-the configure script or use GNU assembler with stabs-in-COFF encapsulation
-by providing @samp{--with-gnu-as --stabs}. For any problem with the native
-assembler or for availability of the DPX/2 port of GAS, contact
-@email{F.Pierresteguy@@frcl.bull.fr}.
-
@html
</p>
<hr>
@end example
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{m68k-*-nextstep*}m68k-*-nextstep*
-These configurations are obsoleted in GCC 3.1.
-
-Current GCC versions probably do not work on version 2 of the NeXT
-operating system.
-
-On NeXTStep 3.0, the Objective-C compiler does not work, due,
-apparently, to a kernel bug that it happens to trigger. This problem
-does not happen on 3.1.
-
-You absolutely @strong{must} use GNU sed and GNU make on this platform.
-
-
-On NeXTSTEP 3.x where x < 3 the build of GCC will abort during
-stage1 with an error message like this:
-
-@example
- _eh
- /usr/tmp/ccbbsZ0U.s:987:Unknown pseudo-op: .section
- /usr/tmp/ccbbsZ0U.s:987:Rest of line ignored. 1st junk character
- valued 95 (_).
-@end example
-
-The reason for this is the fact that NeXT's assembler for these
-versions of the operating system does not support the @samp{.section}
-pseudo op that's needed for full C++ exception functionality.
-
-As NeXT's assembler is a derived work from GNU as, a free
-replacement that does can be obtained at
-@uref{ftp://ftp.next.peak.org:/next-ftp/next/apps/devtools/as.3.3.NIHS.s.tar.gz,,ftp://ftp.next.peak.org:/next-ftp/next/apps/devtools/as.3.3.NIHS.s.tar.gz}.
-
-If you try to build the integrated C++ & C++ runtime libraries on this system
-you will run into trouble with include files. The way to get around this is
-to use the following sequence. Note you must have write permission to
-the directory @var{prefix} you specified in the configuration process of GCC
-for this sequence to work.
-
-@example
- cd bld-gcc
- make all-texinfo all-bison all-byacc all-binutils all-gas all-ld
- cd gcc
- make bootstrap
- make install-headers-tar
- cd ..
- make bootstrap3
-@end example
-
@html
</p>
<hr>
It is reported that you may need the GNU assembler on this platform.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{m88k-*-svr3}m88k-*-svr3
-Motorola m88k running the AT&T/Unisoft/Motorola V.3 reference port.
-These configurations are obsoleted in GCC 3.1.
-
-These systems tend to use the Green Hills C, revision 1.8.5, as the
-standard C compiler. There are apparently bugs in this compiler that
-result in object files differences between stage 2 and stage 3. If this
-happens, make the stage 4 compiler and compare it to the stage 3
-compiler. If the stage 3 and stage 4 object files are identical, this
-suggests you encountered a problem with the standard C compiler; the
-stage 3 and 4 compilers may be usable.
-
-It is best, however, to use an older version of GCC for bootstrapping
-if you have one.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{m88k-*-dgux}m88k-*-dgux
-Motorola m88k running DG/UX@.
-These configurations are obsoleted in GCC 3.1.
-
-To build 88open BCS native or cross
-compilers on DG/UX, specify the configuration name as
-@samp{m88k-*-dguxbcs} and build in the 88open BCS software development
-environment. To build ELF native or cross compilers on DG/UX, specify
-@samp{m88k-*-dgux} and build in the DG/UX ELF development environment.
-You set the software development environment by issuing
-@samp{sde-target} command and specifying either @samp{m88kbcs} or
-@samp{m88kdguxelf} as the operand.
-
-If you do not specify a configuration name, @file{configure} guesses the
-configuration based on the current software development environment.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{m88k-tektronix-sysv3}m88k-tektronix-sysv3
-Tektronix XD88 running UTekV 3.2e.
-These configurations are obsoleted in GCC 3.1.
-
-Do not turn on
-optimization while building stage1 if you bootstrap with
-the buggy Green Hills compiler. Also, the bundled LAI
-System V NFS is buggy so if you build in an NFS mounted
-directory, start from a fresh reboot, or avoid NFS all together.
-Otherwise you may have trouble getting clean comparisons
-between stages.
-
@html
</p>
<hr>
@end html
@heading @anchor{mips-*-*}mips-*-*
-If you use the 1.31 version of the MIPS assembler (such as was shipped
-with Ultrix 3.1), you will need to use the @option{-fno-delayed-branch} switch
-when optimizing floating point code. Otherwise, the assembler will
-complain when the GCC compiler fills a branch delay slot with a
-floating point instruction, such as @code{add.d}.
-
If on a MIPS system you get an error message saying ``does not have gp
sections for all it's [sic] sectons [sic]'', don't worry about it. This
happens whenever you use GAS with the MIPS linker, but there is not
It would be nice to extend GAS to produce the gp tables, but they are
optional, and there should not be a warning about their absence.
-Users have reported some problems with version 2.0 of the MIPS
-compiler tools that were shipped with Ultrix 4.1. Version 2.10
-which came with Ultrix 4.2 seems to work fine.
-
-Users have also reported some problems with version 2.20 of the
-MIPS compiler tools that were shipped with RISC/os 4.x. The earlier
-version 2.11 seems to work fine.
-
-Some versions of the MIPS linker will issue an assertion failure
-when linking code that uses @code{alloca} against shared
-libraries on RISC-OS 5.0, and DEC's OSF/1 systems. This is a bug
-in the linker, that is supposed to be fixed in future revisions.
-To protect against this, GCC passes @option{-non_shared} to the
-linker unless you pass an explicit @option{-shared} or
-@option{-call_shared} switch.
-
-@heading @anchor{mips-mips-bsd}mips-mips-bsd
-MIPS machines running the MIPS operating system in BSD mode.
-These configurations are obsoleted in GCC 3.1.
-
-It's possible that some old versions of the system lack the functions
-@code{memcpy}, @code{memmove}, @code{memcmp}, and @code{memset}. If your
-system lacks these, you must remove or undo the definition of
-@code{TARGET_MEM_FUNCTIONS} in @file{mips-bsd.h}.
-
-If you use the MIPS C compiler to bootstrap, it may be necessary
-to increase its table size for switch statements with the
-@option{-Wf,-XNg1500} option. If you use the @option{-O2}
-optimization option, you also need to use @option{-Olimit 3000}.
-Both of these options are automatically generated in the
-@file{Makefile} that the shell script @file{configure} builds.
-If you override the @code{CC} make variable and use the MIPS
-compilers, you may need to add @option{-Wf,-XNg1500 -Olimit 3000}.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{mips-dec-*}mips-dec-*
-These configurations are obsoleted in GCC 3.1.
-
-MIPS-based DECstations can support three different personalities:
-Ultrix, DEC OSF/1, and OSF/rose. (Alpha-based DECstation products have
-a configuration name beginning with @samp{alpha*-dec}.) To configure GCC
-for these platforms use the following configurations:
-
-@table @samp
-@item mips-dec-ultrix
-Ultrix configuration.
-
-@item mips-dec-osf1
-DEC's version of OSF/1.
-
-@item mips-dec-osfrose
-Open Software Foundation reference port of OSF/1 which uses the
-OSF/rose object file format instead of ECOFF@. Normally, you
-would not select this configuration.
-@end table
-
-If you use the MIPS C compiler to bootstrap, it may be necessary
-to increase its table size for switch statements with the
-@option{-Wf,-XNg1500} option. If you use the @option{-O2}
-optimization option, you also need to use @option{-Olimit 3000}.
-Both of these options are automatically generated in the
-@file{Makefile} that the shell script @file{configure} builds.
-If you override the @code{CC} make variable and use the MIPS
-compilers, you may need to add @option{-Wf,-XNg1500 -Olimit 3000}.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{mips-mips-riscos*}mips-mips-riscos*
-These configurations are obsoleted in GCC 3.1.
-
-If you use the MIPS C compiler to bootstrap, it may be necessary
-to increase its table size for switch statements with the
-@option{-Wf,-XNg1500} option. If you use the @option{-O2}
-optimization option, you also need to use @option{-Olimit 3000}.
-Both of these options are automatically generated in the
-@file{Makefile} that the shell script @file{configure} builds.
-If you override the @code{CC} make variable and use the MIPS
-compilers, you may need to add @samp{-Wf,-XNg1500 -Olimit 3000}.
-
-MIPS computers running RISC-OS can support four different
-personalities: default, BSD 4.3, System V.3, and System V.4
-(older versions of RISC-OS don't support V.4). To configure GCC
-for these platforms use the following configurations:
-
-@table @samp
-@item mips-mips-riscos@var{rev}
-Default configuration for RISC-OS, revision @var{rev}.
-
-@item mips-mips-riscos@var{rev}bsd
-BSD 4.3 configuration for RISC-OS, revision @var{rev}.
-
-@item mips-mips-riscos@var{rev}sysv4
-System V.4 configuration for RISC-OS, revision @var{rev}.
-
-@html
-</p>
-<hr>
-@end html
-@item mips-mips-riscos@var{rev}sysv
-System V.3 configuration for RISC-OS, revision @var{rev}.
-@end table
-
-The revision @code{rev} mentioned above is the revision of
-RISC-OS to use. You must reconfigure GCC when going from a
-RISC-OS revision 4 to RISC-OS revision 5. This has the effect of
-avoiding a linker bug.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{mips-sgi-irix4}mips-sgi-irix4
-This configuration is obsoleted in GCC 3.1.
-
-In order to compile GCC on an SGI running IRIX 4, the ``c.hdr.lib''
-option must be installed from the CD-ROM supplied from Silicon Graphics.
-This is found on the 2nd CD in release 4.0.1.
-
-On IRIX version 4.0.5F, and perhaps on some other versions as well,
-there is an assembler bug that reorders instructions incorrectly. To
-work around it, specify the target configuration
-@samp{mips-sgi-irix4loser}. This configuration inhibits assembler
-optimization.
-
-In a compiler configured with target @samp{mips-sgi-irix4}, you can turn
-off assembler optimization by using the @option{-noasmopt} option. This
-compiler option passes the option @option{-O0} to the assembler, to
-inhibit reordering.
-
-The @option{-noasmopt} option can be useful for testing whether a problem
-is due to erroneous assembler reordering. Even if a problem does not go
-away with @option{-noasmopt}, it may still be due to assembler
-reordering---perhaps GCC itself was miscompiled as a result.
-
-You may get the following warning on IRIX 4 platforms, it can be safely
-ignored.
-@example
- warning: foo.o does not have gp tables for all its sections.
-@end example
-
-@html
-</p>
-<hr>
-@end html
@heading @anchor{mips-sgi-irix5}mips-sgi-irix5
This configuration has considerable problems, which will be fixed in a
See @uref{http://freeware.sgi.com/,,http://freeware.sgi.com/} for more
information about using GCC on IRIX platforms.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{mips-sony-sysv}mips-sony-sysv
-Sony MIPS NEWS@. This configuration is obsoleted in GCC 3.1.
-
-This works in NEWSOS 5.0.1, but not in 5.0.2 (which uses ELF instead of
-COFF)@. In particular, the linker does not like the code generated by
-GCC when shared libraries are linked in.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ns32k-encore}ns32k-encore
-This configuration is obsoleted in GCC 3.1.
-
-Encore ns32000 system. Encore systems are supported only under BSD@.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ns32k-*-genix}ns32k-*-genix
-National Semiconductor ns32000 system. This configuration is obsoleted
-in GCC 3.1.
-
-Genix has bugs in @code{alloca} and @code{malloc}; you must get the
-compiled versions of these from GNU Emacs.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ns32k-sequent}ns32k-sequent
-This configuration is obsoleted in GCC 3.1.
-
-Go to the Berkeley universe before compiling.
-
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{ns32k-utek}ns32k-utek
-UTEK ns32000 system (``merlin''). This configuration is obsoleted in
-GCC 3.1.
-
-The C compiler that comes with this system cannot compile GCC; contact
-@samp{tektronix!reed!mason} to get binaries of GCC for bootstrapping.
-
-
@html
</p>
<hr>
@heading @anchor{powerpcle-*-winnt}powerpcle-*-winnt, powerpcle-*-pe
PowerPC system in little endian mode running Windows NT@.
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{romp-*-aos}romp-*-aos, romp-*-mach
-These configurations are obsoleted in GCC 3.1.
-
-We recommend you compile GCC with an earlier version of itself; if you
-compile GCC with @command{hc}, the Metaware compiler, it will work, but
-you will get mismatches between the stage 2 and stage 3 compilers in
-various files. These errors are minor differences in some
-floating-point constants and can be safely ignored; the stage 3 compiler
-is correct.
-
@html
</p>
<hr>
Don't try compiling with VAX C (@code{vcc}). It produces incorrect code
in some cases (for example, when @code{alloca} is used).
-@html
-</p>
-<hr>
-@end html
-@heading @anchor{we32k-*-*}we32k-*-*
-These computers are also known as the 3b2, 3b5, 3b20 and other similar
-names. (However, the 3b1 is actually a 68000.)
-These configurations are obsoleted in GCC 3.1.
-
-Don't use @option{-g} when compiling with the system's compiler. The
-system's linker seems to be unable to handle such a large program with
-debugging information.
-
-The system's compiler runs out of capacity when compiling @file{stmt.c}
-in GCC@. You can work around this by building @file{cpp} in GCC
-first, then use that instead of the system's preprocessor with the
-system's C compiler to compile @file{stmt.c}. Here is how:
-
-@smallexample
-mv /lib/cpp /lib/cpp.att
-cp cpp /lib/cpp.gnu
-echo '/lib/cpp.gnu -traditional $@{1+"$@@"@}' > /lib/cpp
-chmod +x /lib/cpp
-@end smallexample
-
-The system's compiler produces bad code for some of the GCC
-optimization files. So you must build the stage 2 compiler without
-optimization. Then build a stage 3 compiler with optimization.
-That executable should work. Here are the necessary commands:
-
-@smallexample
-make LANGUAGES=c CC=stage1/xgcc CFLAGS="-Bstage1/ -g"
-make stage2
-make CC=stage2/xgcc CFLAGS="-Bstage2/ -g -O"
-@end smallexample
-
-You may need to raise the ULIMIT setting to build a C++ compiler,
-as the file @file{cc1plus} is larger than one megabyte.
-
@html
</p>
<hr>
GCC contains support files for many older (1980s and early
1990s) Unix variants. For the most part, support for these systems
has not been deliberately removed, but it has not been maintained for
-several years and may suffer from bitrot. Support from some systems
-has been removed from GCC 3: fx80, ns32-ns-genix, pyramid, tahoe,
-gmicro, spur; most of these targets had not been updated since GCC
-version 1.
+several years and may suffer from bitrot.
-We are planning to remove support for more older systems, starting in
-GCC 3.1. Each release will have a list of ``obsoleted'' systems.
+Starting with GCC 3.1, each release has a list of ``obsoleted'' systems.
Support for these systems is still present in that release, but
@command{configure} will fail unless the @option{--enable-obsolete}
-option is given. Unless a maintainer steps forward, support for
-these systems will be removed from the next release of GCC@.
-
-Support for older systems as targets for cross-compilation is less
-problematic than support for them as hosts for GCC; if an enthusiast
-wishes to make such a target work again (including resurrecting any
-of the targets that never worked with GCC 2, starting from the last
-CVS version before they were removed), patches
-@uref{../contribute.html,,following the usual requirements}
-would be likely to be accepted, since they should not affect the
-support for more modern targets.
+option is given. Unless a maintainer steps forward, support for these
+systems will be removed from the next release of GCC@.
Support for old systems as hosts for GCC can cause problems if the
workarounds for compiler, library and operating system bugs affect the
cleanliness or maintainability of the rest of GCC@. In some cases, to
bring GCC up on such a system, if still possible with current GCC, may
require first installing an old version of GCC which did work on that
-system, and using it to compile a more recent GCC, to avoid bugs in
-the vendor compiler. Old releases of GCC 1 and GCC 2 are available in
-the @file{old-releases} directory on the
-@uref{../mirrors.html,,GCC mirror sites}. Header bugs may generally
-be avoided using @command{fixincludes}, but bugs or deficiencies in
-libraries and the operating system may still cause problems.
+system, and using it to compile a more recent GCC, to avoid bugs in the
+vendor compiler. Old releases of GCC 1 and GCC 2 are available in the
+@file{old-releases} directory on the @uref{../mirrors.html,,GCC mirror
+sites}. Header bugs may generally be avoided using
+@command{fixincludes}, but bugs or deficiencies in libraries and the
+operating system may still cause problems.
+
+Support for older systems as targets for cross-compilation is less
+problematic than support for them as hosts for GCC; if an enthusiast
+wishes to make such a target work again (including resurrecting any of
+the targets that never worked with GCC 2, starting from the last CVS
+version before they were removed), patches
+@uref{../contribute.html,,following the usual requirements} would be
+likely to be accepted, since they should not affect the support for more
+modern targets.
For some systems, old versions of GNU binutils may also be useful,
and are available from @file{pub/binutils/old-releases} on
armel-semi-aout | \
arm-semi-aof | \
armel-semi-aof | \
- c*-convex-* | \
hppa1.1-*-osf* | \
hppa1.0-*-osf* | \
hppa1.1-*-bsd* | \
i?86-*-cygwin* | \
i?86-*-mingw32* | \
i?86-*-uwin* | \
- mips-sgi-irix5cross64 | \
powerpc-*-eabiaix* | \
powerpc-*-eabisim* | \
powerpc-*-eabi* | \
projects / thirdparty / gcc.git / commitdiff
