drm/amd/display: Ensure correct GFX tiling info passed to DML

[Why]
To ensure DML validation receives the correct tiling information,
such as swizzle mode or array mode, based on the active GFX format

[How]
- For new GFX format passed swizzle_mode to DML.
- For legacy GFX format passed array_mode to DML.
- Dynamically determined the appropriate tiling info based on the
  active GFX format.

[Description]
This commit ensures that the correct GFX tiling information is passed
to DML. Depending on the active GFX format, the appropriate tiling info
is passed to DML. This change accommodates the different GFX formats
supported by latest platforms, ensuring compatibility and proper
DML validation.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index db8c55cc865e51b88751de246ce5dff9cd7762be..774cc3f4f3fd9a964fe48c66eb596d2f6dfee602 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -190,6 +190,7 @@ static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_in
                tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
                num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
 
+               tiling_info->gfxversion = DcGfxVersion8;
                /* XXX fix me for VI */
                tiling_info->gfx8.num_banks = num_banks;
                tiling_info->gfx8.array_mode =
@@ -317,6 +318,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg
 
        amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
        tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);
+       tiling_info->gfxversion = DcGfxVersion9;
 
        if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {
                uint64_t dcc_address = afb->address + afb->base.offsets[1];
@@ -369,6 +371,7 @@ static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amd
        amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);
 
        tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);
+       tiling_info->gfxversion = DcGfxAddr3;
 
        if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {
                int max_compressed_block = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index efb09990549658fa16d302d32cc9d740f52fdb27..47a8c770794b85ec4f2590a143141a93e5579eb5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -721,11 +721,21 @@ static void populate_dml21_surface_config_from_plane_state(
        surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_blks_c;
        surface->dcc.plane0.pitch = plane_state->dcc.meta_pitch;
        surface->dcc.plane1.pitch = plane_state->dcc.meta_pitch_c;
-       if (in_dc->ctx->dce_version < DCN_VERSION_4_01) {
-               /* needed for N-1 testing */
+
+       // Update swizzle / array mode based on the gfx_format
+       switch (plane_state->tiling_info.gfxversion) {
+       case DcGfxVersion7:
+       case DcGfxVersion8:
+               // Placeholder for programming the array_mode
+               break;
+       case DcGfxVersion9:
+       case DcGfxVersion10:
+       case DcGfxVersion11:
                surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle);
-       } else {
+               break;
+       case DcGfxAddr3:
                surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle);
+               break;
        }
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 89e2adcf2a28580fd212e200b5b38454b79dc2e8..b878b60feff9432c58a7b08e91b2831b9f67cdaa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -1752,6 +1752,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc,
        return out;
 }
 
+enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)
+{
+       plane_state->tiling_info.gfxversion = DcGfxVersion9;
+       dcn20_patch_unknown_plane_state(plane_state);
+       return DC_OK;
+}
+
 
 static struct resource_funcs dcn35_res_pool_funcs = {
        .destroy = dcn35_destroy_resource_pool,
@@ -1775,7 +1782,7 @@ static struct resource_funcs dcn35_res_pool_funcs = {
        .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
-       .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+       .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
        .get_panel_config_defaults = dcn35_get_panel_config_defaults,
        .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
        .get_det_buffer_size = dcn31_get_det_buffer_size,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
index f97bb4cb3761f46e0ed8447cabd24a0bb0df76a5..9d03a55d90cf0341d39fa1460350df7008655eee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
@@ -35,6 +35,7 @@
 
 extern struct _vcs_dpi_ip_params_st dcn3_5_ip;
 extern struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc;
+enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state);
 
 struct dcn35_resource_pool {
        struct resource_pool base;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 263a37c1cd3ae8c649a4b6807c04b8eb40a1fe61..16abd3ae868405d2616373d3d1ff77d9daa7e8b3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1754,7 +1754,7 @@ static struct resource_funcs dcn351_res_pool_funcs = {
        .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,
-       .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+       .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
        .get_panel_config_defaults = dcn35_get_panel_config_defaults,
        .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
        .get_det_buffer_size = dcn31_get_det_buffer_size,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 09f5b8b40791e50b42db0d4621c73e82d5679ac4..d75f8da63e10f772b2500d962a3fa617f7df5bbd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1609,6 +1609,7 @@ static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
 
 enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
 {
+       plane_state->tiling_info.gfxversion = DcGfxAddr3;
        plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;
        return DC_OK;
 }