mmc: sdhci-of-dwcmshc: Disable internal clock auto gate for Rockchip SOCs

Enabling CMDQ support can lead to random occurrences of the error log when
there are RPMB access and data flush executed:

"mmc2: Timeout waiting for hardware interrupt."

Enabling CMDQ and then issuing a DCMD as the final command before disabling
it causes the eMMC controller to auto-gate its internal clock. Chip simulation
shows this results in a state machine mismatch after CMDQ mode exit, triggering
data-timeout errors for all subsequent read and write operations.

Therefore, the auto-clock-gate function must be disabled whenever CMDQ is
enabled.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: fda1e0af7c28 ("mmc: sdhci-of-dwcmshc: Add command queue support for rockchip SOCs")
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 498997c8648f5a18060da4a4e2ebde38c5ff45f3..36e7c0bec43151a75eb5ad3af44d9a1660791288 100644 (file)
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -726,10 +726,11 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
 
        sdhci_set_clock(host, clock);
 
-       /* Disable cmd conflict check */
+       /* Disable cmd conflict check and internal clock gate */
        reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
        extra = sdhci_readl(host, reg);
        extra &= ~BIT(0);
+       extra |= BIT(4);
        sdhci_writel(host, extra, reg);
 
        if (clock <= 52000000) {