return offsetof(CPUPPCState, vsr[i].u64[1]);
}
+static inline int vsr_full_offset(int i)
+{
+ return offsetof(CPUPPCState, vsr[i].u64[0]);
+}
+
static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
{
return (uint64_t *)((uintptr_t)env + vsrl_offset(i));
}
+static inline int avr_full_offset(int i)
+{
+ return vsr_full_offset(i + 32);
+}
+
static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
{
- return &env->vsr[32 + i];
+ return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
}
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
static inline TCGv_ptr gen_avr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0]));
+ tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
return r;
}
}
val = tcg_temp_new_i32();
- bofs = avr64_offset(rB(ctx->opcode), true);
+ bofs = avr_full_offset(rB(ctx->opcode));
#ifdef HOST_WORDS_BIGENDIAN
bofs += 3 * 4;
#endif
} \
\
tcg_op(vece, \
- avr64_offset(rD(ctx->opcode), true), \
- avr64_offset(rA(ctx->opcode), true), \
- avr64_offset(rB(ctx->opcode), true), \
+ avr_full_offset(rD(ctx->opcode)), \
+ avr_full_offset(rA(ctx->opcode)), \
+ avr_full_offset(rB(ctx->opcode)), \
16, 16); \
}
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
- tcg_gen_gvec_4(avr64_offset(rD(ctx->opcode), true), \
+ tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
offsetof(CPUPPCState, vscr_sat), \
- avr64_offset(rA(ctx->opcode), true), \
- avr64_offset(rB(ctx->opcode), true), \
+ avr_full_offset(rA(ctx->opcode)), \
+ avr_full_offset(rB(ctx->opcode)), \
16, 16, &g); \
}
return; \
} \
simm = SIMM5(ctx->opcode); \
- tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \
+ tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
}
GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
}
uimm = UIMM5(ctx->opcode);
- bofs = avr64_offset(rB(ctx->opcode), true);
- dofs = avr64_offset(rD(ctx->opcode), true);
+ bofs = avr_full_offset(rB(ctx->opcode));
+ dofs = avr_full_offset(rD(ctx->opcode));
/* Experimental testing shows that hardware masks the immediate. */
bofs += (uimm << vece) & 15;