arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs

Arm heterogeneous configurations should have separate PMU nodes for each
CPU uarch as the uarch specific events can be different. The
"arm,armv8-pmuv3" compatible is also intended for s/w models rather than
specific uarch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't be fixed.

Signed-off-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20240417204247.3216703-1-robh@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi
index 668e05185c21ee59f6040ce661d2fef2cccd5004..fa36b62156bb79d818678d5f22b110f9470970a9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8956.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi
@@ -8,8 +8,8 @@
 
 #include "msm8976.dtsi"
 
-&pmu {
-       interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+&pmu_a72 {
+       interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>;
 };
 
 &tsens {

diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 1b158608c49d8b6efdbc42cb0ba37b5f49666ba4..861c24cc255688a532797e40bc6ec0e6bd9d4641 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -222,11 +222,17 @@
                reg = <0x0 0x80000000 0x0 0x0>;
        };
 
-       pmu: pmu {
-               compatible = "arm,armv8-pmuv3";
-               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+       pmu-a53 {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
+       pmu_a72: pmu-a72 {
+               compatible = "arm,cortex-a72-pmu";
+               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";

diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 8d75c4f9731ccafccb6f0b906af5da44491312ad..9c9919e78fbdbf4dab77e0bd5b611804de178439 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -292,9 +292,14 @@
                reg = <0x0 0xa0000000 0x0 0x0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+       pmu-a55 {
+               compatible = "arm,cortex-a55-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a78 {
+               compatible = "arm,cortex-a78-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
        psci {

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 708107da0ab0f21903da9f7d7c966bf043a0c587..e01b4d4c07f1f2f61e7157c4296ef48d9dd2f7e3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -301,8 +301,18 @@
                reg = <0x0 0x80000000 0x0 0x0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu-a55 {
+               compatible = "arm,cortex-a55-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a78 {
+               compatible = "arm,cortex-a78-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-x1 {
+               compatible = "arm,cortex-x1-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 79311a6bd1ad6e691bcaa0757b4993f1b8952991..9564963fbabf5589d4f3042449d03526c1d58093 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -352,8 +352,23 @@
                reg = <0 0xa0000000 0 0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu-a510 {
+               compatible = "arm,cortex-a510-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a710 {
+               compatible = "arm,cortex-a710-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a715 {
+               compatible = "arm,cortex-a715-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-x3 {
+               compatible = "arm,cortex-x3-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 1774be6c53e5c4b6dd7c346914298ddbc3390dfc..336c54242778b24020d9632fdd48af8e9a9bee0f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -390,8 +390,18 @@
                reg = <0 0xa0000000 0 0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu-a520 {
+               compatible = "arm,cortex-a520-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a720 {
+               compatible = "arm,cortex-a720-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-x4 {
+               compatible = "arm,cortex-x4-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };