--- /dev/null
+From b8c5d882c8334d05754b69dcdf1cfd6bc48a9e12 Mon Sep 17 00:00:00 2001
+From: Pascal van Leeuwen <pascalvanl@gmail.com>
+Date: Tue, 17 Sep 2019 11:55:18 +0200
+Subject: crypto: inside-secure - Fix stability issue with Macchiatobin
+
+From: Pascal van Leeuwen <pascalvanl@gmail.com>
+
+commit b8c5d882c8334d05754b69dcdf1cfd6bc48a9e12 upstream.
+
+This patch corrects an error in the Transform Record Cache initialization
+code that was causing intermittent stability problems on the Macchiatobin
+board.
+
+Unfortunately, due to HW platform specifics, the problem could not happen
+on the main development platform, being the VCU118 Xilinx development
+board. And since it was a problem with hash table access, it was very
+dependent on the actual physical context record DMA buffers being used,
+i.e. with some (bad) luck it could seemingly work quit stable for a while.
+
+Signed-off-by: Pascal van Leeuwen <pvanleeuwen@verimatrix.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/crypto/inside-secure/safexcel.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/crypto/inside-secure/safexcel.c
++++ b/drivers/crypto/inside-secure/safexcel.c
+@@ -221,9 +221,9 @@ static void eip197_trc_cache_init(struct
+ /* Step #3: Determine log2 of hash table size */
+ cs_ht_sz = __fls(asize - cs_rc_max) - 2;
+ /* Step #4: determine current size of hash table in dwords */
+- cs_ht_wc = 16<<cs_ht_sz; /* dwords, not admin words */
++ cs_ht_wc = 16 << cs_ht_sz; /* dwords, not admin words */
+ /* Step #5: add back excess words and see if we can fit more records */
+- cs_rc_max = min_t(uint, cs_rc_abs_max, asize - (cs_ht_wc >> 4));
++ cs_rc_max = min_t(uint, cs_rc_abs_max, asize - (cs_ht_wc >> 2));
+
+ /* Clear the cache RAMs */
+ eip197_trc_cache_clear(priv, cs_rc_max, cs_ht_wc);