--- /dev/null
+From faefd550c45d8d314e8f260f21565320355c947f Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Date: Wed, 15 May 2013 09:39:17 +0100
+Subject: ARM: 7722/1: zImage: Convert 32bits memory size and address from ATAG to 64bits DTB
+
+From: Gregory CLEMENT <gregory.clement@free-electrons.com>
+
+commit faefd550c45d8d314e8f260f21565320355c947f upstream.
+
+When CONFIG_ARM_APPENDED_DTB is selected, if the bootloader provides
+an ATAG_MEM it replaces the memory size and the memory address in the
+memory node of the device tree. In the case of a system which can
+handle more than 4GB, the memory node cell size is 4: each data
+(memory size and memory address) are 64 bits and then use 2 cells.
+
+The current code in atags_to_fdt.c made the assumption of a cell size
+of 2 (one cell for the memory size and one cell for the memory
+address), this leads to an improper write of the data and ends with a
+boot hang.
+
+This patch writes the memory size and the memory address on the memory
+node in the device tree depending of the size of the memory node (32
+bits or 64 bits).
+
+It has been tested in the 2 cases:
+- with a dtb using skeleton.dtsi
+- and with a dtb using skeleton64.dtsi
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Acked-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Cc: Willy Tarreau <w@1wt.eu>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/compressed/atags_to_fdt.c | 44 +++++++++++++++++++++++++++-----
+ 1 file changed, 38 insertions(+), 6 deletions(-)
+
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -53,6 +53,17 @@ static const void *getprop(const void *f
+ return fdt_getprop(fdt, offset, property, len);
+ }
+
++static uint32_t get_cell_size(const void *fdt)
++{
++ int len;
++ uint32_t cell_size = 1;
++ const uint32_t *size_len = getprop(fdt, "/", "#size-cells", &len);
++
++ if (size_len)
++ cell_size = fdt32_to_cpu(*size_len);
++ return cell_size;
++}
++
+ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+ {
+ char cmdline[COMMAND_LINE_SIZE];
+@@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt
+ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
+ {
+ struct tag *atag = atag_list;
+- uint32_t mem_reg_property[2 * NR_BANKS];
++ /* In the case of 64 bits memory size, need to reserve 2 cells for
++ * address and size for each bank */
++ uint32_t mem_reg_property[2 * 2 * NR_BANKS];
+ int memcount = 0;
+- int ret;
++ int ret, memsize;
+
+ /* make sure we've got an aligned pointer */
+ if ((u32)atag_list & 0x3)
+@@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *
+ continue;
+ if (!atag->u.mem.size)
+ continue;
+- mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
+- mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
++ memsize = get_cell_size(fdt);
++
++ if (memsize == 2) {
++ /* if memsize is 2, that means that
++ * each data needs 2 cells of 32 bits,
++ * so the data are 64 bits */
++ uint64_t *mem_reg_prop64 =
++ (uint64_t *)mem_reg_property;
++ mem_reg_prop64[memcount++] =
++ cpu_to_fdt64(atag->u.mem.start);
++ mem_reg_prop64[memcount++] =
++ cpu_to_fdt64(atag->u.mem.size);
++ } else {
++ mem_reg_property[memcount++] =
++ cpu_to_fdt32(atag->u.mem.start);
++ mem_reg_property[memcount++] =
++ cpu_to_fdt32(atag->u.mem.size);
++ }
++
+ } else if (atag->hdr.tag == ATAG_INITRD2) {
+ uint32_t initrd_start, initrd_size;
+ initrd_start = atag->u.initrd.start;
+@@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *
+ }
+ }
+
+- if (memcount)
+- setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
++ if (memcount) {
++ setprop(fdt, "/memory", "reg", mem_reg_property,
++ 4 * memcount * memsize);
++ }
+
+ return fdt_pack(fdt);
+ }
--- /dev/null
+From cb6f66a2d278e57a6c9d8fb59bd9ebd8ab3965c2 Mon Sep 17 00:00:00 2001
+From: Chih-Chung Chang <chihchung@chromium.org>
+Date: Mon, 15 Jul 2013 09:38:46 -0700
+Subject: ASoC: max98088 - fix element type of the register cache.
+
+From: Chih-Chung Chang <chihchung@chromium.org>
+
+commit cb6f66a2d278e57a6c9d8fb59bd9ebd8ab3965c2 upstream.
+
+The registers of max98088 are 8 bits, not 16 bits. This bug causes the
+contents of registers to be overwritten with bad values when the codec
+is suspended and then resumed.
+
+Signed-off-by: Chih-Chung Chang <chihchung@chromium.org>
+Signed-off-by: Dylan Reid <dgreid@chromium.org>
+Signed-off-by: Mark Brown <broonie@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/soc/codecs/max98088.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/sound/soc/codecs/max98088.c
++++ b/sound/soc/codecs/max98088.c
+@@ -1612,7 +1612,7 @@ static int max98088_dai2_digital_mute(st
+
+ static void max98088_sync_cache(struct snd_soc_codec *codec)
+ {
+- u16 *reg_cache = codec->reg_cache;
++ u8 *reg_cache = codec->reg_cache;
+ int i;
+
+ if (!codec->cache_sync)
--- /dev/null
+From 016fcab8ff46fca29375d484226ec91932aa4a07 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Thu, 4 Jul 2013 20:01:02 -0300
+Subject: ASoC: sglt5000: Fix the default value of CHIP_SSS_CTRL
+
+From: Fabio Estevam <fabio.estevam@freescale.com>
+
+commit 016fcab8ff46fca29375d484226ec91932aa4a07 upstream.
+
+According to the sgtl5000 reference manual, the default value of CHIP_SSS_CTRL
+is 0x10.
+
+Reported-by: Oskar Schirmer <oskar@scara.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Signed-off-by: Mark Brown <broonie@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/soc/codecs/sgtl5000.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/sound/soc/codecs/sgtl5000.c
++++ b/sound/soc/codecs/sgtl5000.c
+@@ -37,7 +37,7 @@
+ static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
+ [SGTL5000_CHIP_CLK_CTRL] = 0x0008,
+ [SGTL5000_CHIP_I2S_CTRL] = 0x0010,
+- [SGTL5000_CHIP_SSS_CTRL] = 0x0008,
++ [SGTL5000_CHIP_SSS_CTRL] = 0x0010,
+ [SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
+ [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
+ [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
--- /dev/null
+From 647ab784c507763bfda79155f125b6edd1244806 Mon Sep 17 00:00:00 2001
+From: Richard Zhao <rizhao@nvidia.com>
+Date: Sun, 21 Jul 2013 10:34:09 +0800
+Subject: ASoC: tegra: correct playback_dma_data setup
+
+From: Richard Zhao <rizhao@nvidia.com>
+
+commit 647ab784c507763bfda79155f125b6edd1244806 upstream.
+
+The errors were caused by copy/paste mistake in below commit
+since v3.10:
+3489d50 ASoC: tegra: Use common DAI DMA data struct
+
+It also corrects slave_id initialization in tegra20_ac97 driver.
+
+Signed-off-by: Richard Zhao <rizhao@nvidia.com>
+Acked-by: Stephen Warren <swarren@nvidia.com>
+Acked-by: Lucas Stach <dev@lynxeye.de>
+Signed-off-by: Mark Brown <broonie@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/soc/tegra/tegra20_ac97.c | 6 +++---
+ sound/soc/tegra/tegra20_spdif.c | 4 ++--
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/sound/soc/tegra/tegra20_ac97.c
++++ b/sound/soc/tegra/tegra20_ac97.c
+@@ -399,9 +399,9 @@ static int tegra20_ac97_platform_probe(s
+ ac97->capture_dma_data.slave_id = of_dma[1];
+
+ ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
+- ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+- ac97->capture_dma_data.maxburst = 4;
+- ac97->capture_dma_data.slave_id = of_dma[0];
++ ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ ac97->playback_dma_data.maxburst = 4;
++ ac97->playback_dma_data.slave_id = of_dma[1];
+
+ ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
+ &tegra20_ac97_dai, 1);
+--- a/sound/soc/tegra/tegra20_spdif.c
++++ b/sound/soc/tegra/tegra20_spdif.c
+@@ -323,8 +323,8 @@ static int tegra20_spdif_platform_probe(
+ }
+
+ spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
+- spdif->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+- spdif->capture_dma_data.maxburst = 4;
++ spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ spdif->playback_dma_data.maxburst = 4;
+ spdif->playback_dma_data.slave_id = dmareq->start;
+
+ pm_runtime_enable(&pdev->dev);
--- /dev/null
+From 2e7ee15ced914e109a1a5b6dfcd463d846a13bd5 Mon Sep 17 00:00:00 2001
+From: Nicolin Chen <b42378@freescale.com>
+Date: Fri, 14 Jun 2013 12:34:50 +0800
+Subject: ASoC: wm8962: Remove remaining direct register cache accesses
+
+From: Nicolin Chen <b42378@freescale.com>
+
+commit 2e7ee15ced914e109a1a5b6dfcd463d846a13bd5 upstream.
+
+Also fix return values for headphone switch updates.
+
+Signed-off-by: Nicolin Chen <b42378@freescale.com>
+Signed-off-by: Mark Brown <broonie@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/soc/codecs/wm8962.c | 24 +++++++++++++-----------
+ 1 file changed, 13 insertions(+), 11 deletions(-)
+
+--- a/sound/soc/codecs/wm8962.c
++++ b/sound/soc/codecs/wm8962.c
+@@ -1600,7 +1600,6 @@ static int wm8962_put_hp_sw(struct snd_k
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+- u16 *reg_cache = codec->reg_cache;
+ int ret;
+
+ /* Apply the update (if any) */
+@@ -1609,16 +1608,19 @@ static int wm8962_put_hp_sw(struct snd_k
+ return 0;
+
+ /* If the left PGA is enabled hit that VU bit... */
+- if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
+- return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
+- reg_cache[WM8962_HPOUTL_VOLUME]);
++ ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
++ if (ret & WM8962_HPOUTL_PGA_ENA) {
++ snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
++ snd_soc_read(codec, WM8962_HPOUTL_VOLUME));
++ return 1;
++ }
+
+ /* ...otherwise the right. The VU is stereo. */
+- if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
+- return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
+- reg_cache[WM8962_HPOUTR_VOLUME]);
++ if (ret & WM8962_HPOUTR_PGA_ENA)
++ snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
++ snd_soc_read(codec, WM8962_HPOUTR_VOLUME));
+
+- return 0;
++ return 1;
+ }
+
+ /* The VU bits for the speakers are in a different register to the mute
+@@ -3374,7 +3376,6 @@ static int wm8962_probe(struct snd_soc_c
+ int ret;
+ struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+ struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
+- u16 *reg_cache = codec->reg_cache;
+ int i, trigger, irq_pol;
+ bool dmicclk, dmicdat;
+
+@@ -3432,8 +3433,9 @@ static int wm8962_probe(struct snd_soc_c
+
+ /* Put the speakers into mono mode? */
+ if (pdata->spk_mono)
+- reg_cache[WM8962_CLASS_D_CONTROL_2]
+- |= WM8962_SPK_MONO;
++ snd_soc_update_bits(codec, WM8962_CLASS_D_CONTROL_2,
++ WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
++
+
+ /* Micbias setup, detection enable and detection
+ * threasholds. */
alsa-hda-yet-another-dell-headset-mic-quirk.patch
alsa-hda-guess-what-it-s-two-more-dell-headset-mic-quirks.patch
firewire-fix-libdc1394-flycap2-iso-event-regression.patch
+asoc-sglt5000-fix-the-default-value-of-chip_sss_ctrl.patch
+asoc-max98088-fix-element-type-of-the-register-cache.patch
+asoc-tegra-correct-playback_dma_data-setup.patch
+asoc-wm8962-remove-remaining-direct-register-cache-accesses.patch
+arm-7722-1-zimage-convert-32bits-memory-size-and-address-from-atag-to-64bits-dtb.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
