]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
net: stmmac: Extend CSR calc support
authorJan Petrous (OSS) <jan.petrous@oss.nxp.com>
Thu, 5 Dec 2024 16:42:59 +0000 (17:42 +0100)
committerJakub Kicinski <kuba@kernel.org>
Tue, 10 Dec 2024 02:36:02 +0000 (18:36 -0800)
Add support for CSR clock range up to 800 MHz.

Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Link: https://patch.msgid.link/20241205-upstream_s32cc_gmac-v8-2-ec1d180df815@oss.nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/stmicro/stmmac/common.h
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
include/linux/stmmac.h

index 1367fa5c9b8ea3a8ed5fa26274147a01b6948563..70d601f454811b3d6986dff955c0874f1cf383eb 100644 (file)
@@ -257,6 +257,8 @@ struct stmmac_safety_stats {
 #define CSR_F_150M     150000000
 #define CSR_F_250M     250000000
 #define CSR_F_300M     300000000
+#define CSR_F_500M     500000000
+#define CSR_F_800M     800000000
 
 #define        MAC_CSR_H_FRQ_MASK      0x20
 
index 9b262cdad60b28befcc8d92111c8feb9d65c6bcc..3cb7ad6ccc4e5ec82b2a3e81a961a22b5d302cd4 100644 (file)
@@ -325,6 +325,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
                        priv->clk_csr = STMMAC_CSR_150_250M;
                else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
                        priv->clk_csr = STMMAC_CSR_250_300M;
+               else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M))
+                       priv->clk_csr = STMMAC_CSR_300_500M;
+               else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M))
+                       priv->clk_csr = STMMAC_CSR_500_800M;
        }
 
        if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
index 75cbfb5763582a1f72fbfb52bfe015cf927e54eb..865d0fe26f98c30557de7bb0680ec4a92e7f38d1 100644 (file)
@@ -34,6 +34,8 @@
 #define        STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
 #define        STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
 #define        STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/124 */
+#define        STMMAC_CSR_300_500M     0x6     /* MDC = clk_scr_i/204 */
+#define        STMMAC_CSR_500_800M     0x7     /* MDC = clk_scr_i/324 */
 
 /* MTL algorithms identifiers */
 #define MTL_TX_ALGORITHM_WRR   0x0