drm/amd/display: Add z-state support policy for dcn35

[Why]
DML2 means that the dcn3x policy for calculating z-state support
no longer runs from validate_bandwidth.

This means we are unconditionally allowing Z8, the hardware default.

[How]
Port the policy over to DCN35, but with a few modifications:
- Don't use min_dst_y_next_start as a check for Z8/Z10 allow
- Add support for overriding the Z10 stutter period per ASIC
- Cleanup the code to make the policy assignment more clear

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9316b737a8ba892c6494687bae472e206d01283d..c4e5c3350b754f487452e7c87d95f05ed5e75d82 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -874,6 +874,7 @@ struct dc_debug_options {
        unsigned int seamless_boot_odm_combine;
        unsigned int force_odm_combine_4to1; //bit vector based on otg inst
        int minimum_z8_residency_time;
+       int minimum_z10_residency_time;
        bool disable_z9_mpc;
        unsigned int force_fclk_khz;
        bool enable_tri_buf;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index c7e011d26d41780262c06ce59dee7f13b3de8997..8f1a9c959bb54dcafe8211d38cae3164d4344395 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -1712,6 +1712,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc,
 
        out = dml2_validate(dc, context, fast_validate);
 
+       if (fast_validate)
+               return out;
+
+       DC_FP_START();
+       dcn35_decide_zstate_support(dc, context);
+       DC_FP_END();
+
        return out;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index a5fe523668e94aaaa6a9e1ba88739b58bc39e5a2..dee80429fc4c89d54cdf5c88864dd7e450482640 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -507,3 +507,37 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
 
        return pipe_cnt;
 }
+
+void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
+{
+       enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;
+       unsigned int i, plane_count = 0;
+
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               if (context->res_ctx.pipe_ctx[i].plane_state)
+                       plane_count++;
+       }
+
+       if (plane_count == 0) {
+               support = DCN_ZSTATE_SUPPORT_ALLOW;
+       } else if (plane_count == 1 && context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
+               struct dc_link *link = context->streams[0]->sink->link;
+               bool is_pwrseq0 = link && link->link_index == 0;
+               bool is_psr1 = link && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr;
+               int minmum_z8_residency =
+                       dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
+               bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
+               int minmum_z10_residency =
+                       dc->debug.minimum_z10_residency_time > 0 ? dc->debug.minimum_z10_residency_time : 5000;
+               bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency;
+
+               if (is_pwrseq0 && allow_z10)
+                       support = DCN_ZSTATE_SUPPORT_ALLOW;
+               else if (is_pwrseq0 && is_psr1)
+                       support = allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
+               else if (allow_z8)
+                       support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
+       }
+
+       context->bw_ctx.bw.dcn.clk.zstate_support = support;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
index e8d5a170893e3b650b67d77f61db08be13e05108..067480fc3691322154f419e57479333be51b6b66 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
@@ -39,4 +39,6 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
                                              display_e2e_pipe_params_st *pipes,
                                              bool fast_validate);
 
+void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);
+
 #endif