drm/amd: Restore cached manual clock settings during resume

[ Upstream commit 796ff8a7e01bd18738d3bb4111f9d6f963145d29 ]

If the SCLK limits have been set before S3 they will not
be restored. The limits are however cached in the driver and so
they can be restored by running a commit sequence during resume.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250725031222.3015095-3-superm1@kernel.org
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 4e9526924d09057a9ba854305e17eded900ced82)
Cc: stable@vger.kernel.org
[ Adjust context ]
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7537964c3c9982713fc8634f4c42c432ef89d7e4..26b8e232f85825f694b6624803a747847bf4a47c 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -76,6 +76,9 @@ static void smu_power_profile_mode_get(struct smu_context *smu,
                                       enum PP_SMC_POWER_PROFILE profile_mode);
 static void smu_power_profile_mode_put(struct smu_context *smu,
                                       enum PP_SMC_POWER_PROFILE profile_mode);
+static int smu_od_edit_dpm_table(void *handle,
+                                enum PP_OD_DPM_TABLE_COMMAND type,
+                                long *input, uint32_t size);
 
 static int smu_sys_get_pp_feature_mask(void *handle,
                                       char *buf)
@@ -2144,6 +2147,7 @@ static int smu_resume(struct amdgpu_ip_block *ip_block)
        int ret;
        struct amdgpu_device *adev = ip_block->adev;
        struct smu_context *smu = adev->powerplay.pp_handle;
+       struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 
        if (amdgpu_sriov_multi_vf_mode(adev))
                return 0;
@@ -2181,6 +2185,12 @@ static int smu_resume(struct amdgpu_ip_block *ip_block)
                        return ret;
        }
 
+       if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
+               ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0);
+               if (ret)
+                       return ret;
+       }
+
        dev_info(adev->dev, "SMU is resumed successfully!\n");
 
        return 0;