]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: ti: k3-am642-tqma64xxl: add boot phase tags
authorMatthias Schiffer <matthias.schiffer@ew.tq-group.com>
Wed, 5 Nov 2025 14:17:26 +0000 (15:17 +0100)
committerVignesh Raghavendra <vigneshr@ti.com>
Thu, 6 Nov 2025 05:27:39 +0000 (10:57 +0530)
Similar to other AM64x-based boards, add boot phase tags to make the
Device Trees usable for firmware/bootloaders without modification.

Supported boot devices are eMMC/SD card, SPI-NOR and USB (both mass
storage and DFU). The I2C EEPROM is included to allow the firmware to
select the correct RAM configuration for different TQMa64xxL variants.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://patch.msgid.link/20251105141726.39579-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi

index 8f64d6272b1ba4a7471affaa3db2bd2b5adff95f..7a69e729eae842d45ed16a41df41803dd30ef98c 100644 (file)
                regulator-max-microvolt = <3300000>;
                gpio = <&main_gpio1 43 GPIO_ACTIVE_HIGH>;
                enable-active-high;
+               bootph-all;
        };
 };
 
                "", "", "STATUS_OUT_3", "EN_DIG_OUT_4", /* 32-35 */
                "", "", "STATUS_OUT_4", "DIG_IN_1", /* 36-39 */
                "DIG_IN_2", "DIG_IN_3", "DIG_IN_4"; /* 40- */
+       bootph-all;
 };
 
 &main_gpio1 {
                "", "", "", "", /* 60-63 */
                "", "", "", "ADC_INT#", /* 64-67 */
                "BG95_PWRKEY", "BG95_RESET"; /* 68- */
+       bootph-all;
 
        line50-hog {
                /* See also usb0 */
 &main_uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_uart0_pins>;
+       bootph-pre-ram;
        status = "okay";
 };
 
 
 &serdes_ln_ctrl {
        idle-states = <AM64_SERDES0_LANE0_USB>;
+       bootph-all;
+};
+
+&serdes_refclk {
+       bootph-all;
 };
 
 &serdes0 {
                reg = <0>;
                #phy-cells = <0>;
                resets = <&serdes_wiz0 1>;
+               bootph-all;
                cdns,num-lanes = <1>;
                cdns,phy-type = <PHY_TYPE_USB3>;
        };
        cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>;
        disable-wp;
        no-mmc;
+       bootph-all;
        ti,fails-without-test-cd;
        /* Enabled by overlay */
 };
        maximum-speed = "super-speed";
        phys = <&serdes0_usb_link>;
        phy-names = "cdns3,usb3-phy";
+       bootph-all;
 };
 
 &usbss0 {
+       bootph-all;
        ti,vbus-divider;
 };
 
                        /* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */
                        AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7)
                >;
+               bootph-all;
        };
 
        main_gpio1_hog_pins: main-gpio1-hog-pins {
                        /* (#N/A) MMC1_CLKLB */
                        AM64X_IOPAD(0x0290, PIN_INPUT, 0)
                >;
+               bootph-all;
        };
 
        main_mmc1_reg_pins: main-mmc1-reg-pins {
                        /* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */
                        AM64X_IOPAD(0x020c, PIN_OUTPUT, 7)
                >;
+               bootph-all;
        };
 
        main_mmc1_wifi_pwrseq_pins: main-mmc1-wifi-pwrseq-pins {
                        /* (C16) UART0_TXD */
                        AM64X_IOPAD(0x0234, PIN_OUTPUT, 0)
                >;
+               bootph-pre-ram;
        };
 
        main_uart1_pins: main-uart1-pins {
                        /* (E19) USB0_DRVVBUS */
                        AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0)
                >;
+               bootph-all;
        };
 
        pru_icssg1_mdio_pins: pru-icssg1-mdio-pins {
index ff3b2e0b8dd45bf775d31bba2c6942275fcac81f..dde19d0784e313a944f4dd35d4d7fd06b2e03122 100644 (file)
@@ -17,7 +17,7 @@
                device_type = "memory";
                /* 1G RAM - default variant */
                reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
-
+               bootph-pre-ram;
        };
 
        reserved_memory: reserved-memory {
        };
 };
 
+&fss {
+       bootph-all;
+};
+
 &main_i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c0_pins>;
        clock-frequency = <400000>;
+       bootph-pre-ram;
        status = "okay";
 
        tmp1075: temperature-sensor@4a {
@@ -72,6 +77,7 @@
                vcc-supply = <&reg_1v8>;
                pagesize = <16>;
                read-only;
+               bootph-pre-ram;
        };
 
        pcf85063: rtc@51 {
 };
 
 &ospi0 {
-       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&ospi0_pins>;
+       bootph-all;
+       status = "okay";
 
        flash@0 {
                compatible = "jedec,spi-nor";
                spi-tx-bus-width = <8>;
                spi-rx-bus-width = <8>;
                spi-max-frequency = <84000000>;
+               bootph-all;
                cdns,tshsl-ns = <60>;
                cdns,tsd2d-ns = <60>;
                cdns,tchsh-ns = <60>;
        disable-wp;
        no-sdio;
        no-sd;
+       bootph-all;
        ti,driver-strength-ohm = <50>;
 };
 
                        /* (B18) I2C0_SDA */
                        AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0)
                >;
+               bootph-pre-ram;
        };
 
        ospi0_pins: ospi0-pins {
                        /* (N19) OSPI0_DQS */
                        AM64X_IOPAD(0x0008, PIN_INPUT, 0)
                >;
+               bootph-all;
        };
 };