target-arm queue:
* Fix PC test for LDM (exception return)
* Implement ARMv8.0-SB
* Implement ARMv8.0-PredInv
* Implement ARMv8.4-CondM
* Implement ARMv8.5-CondM
* Implement ARMv8.5-FRINT
* hw/arm/stellaris: Implement watchdog timer
* virt: support more than 255GB of RAM
# gpg: Signature made Tue 05 Mar 2019 16:49:47 GMT
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20190305: (22 commits)
hw/arm/stellaris: Implement watchdog timer
hw/arm/virt: Bump the 255GB initial RAM limit
hw/arm/virt: Check the VCPU PA range in TCG mode
hw/arm/virt: Implement kvm_type function for 4.0 machine
hw/arm/virt: Dynamic memory map depending on RAM requirements
vl: Set machine ram_size, maxram_size and ram_slots earlier
kvm: add kvm_arm_get_max_vm_ipa_size
hw/boards: Add a MachineState parameter to kvm_type callback
hw/arm/virt: Split the memory map description
hw/arm/virt: Rename highmem IO regions
hw/arm/boot: introduce fdt_add_memory_node helper
target/arm: Implement ARMv8.5-FRINT
target/arm: Restructure handle_fp_1src_{single, double}
target/arm: Implement ARMv8.5-CondM
target/arm: Implement ARMv8.4-CondM
target/arm: Rearrange disas_data_proc_reg
target/arm: Add set/clear_pstate_bits, share gen_ss_advance
target/arm: Split helper_msr_i_pstate into 3
target/arm: Implement ARMv8.0-PredInv
target/arm: Implement ARMv8.0-SB
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>