Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports"

This reverts commit 794a066688038df46c01e177cc6faebded0acba4 because it
misunderstood interworking between arm trusted firmware and the common
phy driver, and does not consistently resolve the issue it was intended
to address.

Further diagnostics have revealed the root cause for the reported system
lock-up in a race condition between pci driver probe and clock core
disabling unused clocks.

Revert the wrong change restoring driver control over all pci lanes.
As a temporary workaround for the original issue, users can boot with
"clk_ignore_unused".

Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
index 5cf83d8ca1f598a30c5a979e1e30920c89dbd4b0..2507896d58f9b6b86e7033f28c49964f8f90d7c0 100644 (file)
--- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
+++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
@@ -413,13 +413,7 @@
 /* SRDS #0,#1,#2,#3 - PCIe */
 &cp0_pcie0 {
        num-lanes = <4>;
-       /*
-        * The mvebu-comphy driver does not currently know how to pass correct
-        * lane-count to ATF while configuring the serdes lanes.
-        * Rely on bootloader configuration only.
-        *
-        * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
-        */
+       phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
        status = "okay";
 };
 
@@ -481,13 +475,7 @@
 /* SRDS #0,#1 - PCIe */
 &cp1_pcie0 {
        num-lanes = <2>;
-       /*
-        * The mvebu-comphy driver does not currently know how to pass correct
-        * lane-count to ATF while configuring the serdes lanes.
-        * Rely on bootloader configuration only.
-        *
-        * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
-        */
+       phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
        status = "okay";
 };