]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arm64: versal: Add description for a2197-p x-prc-04
authorMichal Simek <michal.simek@xilinx.com>
Mon, 24 Jun 2019 13:31:50 +0000 (15:31 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 28 Jun 2019 09:25:30 +0000 (11:25 +0200)
Add description based on specification and schematics.
All FIXMEs should be fixed when HW is ready.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/Makefile
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi.dts [new file with mode: 0644]
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-04-revA.dts [new file with mode: 0644]
configs/xilinx_versal_virt_defconfig

index 8cecd1bad070340a0f473621dd4e3669a9bfabf0..b6268eedced2f95ba949d794c1b97e9c75a893c9 100644 (file)
@@ -216,6 +216,8 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
        versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi.dtb \
        versal-vc-p-a2197-00-revA-x-prc-02-revA.dtb \
        versal-vc-p-a2197-00-revA-x-prc-03-revA.dtb \
+       versal-vc-p-a2197-00-revA-x-prc-04-revA.dtb \
+       versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi.dtb \
        versal-vc-d-d1760-01-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
        zynqmp-r5.dtb
diff --git a/arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi.dts b/arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi.dts
new file mode 100644 (file)
index 0000000..5be15fa
--- /dev/null
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal X-PRC-04 revA (SE4)
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "versal-vc-p-a2197-00-revA-x-prc-04-revA.dts"
+
+/ {
+       chosen {
+               bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused";
+               stdout-path = "serial0:115200";
+       };
+
+       aliases {
+               spi0 = &ospi;
+       };
+};
+
+/* Mutually exclusive with qspi */
+&ospi {
+       status = "okay"; /* U163/U97 MT35XU02G */
+};
+
+&qspi {
+       status = "disabled";
+};
diff --git a/arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-04-revA.dts b/arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-04-revA.dts
new file mode 100644 (file)
index 0000000..735147e
--- /dev/null
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal X-PRC-04 revA (SE4)
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "versal-vc-p-a2197-00-revA.dts"
+
+/ {
+       chosen {
+               bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused";
+               stdout-path = "serial0:115200";
+       };
+
+       aliases {
+               serial0 = &serial0;
+               serial1 = &serial1;
+               ethernet1 = &gem1;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               mmc0 = &sdhci1;
+               gpio0 = &gpio;
+               spi0 = &qspi;
+               spi1 = &spi0;
+               usb0 = &usb0;
+       };
+};
+
+&gem1 {
+       status = "okay";
+       phy-handle = <&phy1>; /* u175 */
+       phy-mode = "rgmii-id"; /* RTL8211DN */
+       phy1: phy@1 {
+               reg = <1>; /* FIXME */
+       };
+};
+
+&gpio {
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+       clock-frequency = <400000>;
+       eeprom_versal: eeprom@51 { /* U153 */
+               compatible = "st,24c128", "atmel,24c128";
+               reg = <0x51>;
+       };
+};
+
+&i2c1 {
+       status = "okay";
+       clock-frequency = <400000>;
+       eeprom: eeprom@51 { /* U155 */
+               compatible = "st,24c128", "atmel,24c128";
+               reg = <0x51>;
+       };
+};
+
+&qspi {
+       status = "okay"; /* u93 and u92 and u161 and u160 */
+       num-cs = <1>;
+       is-dual = <1>;
+       is-stacked = <1>;
+       spi-rx-bus-width = <4>;
+       spi-tx-bus-width = <4>;
+
+       flash@0 {
+               compatible = "m25p80", "spi-flash";
+               reg = <0>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <108000000>;
+       };
+};
+
+&sdhci1 { /* J3 MIO26, MIO29 - MIO33 */
+       status = "okay";
+       disable-wp;
+       xlnx,mio_bank = <1>; /* FIXME */
+       no-1-8-v;
+};
+
+&serial0 { /* MIO35 - MIO37 */
+       status = "okay";
+};
+
+&serial1 { /* MIO4 - MIO7 RS232 */
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+       num-cs = <1>;
+
+       flash@0 { /* U171 - IS25LP016B - 16Mb */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "issi,is25lp016b", "m25p80", "spi-flash";
+               spi-max-frequency = <104000000>;
+               reg = <0>;
+
+               partition@0 {
+                       label = "spi0-flash0";
+                       reg = <0 0x200000>;
+               };
+       };
+};
+
+&usb0 {
+       status = "okay";
+       xlnx,usb-polarity = <0x0>;
+       xlnx,usb-reset-mode = <0x0>;
+};
+
+&dwc3_0 { /* USB 2.0 host - U99 */
+       status = "okay";
+       dr_mode = "host";
+       maximum-speed = "high-speed";
+       snps,dis_u2_susphy_quirk;
+       snps,dis_u3_susphy_quirk;
+       snps,usb3_lpm_capable;
+       phy-names = "usb3-phy";
+};
index ad93c8e972d6ddc62873d5d6c3842d2c1efcec4d..e106ffb14386c18cc2383dad426e19b7046b1824 100644 (file)
@@ -46,7 +46,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 CONFIG_OF_BOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="versal-vc-p-a2197-00-revA-x-prc-01-revA"
-CONFIG_OF_LIST="versal-vc-p-a2197-00-revA-x-prc-01-revA versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi versal-vc-p-a2197-00-revA-x-prc-02-revA versal-vc-p-a2197-00-revA-x-prc-03-revA versal-vc-d-d1760-01-revA "
+CONFIG_OF_LIST="versal-vc-p-a2197-00-revA-x-prc-01-revA versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi versal-vc-p-a2197-00-revA-x-prc-02-revA versal-vc-p-a2197-00-revA-x-prc-03-revA versal-vc-p-a2197-00-revA-x-prc-04-revA versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi versal-vc-d-d1760-01-revA"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y