+++ /dev/null
-From db4ff423cd1659580e541a2d4363342f15c14230 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <david1.zhou@amd.com>
-Date: Tue, 28 May 2019 10:46:04 +0800
-Subject: drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-From: Chunming Zhou <david1.zhou@amd.com>
-
-commit db4ff423cd1659580e541a2d4363342f15c14230 upstream.
-
-Can expose it now that the khronos has exposed the
-vlk extension.
-
-Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
-Reviewed-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -1422,7 +1422,8 @@ static struct drm_driver kms_driver = {
- .driver_features =
- DRIVER_USE_AGP | DRIVER_ATOMIC |
- DRIVER_GEM |
-- DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
-+ DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
-+ DRIVER_SYNCOBJ_TIMELINE,
- .load = amdgpu_driver_load_kms,
- .open = amdgpu_driver_open_kms,
- .postclose = amdgpu_driver_postclose_kms,
--- /dev/null
+From 3c8f5f2a32ae70c831a41a00405370c63dbdee6c Mon Sep 17 00:00:00 2001
+From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
+Date: Wed, 8 Jan 2020 09:34:16 -0800
+Subject: drm/i915/gen9: Clear residual context state on context switch
+
+From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
+
+commit bc8a76a152c5f9ef3b48104154a65a68a8b76946 upstream.
+
+Intel ID: PSIRT-TA-201910-001
+CVEID: CVE-2019-14615
+
+Intel GPU Hardware prior to Gen11 does not clear EU state
+during a context switch. This can result in information
+leakage between contexts.
+
+For Gen8 and Gen9, hardware provides a mechanism for
+fast cleardown of the EU state, by issuing a PIPE_CONTROL
+with bit 27 set. We can use this in a context batch buffer
+to explicitly cleardown the state on every context switch.
+
+As this workaround is already in place for gen8, we can borrow
+the code verbatim for Gen9.
+
+Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
+Cc: Kumar Valsan Prathap <prathap.kumar.valsan@intel.com>
+Cc: Chris Wilson <chris.p.wilson@intel.com>
+Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
+Cc: Bloomfield Jon <jon.bloomfield@intel.com>
+Cc: Dutt Sudeep <sudeep.dutt@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/gt/intel_lrc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
++++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
+@@ -2132,6 +2132,14 @@ static u32 *gen9_init_indirectctx_bb(str
+ /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
+ batch = gen8_emit_flush_coherentl3_wa(engine, batch);
+
++ /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
++ batch = gen8_emit_pipe_control(batch,
++ PIPE_CONTROL_FLUSH_L3 |
++ PIPE_CONTROL_GLOBAL_GTT_IVB |
++ PIPE_CONTROL_CS_STALL |
++ PIPE_CONTROL_QW_WRITE,
++ slm_offset(engine));
++
+ batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
+
+ /* WaMediaPoolStateCmdInWABB:bxt,glk */
input-add-safety-guards-to-input_set_keycode.patch
input-input_event-fix-struct-padding-on-sparc64.patch
drm-i915-add-wa_1408615072-and-wa_1407596294-to-icl-ehl.patch
-drm-amdgpu-add-driver_syncobj_timeline-to-amdgpu.patch
revert-drm-amdgpu-set-no-retry-as-default.patch
drm-sun4i-tcon-set-rgb-dclk-min.-divider-based-on-hardware-model.patch
drm-fb-helper-round-up-bits_per_pixel-if-possible.patch
netfilter-arp_tables-init-netns-pointer-in-xt_tgchk_param-struct.patch
netfilter-conntrack-dccp-sctp-handle-null-timeout-argument.patch
netfilter-ipset-avoid-null-deref-when-ipset_attr_lineno-is-present.patch
+drm-i915-gen9-clear-residual-context-state-on-context-switch.patch