+2012-08-09 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elfxx-mips.c (LA25_LUI_MICROMIPS_1, LA25_LUI_MICROMIPS_2):
+ Remove macros, folding them into...
+ (LA25_LUI_MICROMIPS): ... this new macro.
+ (LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise into...
+ (LA25_J_MICROMIPS): ... this new macro.
+ (LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise
+ into...
+ (LA25_ADDIU_MICROMIPS): ... this new macro.
+ (bfd_put_micromips_32, bfd_get_micromips_32): New functions.
+ (mips_elf_create_la25_stub): Use them.
+ (check_br32_dslot, check_br32, check_relocated_bzc): Likewise.
+ (_bfd_mips_elf_relax_section): Likewise.
+
+ * elf32-ppc.c (ppc_elf_relocate_section): Assert that dynindx is
+ not minus one.
+ * elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
+
+2012-08-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elflink.c (_bfd_elf_merge_symbol): Also override the version
+ a dynamic symbol defaulted to if preempted with a hidden or
+ internal definition.
+
+ * elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections): Look up
+ the options section in the output rather than input BFD to
+ decide if to add a DT_MIPS_OPTIONS tag.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config.bfd: Wrap mips*el-*-linux* and mips*-*-linux* into
+ #ifdef BFD64.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elfxx-mips.c (mips_elf_calculate_relocation): Fix the handling
+ of protected symbols.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elflink.c (bfd_elf_record_link_assignment): Remove --defsym
+ symbols special case.
+
+ * elf64-mips.c (mips16_elf64_howto_table_rela): Correct src_mask
+ field initializers throughout.
+ * elfn32-mips.c (elf_mips16_howto_table_rela): Likewise.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elfxx-mips.c (mips_elf_perform_relocation): Update the
+ cross-mode jump message.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* cpu-ia64-opc.c (ins_cnt6a): New function.
targ_selvecs="bfd_elf32_ntradlittlemips_vec bfd_elf32_tradbigmips_vec bfd_elf32_tradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec"
want64=true
;;
-#endif
mips*el-*-linux*)
targ_defvec=bfd_elf32_tradlittlemips_vec
targ_selvecs="bfd_elf32_tradbigmips_vec ecoff_little_vec ecoff_big_vec bfd_elf32_ntradlittlemips_vec bfd_elf64_tradlittlemips_vec bfd_elf32_ntradbigmips_vec bfd_elf64_tradbigmips_vec"
targ_selvecs="bfd_elf32_tradlittlemips_vec ecoff_big_vec ecoff_little_vec bfd_elf32_ntradbigmips_vec bfd_elf64_tradbigmips_vec bfd_elf32_ntradlittlemips_vec bfd_elf64_tradlittlemips_vec"
want64=true
;;
-#ifdef BFD64
mips64*el-*-freebsd* | mips64*el-*-kfreebsd*-gnu)
# FreeBSD vectors
targ_defvec=bfd_elf32_ntradlittlemips_freebsd_vec
;
else
{
+ BFD_ASSERT (h->dynindx != -1);
indx = h->dynindx;
unresolved_reloc = FALSE;
}
|| h->root.type == bfd_link_hash_undefweak))
|| !SYMBOL_REFERENCES_LOCAL (info, h))
{
+ BFD_ASSERT (h->dynindx != -1);
unresolved_reloc = FALSE;
outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
outrel.r_addend = rel->r_addend;
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GD", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_LDM", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GOTTPREL", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
;
else
{
+ BFD_ASSERT (h->elf.dynindx != -1);
indx = h->elf.dynindx;
unresolved_reloc = FALSE;
}
else if (!SYMBOL_CALLS_LOCAL (info, &h->elf)
&& !is_opd
&& r_type != R_PPC64_TOC)
- outrel.r_info = ELF64_R_INFO (h->elf.dynindx, r_type);
+ {
+ BFD_ASSERT (h->elf.dynindx != -1);
+ outrel.r_info = ELF64_R_INFO (h->elf.dynindx, r_type);
+ }
else
{
/* This symbol is local, or marked to become local,
h->def_regular = 1;
- if (provide && hidden)
+ if (hidden)
{
bed = get_elf_backend_data (output_bfd);
h->other = (h->other & ~ELF_ST_VISIBILITY (-1)) | STV_HIDDEN;
vh->root.type = h->root.type;
h->root.type = bfd_link_hash_indirect;
(*bed->elf_backend_copy_indirect_symbol) (info, vh, h);
- /* Protected symbols will override the dynamic definition
- with default version. */
- if (ELF_ST_VISIBILITY (sym->st_other) == STV_PROTECTED)
+
+ h->root.u.i.link = (struct bfd_link_hash_entry *) vh;
+ if (ELF_ST_VISIBILITY (sym->st_other) != STV_PROTECTED)
{
- h->root.u.i.link = (struct bfd_link_hash_entry *) vh;
- vh->dynamic_def = 1;
- vh->ref_dynamic = 1;
+ /* If the new symbol is hidden or internal, completely undo
+ any dynamic link state. */
+ (*bed->elf_backend_hide_symbol) (info, h, TRUE);
+ h->forced_local = 0;
+ h->ref_dynamic = 0;
}
else
- {
- h->root.type = vh->root.type;
- vh->ref_dynamic = 0;
- /* We have to hide it here since it was made dynamic
- global with extra bits when the symbol info was
- copied from the old dynamic definition. */
- (*bed->elf_backend_hide_symbol) (info, vh, TRUE);
- }
+ h->ref_dynamic = 1;
+
+ h->def_dynamic = 0;
+ h->dynamic_def = 0;
+ /* FIXME: Should we check type and size for protected symbol? */
+ h->size = 0;
+ h->type = 0;
+
h = vh;
}
else
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GD", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_LDM", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GOTTPREL", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
#define LA25_LUI(VAL) (0x3c190000 | (VAL)) /* lui t9,VAL */
#define LA25_J(VAL) (0x08000000 | (((VAL) >> 2) & 0x3ffffff)) /* j VAL */
#define LA25_ADDIU(VAL) (0x27390000 | (VAL)) /* addiu t9,t9,VAL */
-#define LA25_LUI_MICROMIPS_1(VAL) (0x41b9) /* lui t9,VAL */
-#define LA25_LUI_MICROMIPS_2(VAL) (VAL)
-#define LA25_J_MICROMIPS_1(VAL) (0xd400 | (((VAL) >> 17) & 0x3ff)) /* j VAL */
-#define LA25_J_MICROMIPS_2(VAL) ((VAL) >> 1)
-#define LA25_ADDIU_MICROMIPS_1(VAL) (0x3339) /* addiu t9,t9,VAL */
-#define LA25_ADDIU_MICROMIPS_2(VAL) (VAL)
+#define LA25_LUI_MICROMIPS(VAL) \
+ (0x41b90000 | (VAL)) /* lui t9,VAL */
+#define LA25_J_MICROMIPS(VAL) \
+ (0xd4000000 | (((VAL) >> 1) & 0x3ffffff)) /* j VAL */
+#define LA25_ADDIU_MICROMIPS(VAL) \
+ (0x33390000 | (VAL)) /* addiu t9,t9,VAL */
/* This structure is passed to mips_elf_sort_hash_table_f when sorting
the dynamic symbols. */
0x24180000 /* li t8, <pltindex> */
};
\f
+/* microMIPS 32-bit opcode helper installer. */
+
+static void
+bfd_put_micromips_32 (const bfd *abfd, bfd_vma opcode, bfd_byte *ptr)
+{
+ bfd_put_16 (abfd, (opcode >> 16) & 0xffff, ptr);
+ bfd_put_16 (abfd, opcode & 0xffff, ptr + 2);
+}
+
+/* microMIPS 32-bit opcode helper retriever. */
+
+static bfd_vma
+bfd_get_micromips_32 (const bfd *abfd, const bfd_byte *ptr)
+{
+ return (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+}
+\f
/* Look up an entry in a MIPS ELF linker hash table. */
#define mips_elf_link_hash_lookup(table, string, create, copy, follow) \
&& (target_is_16_bit_code_p
|| target_is_micromips_code_p))));
- local_p = h == NULL || SYMBOL_REFERENCES_LOCAL (info, &h->root);
+ local_p = (h == NULL
+ || (h->got_only_for_calls
+ ? SYMBOL_CALLS_LOCAL (info, &h->root)
+ : SYMBOL_REFERENCES_LOCAL (info, &h->root)));
gp0 = _bfd_get_gp_value (input_bfd);
gp = _bfd_get_gp_value (abfd);
jalx_opcode = 0x1d;
}
- /* If the opcode is not JAL or JALX, there's a problem. */
+ /* If the opcode is not JAL or JALX, there's a problem. We cannot
+ convert J or JALS to JALX. */
if (!ok)
{
(*_bfd_error_handler)
- (_("%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled."),
+ (_("%B: %A+0x%lx: Unsupported jump between ISA modes; consider recompiling with interlinking enabled."),
input_bfd,
input_section,
(unsigned long) relocation->r_offset);
if (IRIX_COMPAT (dynobj) == ict_irix6
&& (bfd_get_section_by_name
- (dynobj, MIPS_ELF_OPTIONS_SECTION_NAME (dynobj)))
+ (output_bfd, MIPS_ELF_OPTIONS_SECTION_NAME (dynobj)))
&& !MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_MIPS_OPTIONS, 0))
return FALSE;
}
loc += offset;
if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
{
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_1 (target_high),
- loc);
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_2 (target_high),
- loc + 2);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_1 (target_low),
- loc + 4);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_2 (target_low),
- loc + 6);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_LUI_MICROMIPS (target_high),
+ loc);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_ADDIU_MICROMIPS (target_low),
+ loc + 4);
}
else
{
loc += offset;
if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
{
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_1 (target_high),
- loc);
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_2 (target_high),
- loc + 2);
- bfd_put_16 (hti->output_bfd, LA25_J_MICROMIPS_1 (target), loc + 4);
- bfd_put_16 (hti->output_bfd, LA25_J_MICROMIPS_2 (target), loc + 6);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_1 (target_low),
- loc + 8);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_2 (target_low),
- loc + 10);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_LUI_MICROMIPS (target_high), loc);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_J_MICROMIPS (target), loc + 4);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_ADDIU_MICROMIPS (target_low), loc + 8);
bfd_put_32 (hti->output_bfd, 0, loc + 12);
}
else
unsigned long opcode;
int bdsize;
- opcode = (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
if (find_match (opcode, ds_insns_32_bd32) >= 0)
/* 32-bit branch/jump with a 32-bit delay slot. */
bdsize = 4;
{
unsigned long opcode;
- opcode = (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
if (MATCH (opcode, j_insn_32)
/* J */
|| MATCH (opcode, bc_insn_32)
const Elf_Internal_Rela *irel;
unsigned long opcode;
- opcode = bfd_get_16 (abfd, ptr);
- opcode <<= 16;
- opcode |= bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
if (find_match (opcode, bzc_insns_32) < 0)
return FALSE;
if (irel->r_offset + 4 > sec->size)
continue;
- opcode = bfd_get_16 (abfd, ptr ) << 16;
- opcode |= bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
/* This is the pc-relative distance from the instruction the
relocation is applied to, to the symbol referred. */
continue;
}
- nextopc = bfd_get_16 (abfd, contents + irel[1].r_offset ) << 16;
- nextopc |= bfd_get_16 (abfd, contents + irel[1].r_offset + 2);
+ nextopc = bfd_get_micromips_32 (abfd, contents + irel[1].r_offset);
/* Give up unless the same register is used with both
relocations. */
nextopc = (addiupc_insn.match
| ADDIUPC_REG_FIELD (OP32_TREG (nextopc)));
- bfd_put_16 (abfd, (nextopc >> 16) & 0xffff,
- contents + irel[1].r_offset);
- bfd_put_16 (abfd, nextopc & 0xffff,
- contents + irel[1].r_offset + 2);
+ bfd_put_micromips_32 (abfd, nextopc,
+ contents + irel[1].r_offset);
}
/* Can't do anything, give up, sigh... */
| BZC32_REG_FIELD (reg)
| (opcode & 0xffff)); /* Addend value. */
- bfd_put_16 (abfd, (opcode >> 16) & 0xffff, ptr);
- bfd_put_16 (abfd, opcode & 0xffff, ptr + 2);
+ bfd_put_micromips_32 (abfd, opcode, ptr);
/* Delete the 16-bit delay slot NOP: two bytes from
irel->offset + 4. */
unsigned long n32opc;
bfd_boolean relaxed = FALSE;
- n32opc = bfd_get_16 (abfd, ptr + 4) << 16;
- n32opc |= bfd_get_16 (abfd, ptr + 6);
+ n32opc = bfd_get_micromips_32 (abfd, ptr + 4);
if (MATCH (n32opc, nop_insn_32))
{
{
/* JAL with 32-bit delay slot that is changed to a JALS
with 16-bit delay slot. */
- bfd_put_16 (abfd, (jal_insn_32_bd16.match >> 16) & 0xffff,
- ptr);
- bfd_put_16 (abfd, jal_insn_32_bd16.match & 0xffff,
- ptr + 2);
+ bfd_put_micromips_32 (abfd, jal_insn_32_bd16.match, ptr);
/* Delete 2 bytes from irel->r_offset + 6. */
delcnt = 2;
+ * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
+ (is_opcode_valid): Remove coprocessor instruction exclusions.
+ Replace OPCODE_IS_MEMBER with opcode_is_member.
+ (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ (macro): Remove coprocessor instruction exclusions.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-31 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * doc/c-mips.texi (MIPS Opts): Correct a typo in the -mips5
+ option.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (s_cpload, s_cpsetup): Fail if MIPS16 mode.
+ (s_cplocal, s_cprestore, s_cpreturn): Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (append_insn): Also handle moving delay-slot
+ instruction across frags for fixed branches.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * frags.c (frag_grow): Never shrink the obstack size requested
+ below the default.
+
* config/tc-mips.c (ISA_SUPPORTS_DSP_ASE): Also set if microMIPS
mode.
(ISA_SUPPORTS_DSPR2_ASE): Likewise.
/* True if CPU has seq/sne and seqi/snei instructions. */
#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
-/* True if CPU does not implement the all the coprocessor insns. For these
- CPUs only those COP insns are accepted that are explicitly marked to be
- available on the CPU. ISA membership for COP insns is ignored. */
-#define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU))
-
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
#define MF_HILO_INSN(PINFO) \
((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
-/* Returns true for a (non floating-point) coprocessor instruction. Reading
- or writing the condition code is only possible on the coprocessors and
- these insns are not marked with INSN_COP. Thus for these insns use the
- condition-code flags. */
-#define COP_INSN(PINFO) \
- (PINFO != INSN_MACRO \
- && ((PINFO) & (FP_S | FP_D)) == 0 \
- && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
-
/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
has been selected. This implies, in particular, that addresses of text
labels have their LSB set. */
if (mips_opts.ase_mcu)
isa |= INSN_MCU;
- /* Don't accept instructions based on the ISA if the CPU does not implement
- all the coprocessor insns. */
- if (NO_ISA_COP (mips_opts.arch)
- && COP_INSN (mo->pinfo))
- isa = 0;
-
- if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
+ if (!opcode_is_member (mo, isa, mips_opts.arch))
return FALSE;
/* Check whether the instruction or macro requires single-precision or
static bfd_boolean
is_opcode_valid_16 (const struct mips_opcode *mo)
{
- return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
+ return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
}
/* Return TRUE if the size of the microMIPS opcode MO matches one
move_insn (ip, delay.frag, delay.where);
move_insn (&delay, ip->frag, ip->where + insn_length (ip));
}
- else if (relaxed_branch)
+ else if (relaxed_branch || delay.frag != ip->frag)
{
/* Add the delay slot instruction to the end of the
current frag and shrink the fixed part of the
tempreg = AT;
used_at = 1;
ld_noat:
- if (coproc
- && NO_ISA_COP (mips_opts.arch)
- && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
- {
- as_bad (_("Opcode not supported on this processor: %s"),
- mips_cpu_info_from_arch (mips_opts.arch)->name);
- break;
- }
-
if (offset_expr.X_op != O_constant
&& offset_expr.X_op != O_symbol)
{
s = "c3";
copz:
gas_assert (!mips_opts.micromips);
- if (NO_ISA_COP (mips_opts.arch)
- && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
- {
- as_bad (_("Opcode not supported on this processor: %s"),
- mips_cpu_info_from_arch (mips_opts.arch)->name);
- break;
- }
-
/* For now we just do C (same as Cz). The parameter will be
stored in insn_opcode by mips_ip. */
macro_build (NULL, s, "C", ip->insn_opcode);
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
+ ignore_rest_of_line ();
+ return;
+ }
+
/* .cpload should be in a .set noreorder section. */
if (mips_opts.noreorder == 0)
as_warn (_(".cpload not in noreorder section"));
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
+ ignore_rest_of_line ();
+ return;
+ }
+
reg1 = tc_get_register (0);
SKIP_WHITESPACE ();
if (*input_line_pointer != ',')
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
+ ignore_rest_of_line ();
+ return;
+ }
+
mips_gp_register = tc_get_register (0);
demand_empty_rest_of_line ();
}
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
+ ignore_rest_of_line ();
+ return;
+ }
+
mips_cprestore_offset = get_absolute_expression ();
mips_cprestore_valid = 1;
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
+ ignore_rest_of_line ();
+ return;
+ }
+
macro_start ();
if (mips_cpreturn_register == -1)
{
@itemx -mips2
@itemx -mips3
@itemx -mips4
-@itemx -mips5xo
+@itemx -mips5
@itemx -mips32
@itemx -mips32r2
@itemx -mips64
if (newc < 0)
as_fatal (_("can't extend frag %u chars"), nchars);
- /* Force to allocate at least NEWC bytes. */
+ /* Force to allocate at least NEWC bytes, but not less than the
+ default. */
oldc = obstack_chunk_size (&frchain_now->frch_obstack);
- obstack_chunk_size (&frchain_now->frch_obstack) = newc;
+ if (newc > oldc)
+ obstack_chunk_size (&frchain_now->frch_obstack) = newc;
while (obstack_room (&frchain_now->frch_obstack) < nchars)
{
+ * gas/mips/mips.exp: Set has_newabi for all Linux targets.
+ * gas/mips/cfi-n64-1.d: Adjust for targets that do not infer the
+ ISA from the ABI.
+ * gas/mips/elf-rel-got-n32.d: Likewise.
+ * gas/mips/elf-rel-got-n64.d: Likewise.
+ * gas/mips/elf-rel-xgot-n32.d: Likewise.
+ * gas/mips/elf-rel-xgot-n64.d: Likewise.
+ * gas/mips/elf-rel18.d: Likewise.
+ * gas/mips/elf-rel28-n32.d: Likewise.
+ * gas/mips/elf-rel28-n64.d: Likewise.
+ * gas/mips/jal-newabi.d: Likewise.
+ * gas/mips/ldstla-n64-shared.d: Likewise.
+ * gas/mips/ldstla-n64-sym32.d: Likewise.
+ * gas/mips/ldstla-n64.d: Likewise.
+ * gas/mips/macro-warn-1-n32.d: Likewise.
+ * gas/mips/macro-warn-2-n32.d: Likewise.
+ * gas/mips/n32-consec.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * gas/mips/mips.exp: Set has_newabi for mips*-sde-elf* too.
+ * gas/mips/elf-rel-got-n32.s: Adjust padding.
+ * gas/mips/elf-rel-got-n64.s: Likewise.
+ * gas/mips/elf-rel23.s: Likewise.
+ * gas/mips/elf-rel28.s: Likewise.
+ * gas/mips/n32-consec.s: Likewise.
+ * gas/mips/elf-rel-xgot-n32.d: Adjust output expected.
+ * gas/mips/elf-rel-xgot-n64.d: Likewise.
+ * gas/mips/elf-rel23.d: Likewise.
+ * gas/mips/elf-rel23a.d: Likewise.
+ * gas/mips/elf-rel23b.d: Likewise.
+ * gas/mips/elf-rel28-n32.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * gas/mips/branch-swap-2.l: New list test.
+ * gas/mips/branch-swap-2.s: New test source.
+ * gas/mips/mips.exp: Run the new test.
+
* gas/mips/micromips@mips32-dsp.d: New test.
* gas/mips/micromips@mips32-dspr2.d: New test.
* gas/mips/mips32-dsp.s: Update padding.
-#as: -64 -EB
+#as: -march=from-abi -64 -EB
#objdump: -sj.eh_frame
.*
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF got reloc n32
-#as: -n32 -KPIC
+#as: -march=from-abi -n32 -KPIC
.*: +file format elf32-n.*mips.*
b .Lfn2
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
.end fn
.globl __start
__start:
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
+
.data
.align 2
sp2:
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF got reloc n64
-#as: -64 -KPIC
+#as: -march=from-abi -64 -KPIC
.*: +file format elf64-.*mips.*
ld $5,dl2+34($5)
b .Lfn2
-# Force at least 8 (non-deddlay-slot) zero bytes, to make 'objdump' print ...
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
.end fn
.globl __start
__start:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
.data
.align 3
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF xgot reloc n32
-#as: -n32 -KPIC -xgot
+#as: -march=from-abi -n32 -KPIC -xgot
#source: elf-rel-got-n32.s
.*: +file format elf32-n.*mips.*
000005f0 <fn\+0x5f0> 10000003 b 00000600 <fn2>
000005f4 <fn\+0x5f4> 00000000 nop
\.\.\.
+ \.\.\.
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF xgot reloc n64
-#as: -64 -KPIC -xgot
+#as: -march=from-abi -64 -KPIC -xgot
#source: elf-rel-got-n64.s
.*: +file format elf64-.*mips.*
00000000000005f0 <fn\+0x5f0> 10000003 b 0000000000000600 <fn2>
00000000000005f4 <fn\+0x5f4> 00000000 nop
\.\.\.
+ \.\.\.
#readelf: --relocs
-#as: -mabi=n32 -KPIC
+#as: -march=from-abi -mabi=n32 -KPIC
Relocation section '\.rela\.text' at offset .* contains 4 entries:
Offset Info Type Sym.Value Sym. Name \+ Addend
.*: R_MIPS_SUB \*ABS\*
.*: R_MIPS_LO16 \*ABS\*
.*: 0384e02d daddu \$28,\$28,\$4
+ \.\.\.
foo:
.cpsetup $4,$5,foo
.end foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
.*: R_MIPS_SUB \*ABS\*
.*: R_MIPS_LO16 \*ABS\*
.*: 0384e02d daddu \$28,\$28,\$4
+ \.\.\.
.*: R_MIPS_HI16 __gnu_local_gp
.*: 279c0000 addiu \$28,\$28,0
.*: R_MIPS_LO16 __gnu_local_gp
-.*: 00000000 nop
+ \.\.\.
#source: elf-rel28.s
-#as: -n32
+#as: -march=from-abi -n32
#objdump: -dr
#name: MIPS ELF reloc 28 (n32)
.*: R_MIPS_TLS_TPREL_LO16 bar
.*: fc840000 sd a0,0\(a0\)
.*: R_MIPS_TLS_GOTTPREL bar
- ...
+ \.\.\.
#source: elf-rel28.s
-#as: -64
+#as: -march=from-abi -64
#objdump: -dr
#name: MIPS ELF reloc 28 (n64)
sd $4,%tprel_lo(bar)($4)
sd $4,%gottprel(bar)($4)
.end foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF NewABI jal
-#as: -n32 -KPIC -xgot
+#as: -march=from-abi -n32 -KPIC -xgot
.*: +file format elf32-n.*mips.*
#objdump: -d
-#as: -KPIC -64
+#as: -march=from-abi -KPIC -64
#name: MIPS ld-st-la constants (ABI n64, shared)
#source: ldstla-n64.s
#objdump: -dr
-#as: -64 -msym32 -G8 -EB
+#as: -march=from-abi -64 -msym32 -G8 -EB
#name: MIPS ld-st-la with sym32
#source: ldstla-sym32.s
#objdump: -d
-#as: -64
+#as: -march=from-abi -64
#name: MIPS ld-st-la constants (ABI n64)
#source: ldstla-n64.s
-#as: -n32 -KPIC
+#as: -march=from-abi -n32 -KPIC
#source: macro-warn-1.s
#stderr: macro-warn-1-n32.l
#objdump: -p
-#as: -n32 -KPIC
+#as: -march=from-abi -n32 -KPIC
#source: macro-warn-2.s
#objdump: -p
#pass
set ecoff [expr [istarget *-*-ecoff*] || [istarget *-*-ultrix*] || [istarget *-*-irix\[1-4\]*] ]
set aout [expr [istarget *-*-bsd*] || [istarget *-*-openbsd*] ]
set addr32 [expr [istarget mipstx39*-*-*] || [istarget mips-*-linux*] || [istarget mipsel-*-linux*] || [istarget mips*-*-ecoff]]
- set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]]
+ set has_newabi [expr [istarget *-*-irix6*] || [istarget mips*-*-linux*] || [istarget mips*-sde-elf*]]
set no_mips16 [expr !$elf]
set no_micromips [expr !$elf]
run_dump_test_arches "branch-misc-2pic-64" [mips_arch_list_matching mips3]
run_dump_test "branch-misc-3"
run_dump_test "branch-swap"
+
+ if $elf {
+ # Sweep a range of branch offsets so that it hits a position where
+ # it is at the beginning of a frag and then swapped with a 16-bit
+ # instruction from the preceding frag. The offset will be somewhere
+ # close below 4096 as this is the default obstack size limit that
+ # we use and some space will have been already consumed. The exact
+ # amount depends on the host's programming model.
+ for { set count 960 } { $count <= 1024 } { incr count } {
+ run_list_test "branch-swap-2" "--defsym count=$count" \
+ "MIPS branch swapping ($count)"
+ }
+ }
+
run_dump_test "div"
if { !$addr32 } {
-#as: -n32
+#as: -march=from-abi -n32
#objdump: -Dr --prefix-addresses
#name: n32 consecutive unrelated relocations
.text
.long .
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
+
.data
.long .+4
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
+2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (mips_opcode): Add the exclusions field.
+ (OPCODE_IS_MEMBER): Remove macro.
+ (cpu_is_member): New inline function.
+ (opcode_is_member): Likewise.
+
2012-07-31 Chao-Ying Fu <fu@mips.com>
Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
#ifndef _MIPS_H_
#define _MIPS_H_
+#include "bfd.h"
+
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
instruction, use the expression
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
+ /* A collection of bits describing the instruction sets of which this
+ instruction or macro is not a member. */
+ unsigned long exclusions;
};
/* These are the characters which may appear in the args field of an
#define CPU_OCTEON2 6502
#define CPU_XLR 887682 /* decimal 'XLR' */
+/* Return true if the given CPU is included in INSN_* mask MASK. */
+
+static inline bfd_boolean
+cpu_is_member (int cpu, unsigned int mask)
+{
+ switch (cpu)
+ {
+ case CPU_R4650:
+ case CPU_RM7000:
+ case CPU_RM9000:
+ return (mask & INSN_4650) != 0;
+
+ case CPU_R4010:
+ return (mask & INSN_4010) != 0;
+
+ case CPU_VR4100:
+ return (mask & INSN_4100) != 0;
+
+ case CPU_R3900:
+ return (mask & INSN_3900) != 0;
+
+ case CPU_R10000:
+ case CPU_R12000:
+ case CPU_R14000:
+ case CPU_R16000:
+ return (mask & INSN_10000) != 0;
+
+ case CPU_SB1:
+ return (mask & INSN_SB1) != 0;
+
+ case CPU_R4111:
+ return (mask & INSN_4111) != 0;
+
+ case CPU_VR4120:
+ return (mask & INSN_4120) != 0;
+
+ case CPU_VR5400:
+ return (mask & INSN_5400) != 0;
+
+ case CPU_VR5500:
+ return (mask & INSN_5500) != 0;
+
+ case CPU_LOONGSON_2E:
+ return (mask & INSN_LOONGSON_2E) != 0;
+
+ case CPU_LOONGSON_2F:
+ return (mask & INSN_LOONGSON_2F) != 0;
+
+ case CPU_LOONGSON_3A:
+ return (mask & INSN_LOONGSON_3A) != 0;
+
+ case CPU_OCTEON:
+ return (mask & INSN_OCTEON) != 0;
+
+ case CPU_OCTEONP:
+ return (mask & INSN_OCTEONP) != 0;
+
+ case CPU_OCTEON2:
+ return (mask & INSN_OCTEON2) != 0;
+
+ case CPU_XLR:
+ return (mask & INSN_XLR) != 0;
+
+ default:
+ return FALSE;
+ }
+}
+
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
- test, or zero if no CPU specific ISA test is desired. */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu) \
- (((isa & INSN_ISA_MASK) != 0 \
- && ((insn)->membership & INSN_ISA_MASK) != 0 \
- && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
- (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
- || ((isa & ~INSN_ISA_MASK) \
- & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
- || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
- || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
- || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
- || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
- || cpu == CPU_R16000) \
- && ((insn)->membership & INSN_10000) != 0) \
- || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
- || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
- || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
- || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
- || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
- || (cpu == CPU_LOONGSON_2E \
- && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
- || (cpu == CPU_LOONGSON_2F \
- && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
- || (cpu == CPU_LOONGSON_3A \
- && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
- || (cpu == CPU_OCTEON \
- && ((insn)->membership & INSN_OCTEON) != 0) \
- || (cpu == CPU_OCTEONP \
- && ((insn)->membership & INSN_OCTEONP) != 0) \
- || (cpu == CPU_OCTEON2 \
- && ((insn)->membership & INSN_OCTEON2) != 0) \
- || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
- || 0) /* Please keep this term for easier source merging. */
+ test, or zero if no CPU specific ISA test is desired. Return true
+ if instruction INSN is available to the given ISA and CPU. */
+
+static inline bfd_boolean
+opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
+{
+ if (!cpu_is_member (cpu, insn->exclusions))
+ {
+ /* Test for ISA level compatibility. */
+ if ((isa & INSN_ISA_MASK) != 0
+ && (insn->membership & INSN_ISA_MASK) != 0
+ && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
+ >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
+ return TRUE;
+
+ /* Test for ASE compatibility. */
+ if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
+ return TRUE;
+
+ /* Test for processor-specific extensions. */
+ if (cpu_is_member (cpu, insn->membership))
+ return TRUE;
+ }
+ return FALSE;
+}
/* This is a list of macro expanded instructions.
+ * emulparams/elf32bmip.sh: Make _gp hidden.
+ * emulparams/elf32bmipn32-defs.sh: Likewise.
+ * emulparams/elf32mipswindiss.sh: Likewise.
+ * scripttempl/mips.sc: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ldexp.h (etree_union): Add defsym member to the assign member
+ structure.
+ (exp_assign): Add hidden argument to prototype.
+ * ldexp.c (exp_fold_tree_1): Use the defsym member to handle
+ --defsym symbols.
+ (exp_assop): Add defsym argument, initialize the defsym member
+ of the assign structure.
+ (exp_assign): Handle hidden symbols.
+ (exp_defsym): Update to use the defsym argument to exp_assop.
+ (exp_provide): Update to handle the defsym argument to exp_assop.
+ * ldlex.l (HIDDEN): New token.
+ * ldgram.y (HIDDEN): Likewise.
+ (assignment, section): Update calls to exp_assign.
+ * ldctor.c (ldctor_build_sets): Likewise.
+ * mri.c (mri_format): Likewise.
+ * ldlang.c (lang_insert_orphan, lang_leave_overlay): Likewise.
+ (open_input_bfds): Remove --defsym symbols special case.
+ * emultempl/beos.em (gld_${EMULATION_NAME}_set_symbols): Update
+ call to exp_assign.
+ * emultempl/pe.em (gld_${EMULATION_NAME}_set_symbols): Likewise.
+ * emultempl/pep.em (gld_${EMULATION_NAME}_set_symbols): Likewise.
+ * emultempl/spuelf.em (spu_place_special_section): Likewise.
+ * emultempl/xtensaelf.em (ld_xtensa_insert_page_offsets):
+ Likewise.
+ * ld.texinfo (Assigning Values to Symbols): Add HIDDEN.
+ (HIDDEN): New subsection.
+
2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
# of .got.
OTHER_GOT_SYMBOLS='
. = .;
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
'
# .got.plt is only used for the PLT psABI extension. It should not be
# included in the .sdata block with .got, as there is no need to access
# of .got.
OTHER_GOT_SYMBOLS='
. = .;
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
'
# .got.plt is only used for the PLT psABI extension. It should not be
# included in the .sdata block with .got, as there is no need to access
# the Diab linker.
TEXT_START_ADDR=0x100000
DATA_START_SYMBOLS='__DATA_ROM = .; __DATA_RAM = .;'
-SDATA_START_SYMBOLS='_SDA_BASE_ = .; _gp = . + 0x7ff0;'
+SDATA_START_SYMBOLS='_SDA_BASE_ = .; HIDDEN (_gp = . + 0x7ff0);'
SDATA2_START_SYMBOLS='_SDA2_BASE_ = .;'
EXECUTABLE_SYMBOLS='__HEAP_START = .; __SP_INIT = 0x800000; __SP_END = __SP_INIT - 0x20000; __HEAP_END = __SP_END; __DATA_END = _edata; __BSS_START = __bss_start; __BSS_END = _end; __HEAP_START = _end;'
for (j = 0; init[j].ptr; j++)
{
long val = init[j].value;
- lang_add_assignment (exp_assign (init[j].symbol, exp_intop (val)));
+ lang_add_assignment (exp_assign (init[j].symbol, exp_intop (val),
+ FALSE));
if (init[j].size == sizeof(short))
*(short *)init[j].ptr = val;
else if (init[j].size == sizeof(int))
lang_assignment_statement_type *rv;
rv = lang_add_assignment (exp_assign (GET_INIT_SYMBOL_NAME (j),
- exp_intop (val)));
+ exp_intop (val), FALSE));
if (init[j].size == sizeof (short))
*(short *) init[j].ptr = val;
else if (init[j].size == sizeof (int))
= pe_def_file->base_address;
init[IMAGEBASEOFF].inited = 1;
if (image_base_statement)
- image_base_statement->exp = exp_assign ("__image_base__",
- exp_intop (pe.ImageBase));
+ image_base_statement->exp
+ = exp_assign ("__image_base__", exp_intop (pe.ImageBase),
+ FALSE);
}
if (pe_def_file->stack_reserve != -1
lang_assignment_statement_type *rv;
rv = lang_add_assignment (exp_assign (GET_INIT_SYMBOL_NAME (j),
- exp_intop (val)));
+ exp_intop (val), FALSE));
if (init[j].size == sizeof (short))
*(short *) init[j].ptr = (short) val;
else if (init[j].size == sizeof (int))
= pep_def_file->base_address;
init[IMAGEBASEOFF].inited = 1;
if (image_base_statement)
- image_base_statement->exp = exp_assign ("__image_base__",
- exp_intop (pep.ImageBase));
+ image_base_statement->exp
+ = exp_assign ("__image_base__", exp_intop (pep.ImageBase),
+ FALSE);
}
if (pep_def_file->stack_reserve != -1
push_stat_ptr (&os->children);
e_size = exp_intop (params.line_size - s->size);
- lang_add_assignment (exp_assign (".", e_size));
+ lang_add_assignment (exp_assign (".", e_size, FALSE));
pop_stat_ptr ();
}
lang_add_section (&os->children, s, NULL, os);
etree_type *name_op = exp_nameop (NAME, ".");
etree_type *addend_op = exp_intop (1 << xtensa_page_power);
etree_type *add_op = exp_binop ('+', name_op, addend_op);
- etree_type *assign_op = exp_assign (".", add_op);
+ etree_type *assign_op = exp_assign (".", add_op, FALSE);
lang_assignment_statement_type *assign_stmt;
lang_statement_union_type *assign_union;
@menu
* Simple Assignments:: Simple Assignments
+* HIDDEN:: HIDDEN
* PROVIDE:: PROVIDE
* PROVIDE_HIDDEN:: PROVIDE_HIDDEN
* Source Code Reference:: How to use a linker script defined symbol in source code
defined as the address following the @samp{.text} output section aligned
upward to a 4 byte boundary.
+@node HIDDEN
+@subsection HIDDEN
+@cindex HIDDEN
+For ELF targeted ports, define a symbol that will be hidden and won't be
+exported. The syntax is @code{HIDDEN(@var{symbol} = @var{expression})}.
+
+Here is the example from @ref{Simple Assignments}, rewritten to use
+@code{HIDDEN}:
+
+@smallexample
+HIDDEN(floating_point = 0);
+SECTIONS
+@{
+ .text :
+ @{
+ *(.text)
+ HIDDEN(_etext = .);
+ @}
+ HIDDEN(_bdata = (. + 3) & ~ 3);
+ .data : @{ *(.data) @}
+@}
+@end smallexample
+@noindent
+In this case none of the three symbols will be visible outside this module.
+
@node PROVIDE
@subsection PROVIDE
@cindex PROVIDE
lang_add_assignment (exp_assign (".",
exp_unop (ALIGN_K,
- exp_intop (reloc_size))));
+ exp_intop (reloc_size)),
+ FALSE));
lang_add_assignment (exp_assign (p->h->root.string,
- exp_nameop (NAME, ".")));
+ exp_nameop (NAME, "."),
+ FALSE));
lang_add_data (size, exp_intop (p->count));
for (e = p->elements; e != NULL; e = e->next)
if (expld.result.valid_p
|| (expld.phase <= lang_mark_phase_enum
&& tree->type.node_class == etree_assign
- && tree->assign.hidden))
+ && tree->assign.defsym))
{
if (h == NULL)
{
exp_assop (const char *dst,
etree_type *src,
enum node_tree_enum class,
+ bfd_boolean defsym,
bfd_boolean hidden)
{
etree_type *n;
n->assign.type.node_class = class;
n->assign.src = src;
n->assign.dst = dst;
+ n->assign.defsym = defsym;
n->assign.hidden = hidden;
return n;
}
+/* Handle linker script assignments and HIDDEN. */
+
etree_type *
-exp_assign (const char *dst, etree_type *src)
+exp_assign (const char *dst, etree_type *src, bfd_boolean hidden)
{
- return exp_assop (dst, src, etree_assign, FALSE);
+ return exp_assop (dst, src, etree_assign, FALSE, hidden);
}
+/* Handle --defsym command-line option. */
+
etree_type *
exp_defsym (const char *dst, etree_type *src)
{
- return exp_assop (dst, src, etree_assign, TRUE);
+ return exp_assop (dst, src, etree_assign, TRUE, FALSE);
}
/* Handle PROVIDE. */
etree_type *
exp_provide (const char *dst, etree_type *src, bfd_boolean hidden)
{
- return exp_assop (dst, src, etree_provide, hidden);
+ return exp_assop (dst, src, etree_provide, FALSE, hidden);
}
/* Handle ASSERT. */
node_type type;
const char *dst;
union etree_union *src;
+ bfd_boolean defsym;
bfd_boolean hidden;
} assign;
struct {
etree_type *exp_nameop
(int, const char *);
etree_type *exp_assign
- (const char *, etree_type *);
+ (const char *, etree_type *, bfd_boolean);
etree_type *exp_defsym
(const char *, etree_type *);
etree_type *exp_provide
%token STARTUP HLL SYSLIB FLOAT NOFLOAT NOCROSSREFS
%token ORIGIN FILL
%token LENGTH CREATE_OBJECT_SYMBOLS INPUT GROUP OUTPUT CONSTRUCTORS
-%token ALIGNMOD AT SUBALIGN PROVIDE PROVIDE_HIDDEN AS_NEEDED
+%token ALIGNMOD AT SUBALIGN HIDDEN PROVIDE PROVIDE_HIDDEN AS_NEEDED
%type <token> assign_op atype attributes_opt sect_constraint
%type <name> filename
%token CHIP LIST SECT ABSOLUTE LOAD NEWLINE ENDWORD ORDER NAMEWORD ASSERT_K
assignment:
NAME '=' mustbe_exp
{
- lang_add_assignment (exp_assign ($1, $3));
+ lang_add_assignment (exp_assign ($1, $3, FALSE));
}
| NAME assign_op mustbe_exp
{
exp_binop ($2,
exp_nameop (NAME,
$1),
- $3)));
+ $3), FALSE));
+ }
+ | HIDDEN '(' NAME '=' mustbe_exp ')'
+ {
+ lang_add_assignment (exp_assign ($3, $5, TRUE));
}
| PROVIDE '(' NAME '=' mustbe_exp ')'
{
opt_exp_with_type
{
ldlex_popstate ();
- lang_add_assignment (exp_assign (".", $3));
+ lang_add_assignment (exp_assign (".", $3, FALSE));
}
'{' sec_or_group_p1 '}'
| INCLUDE filename
#endif
break;
case lang_assignment_statement_enum:
- if (s->assignment_statement.exp->assign.hidden)
+ if (s->assignment_statement.exp->assign.defsym)
/* This is from a --defsym on the command line. */
exp_fold_tree_no_dot (s->assignment_statement.exp);
break;
{
overlay_list->os->update_dot = 1;
overlay_list->os->update_dot_tree
- = exp_assign (".", exp_binop ('+', overlay_vma, overlay_max));
+ = exp_assign (".", exp_binop ('+', overlay_vma, overlay_max), FALSE);
}
l = overlay_list;
<BOTH,SCRIPT>"PHDRS" { RTOKEN (PHDRS); }
<EXPRESSION,BOTH,SCRIPT>"AT" { RTOKEN(AT);}
<EXPRESSION,BOTH,SCRIPT>"SUBALIGN" { RTOKEN(SUBALIGN);}
+<EXPRESSION,BOTH,SCRIPT>"HIDDEN" { RTOKEN(HIDDEN); }
<EXPRESSION,BOTH,SCRIPT>"PROVIDE" { RTOKEN(PROVIDE); }
<EXPRESSION,BOTH,SCRIPT>"PROVIDE_HIDDEN" { RTOKEN(PROVIDE_HIDDEN); }
<EXPRESSION,BOTH,SCRIPT>"KEEP" { RTOKEN(KEEP); }
void
mri_public (const char *name, etree_type *exp)
{
- lang_add_assignment (exp_assign (name, exp));
+ lang_add_assignment (exp_assign (name, exp, FALSE));
}
void
*(.data)
${CONSTRUCTING+CONSTRUCTORS}
}
- ${RELOCATING+ _gp = ALIGN(16) + 0x8000;}
+ ${RELOCATING+ HIDDEN (_gp = ALIGN (16) + 0x8000);}
.lit8 : {
*(.lit8)
}
+2012-08-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-elf/export-class.sd: New test.
+ * ld-elf/export-class.vd: New test.
+ * ld-elf/export-class-def.s: New test source.
+ * ld-elf/export-class-dep.s: New test source.
+ * ld-elf/export-class-lib.s: New test source.
+ * ld-elf/export-class-ref.s: New test source.
+ * ld-elf/export-class-lib.ver: New test version script.
+ * ld-elf/export-class.exp: New test script.
+ * ld-arm/arm-export-class.rd: New test.
+ * ld-arm/arm-export-class.xd: New test.
+ * ld-arm/export-class.exp: New test script.
+ * ld-i386/i386-export-class.rd: New test.
+ * ld-i386/i386-export-class.xd: New test.
+ * ld-i386/export-class.exp: New test script.
+ * ld-mips-elf/mips-32-export-class.rd: New test.
+ * ld-mips-elf/mips-32-export-class.xd: New test.
+ * ld-mips-elf/mips-64-export-class.rd: New test.
+ * ld-mips-elf/mips-64-export-class.xd: New test.
+ * ld-mips-elf/export-class.exp: New test script.
+ * ld-powerpc/powerpc-32-export-class.rd: New test.
+ * ld-powerpc/powerpc-32-export-class.xd: New test.
+ * ld-powerpc/powerpc-64-export-class.rd: New test.
+ * ld-powerpc/powerpc-64-export-class.xd: New test.
+ * ld-powerpc/export-class.exp: New test script.
+ * ld-x86-64/x86-64-64-export-class.rd: New test.
+ * ld-x86-64/x86-64-x32-export-class.rd: New test.
+ * ld-x86-64/export-class.exp: New test script.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/export-class-call16-o32.dd: New test.
+ * ld-mips-elf/export-class-call16-o32-irix.dd: New test.
+ * ld-mips-elf/export-class-call16-o32.gd: New test.
+ * ld-mips-elf/export-class-call16-n32.dd: New test.
+ * ld-mips-elf/export-class-call16-n32.gd: New test.
+ * ld-mips-elf/export-class-call16-n64.dd: New test.
+ * ld-mips-elf/export-class-call16-n64.gd: New test.
+ * ld-mips-elf/export-class-call16-def.s: New test source.
+ * ld-mips-elf/export-class-call16-o32.s: New test source.
+ * ld-mips-elf/export-class-call16-n32.s: New test source.
+ * ld-mips-elf/export-class-call16-n64.s: New test source.
+ * ld-mips-elf/export-class-call16.ld: New test linker script.
+ * ld-mips-elf/mips-elf.exp: Run the new tests.
+
+ * ld-mips-elf/dyn-sec64.ld: Use HIDDEN to define _gp.
+ * ld-mips-elf/eh-frame5.ld: Likewise.
+ * ld-mips-elf/got-dump-1.ld: Likewise.
+ * ld-mips-elf/got-dump-2.ld: Likewise.
+ * ld-mips-elf/got-page-1.ld: Likewise.
+ * ld-mips-elf/mips-dyn.ld: Likewise.
+ * ld-mips-elf/mips-lib.ld: Likewise.
+ * ld-mips-elf/mips16-pic-1.ld: Likewise.
+ * ld-mips-elf/no-shared-1.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-1.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3a.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-5b.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6.ld: Likewise.
+ * ld-mips-elf/reloc-2.ld: Likewise.
+ * ld-mips-elf/reloc-estimate-1.ld: Likewise.
+ * ld-mips-elf/stub-dynsym-1.ld: Likewise.
+ * ld-mips-elf/tls-hidden3.ld: Likewise.
+ * ld-mips-elf/mips16-pic-2.ad: Update accordingly.
+ * ld-mips-elf/pic-and-nonpic-3b.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-5b.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n32.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n64.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-o32.ad: Likewise.
+ * ld-mips-elf/eh-frame5.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32-1.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32-2.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32-3.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32.d: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3a.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise.
+ * ld-mips-elf/tls-multi-got-1.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32-1.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32-2.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32-3.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32.got: Likewise.
+ * ld-mips-elf/tlslib-o32-ver.got: Likewise.
+ * ld-mips-elf/tlslib-o32.got: Likewise.
+ * ld-mips-elf/mips16-pic-2.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-1.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-5b.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n32.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n64.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-o32.nd: Likewise.
+ * ld-mips-elf/tls-multi-got-1.r: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.rd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.rd: Likewise.
+ * ld-mips-elf/mips-elf.exp: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/gp-hidden.rd: New test.
+ * ld-mips-elf/gp-hidden.sd: New test.
+ * ld-mips-elf/gp-hidden-lib.rd: New test.
+ * ld-mips-elf/gp-hidden-ver.rd: New test.
+ * ld-mips-elf/gp-hidden-64.rd: New test.
+ * ld-mips-elf/gp-hidden-lib-64.rd: New test.
+ * ld-mips-elf/gp-hidden-ver-64.rd: New test.
+ * ld-mips-elf/gp-hidden.s: New test source.
+ * ld-mips-elf/gp-hidden-lib.s: New test source.
+ * ld-mips-elf/gp-hidden-ver.s: New test source.
+ * ld-mips-elf/gp-hidden-ver.ver: New test version script.
+ * ld-mips-elf/mips-elf.exp: Run the new tests.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/mips-elf.exp: Set has_newabi for all Linux targets.
+ Adjust abi_asflags for targets that do not infer the ISA from the
+ ABI.
+ * ld-mips-elf/eh-frame1-n32.d: Adjust for targets that do not
+ infer the ISA from the ABI.
+ * ld-mips-elf/eh-frame1-n64.d: Likewise.
+ * ld-mips-elf/eh-frame2-n32.d: Likewise.
+ * ld-mips-elf/eh-frame2-n64.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n32-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n32.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n64-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n64-linux.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n64.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n32.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n64.d: Likewise.
+ * ld-mips-elf/emit-relocs-1.d: Likewise.
+ * ld-mips-elf/got-page-2.d: Likewise.
+ * ld-mips-elf/no-shared-1-n32.d: Likewise.
+ * ld-mips-elf/no-shared-1-n64.d: Likewise.
+ * ld-mips-elf/rel32-n32.d: Likewise.
+ * ld-mips-elf/rel64.d: Likewise.
+ * ld-mips-elf/relax-jalr-n32-shared.d: Likewise.
+ * ld-mips-elf/relax-jalr-n32.d: Likewise.
+ * ld-mips-elf/relax-jalr-n64-shared.d: Likewise.
+ * ld-mips-elf/relax-jalr-n64.d: Likewise.
+ * ld-mips-elf/reloc-1-n32.d: Likewise.
+ * ld-mips-elf/reloc-1-n64.d: Likewise.
+ * ld-mips-elf/textrel-1.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/reloc-1-n32.d: Add -EB to GAS flags.
+ * ld-mips-elf/mips-elf.exp: Update GAS flags in reloc test 6.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * lib/ld-lib.exp (run_dump_test): Implement the EXTRA_OPTIONS
+ argument and the "dump" keyword.
+ * ld-mips-elf/emit-relocs-1a.s: Make section alignment uniform
+ across targets.
+ * ld-mips-elf/emit-relocs-1b.s: Likewise.
+ * ld-mips-elf/jalbal.s: Adjust padding.
+ * ld-mips-elf/elf-rel-got-n32-embed.d: New test.
+ * ld-mips-elf/elf-rel-got-n64-embed.d: New test.
+ * ld-mips-elf/elf-rel-xgot-n32-embed.d: New test.
+ * ld-mips-elf/elf-rel-xgot-n64-embed.d: New test.
+ * ld-mips-elf/elf-rel-got-n32.d: Remove -melf32btsmipn32.
+ * ld-mips-elf/elf-rel-got-n64.d: Remove -melf64btsmip. Adjust
+ output.
+ * ld-mips-elf/elf-rel-got-n64-linux.d: Remove -melf64btsmip.
+ * ld-mips-elf/elf-rel-xgot-n32.d: Remove -melf32btsmipn32.
+ Adjust output.
+ * ld-mips-elf/elf-rel-xgot-n64.d: Remove -melf64btsmip. Adjust
+ output.
+ * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
+ * ld-mips-elf/reloc-1-n64.d: Remove -melf64btsmip.
+ * ld-mips-elf/mips-elf.exp: Set has_newabi for mips*-sde-elf*
+ too. Move tool flags from o32_as_flags and o32_ld_flags
+ variables into abi_asflags and abi_ldflags arrays. Adjust test
+ cases run to use them. Run the new tests.
+
+ * ld-mips-elf/rel32-o32.d: Adjust section VMAs after the removal
+ of _gp from the global scope.
+ * ld-mips-elf/rel32-n32.d: Likewise.
+ * ld-mips-elf/rel64.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * lib/ld-lib.exp (at_least_gcc_version): Accept more version
+ number formats; avoid throwing exceptions in any case.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/mode-change-error-1.d: Update the error message.
+
2012-08-05 Maciej W. Rozycki <macro@linux-mips.org>
* ld-vax-elf: New directory.
.MIPS.stubs : { *(.MIPS.stubs) }
. = 0x1235000000000;
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
.data : { *(.data) }
}
#name: MIPS eh-frame 1, n32
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -n32 --defsym alignment=2 --defsym fill=0x40
+#as: -march=from-abi -EB -n32 --defsym alignment=2 --defsym fill=0x40
#readelf: --relocs -wf
#ld: -shared -melf32btsmipn32 -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
#name: MIPS eh-frame 1, n64
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -64 --defsym alignment=3 --defsym fill=0x40
+#as: -march=from-abi -EB -64 --defsym alignment=3 --defsym fill=0x40
#readelf: --relocs -wf
#ld: -shared -melf64btsmip -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
#name: MIPS eh-frame 2, n32
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -n32 --defsym alignment=2 --defsym fill=0
+#as: -march=from-abi -EB -n32 --defsym alignment=2 --defsym fill=0
#readelf: --relocs -wf
#ld: -shared -melf32btsmipn32 -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
#name: MIPS eh-frame 2, n64
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -64 --defsym alignment=3 --defsym fill=0
+#as: -march=from-abi -EB -64 --defsym alignment=3 --defsym fill=0
#readelf: --relocs -wf
#ld: -shared -melf64btsmip -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
-Relocation section '.rel.dyn' at offset 0x101f0 contains 8 entries:
+Relocation section '.rel.dyn' at offset 0x101dc contains 8 entries:
Offset Info Type Sym.Value Sym. Name
00000000 .* R_MIPS_NONE *
#
. = 0x10000;
.data : { *(.data) }
. = 0x10400;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
}
#name: MIPS ELF got reloc n32
-#as: -EB -n32 -KPIC
+#as: -march=from-abi -EB -n32 -KPIC
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
-#ld: -melf32btsmipn32
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf32-n.*mips.*
#name: MIPS ELF got reloc n64
-#as: -EB -64 -KPIC
+#as: -march=from-abi -EB -64 -KPIC
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
#name: MIPS ELF got reloc n64
-#as: -EB -64 -KPIC
+#as: -march=from-abi -EB -64 -KPIC
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
Disassembly of section \.MIPS\.options:
-00000000100000b0 <\.MIPS\.options>:
- 100000b0: 01280000 .*
- 100000b4: 00000000 .*
- 100000b8: 92020022 .*
+00000000100000e8 <\.MIPS\.options>:
+ 100000e8: 01280000 .*
+ 100000ec: 00000000 .*
+ 100000f0: 92020022 .*
\.\.\.
- 100000d4: 101085d0 .*
+ 1000010c: 10018600 .*
Disassembly of section \.text:
-00000000100000e0 <fn>:
- 100000e0: df8580b8 ld a1,-32584\(gp\)
- 100000e4: df8580b8 ld a1,-32584\(gp\)
- 100000e8: 64a5000c daddiu a1,a1,12
- 100000ec: df8580b8 ld a1,-32584\(gp\)
- 100000f0: 3c010002 lui at,0x2
- 100000f4: 6421e240 daddiu at,at,-7616
- 100000f8: 00a1282d daddu a1,a1,at
- 100000fc: df8580b8 ld a1,-32584\(gp\)
- 10000100: 00b1282d daddu a1,a1,s1
- 10000104: df8580b8 ld a1,-32584\(gp\)
- 10000108: 64a5000c daddiu a1,a1,12
- 1000010c: 00b1282d daddu a1,a1,s1
- 10000110: df8580b8 ld a1,-32584\(gp\)
- 10000114: 3c010002 lui at,0x2
- 10000118: 6421e240 daddiu at,at,-7616
- 1000011c: 00a1282d daddu a1,a1,at
- 10000120: 00b1282d daddu a1,a1,s1
- 10000124: df8580b8 ld a1,-32584\(gp\)
- 10000128: dca50000 ld a1,0\(a1\)
- 1000012c: df8580b8 ld a1,-32584\(gp\)
- 10000130: dca5000c ld a1,12\(a1\)
- 10000134: df8580b8 ld a1,-32584\(gp\)
- 10000138: 00b1282d daddu a1,a1,s1
- 1000013c: dca50000 ld a1,0\(a1\)
- 10000140: df8580b8 ld a1,-32584\(gp\)
- 10000144: 00b1282d daddu a1,a1,s1
- 10000148: dca5000c ld a1,12\(a1\)
- 1000014c: df8180b8 ld at,-32584\(gp\)
- 10000150: 0025082d daddu at,at,a1
- 10000154: dc250022 ld a1,34\(at\)
- 10000158: df8180b8 ld at,-32584\(gp\)
- 1000015c: 0025082d daddu at,at,a1
- 10000160: fc250038 sd a1,56\(at\)
- 10000164: df8180b8 ld at,-32584\(gp\)
- 10000168: 88250000 lwl a1,0\(at\)
- 1000016c: 98250003 lwr a1,3\(at\)
- 10000170: df8180b8 ld at,-32584\(gp\)
- 10000174: 6421000c daddiu at,at,12
- 10000178: 88250000 lwl a1,0\(at\)
- 1000017c: 98250003 lwr a1,3\(at\)
- 10000180: df8180b8 ld at,-32584\(gp\)
- 10000184: 0031082d daddu at,at,s1
- 10000188: 88250000 lwl a1,0\(at\)
- 1000018c: 98250003 lwr a1,3\(at\)
- 10000190: df8180b8 ld at,-32584\(gp\)
- 10000194: 6421000c daddiu at,at,12
- 10000198: 0031082d daddu at,at,s1
- 1000019c: 88250000 lwl a1,0\(at\)
- 100001a0: 98250003 lwr a1,3\(at\)
- 100001a4: df8180b8 ld at,-32584\(gp\)
- 100001a8: 64210022 daddiu at,at,34
- 100001ac: 0025082d daddu at,at,a1
- 100001b0: 88250000 lwl a1,0\(at\)
- 100001b4: 98250003 lwr a1,3\(at\)
- 100001b8: df8180b8 ld at,-32584\(gp\)
- 100001bc: 64210038 daddiu at,at,56
- 100001c0: 0025082d daddu at,at,a1
- 100001c4: a8250000 swl a1,0\(at\)
- 100001c8: b8250003 swr a1,3\(at\)
- 100001cc: df858020 ld a1,-32736\(gp\)
- 100001d0: df858028 ld a1,-32728\(gp\)
- 100001d4: df858030 ld a1,-32720\(gp\)
- 100001d8: df858020 ld a1,-32736\(gp\)
- 100001dc: 00b1282d daddu a1,a1,s1
- 100001e0: df858028 ld a1,-32728\(gp\)
- 100001e4: 00b1282d daddu a1,a1,s1
- 100001e8: df858030 ld a1,-32720\(gp\)
- 100001ec: 00b1282d daddu a1,a1,s1
- 100001f0: df858038 ld a1,-32712\(gp\)
- 100001f4: dca5052c ld a1,1324\(a1\)
- 100001f8: df858038 ld a1,-32712\(gp\)
- 100001fc: dca50538 ld a1,1336\(a1\)
- 10000200: df858038 ld a1,-32712\(gp\)
- 10000204: 00b1282d daddu a1,a1,s1
- 10000208: dca5052c ld a1,1324\(a1\)
- 1000020c: df858038 ld a1,-32712\(gp\)
- 10000210: 00b1282d daddu a1,a1,s1
- 10000214: dca50538 ld a1,1336\(a1\)
- 10000218: df818038 ld at,-32712\(gp\)
- 1000021c: 0025082d daddu at,at,a1
- 10000220: dc25054e ld a1,1358\(at\)
- 10000224: df818038 ld at,-32712\(gp\)
- 10000228: 0025082d daddu at,at,a1
- 1000022c: fc250564 sd a1,1380\(at\)
- 10000230: df818020 ld at,-32736\(gp\)
- 10000234: 88250000 lwl a1,0\(at\)
- 10000238: 98250003 lwr a1,3\(at\)
- 1000023c: df818028 ld at,-32728\(gp\)
- 10000240: 88250000 lwl a1,0\(at\)
- 10000244: 98250003 lwr a1,3\(at\)
- 10000248: df818020 ld at,-32736\(gp\)
- 1000024c: 0031082d daddu at,at,s1
- 10000250: 88250000 lwl a1,0\(at\)
- 10000254: 98250003 lwr a1,3\(at\)
- 10000258: df818028 ld at,-32728\(gp\)
- 1000025c: 0031082d daddu at,at,s1
- 10000260: 88250000 lwl a1,0\(at\)
- 10000264: 98250003 lwr a1,3\(at\)
- 10000268: df818040 ld at,-32704\(gp\)
- 1000026c: 0025082d daddu at,at,a1
+0000000010000110 <fn>:
+ 10000110: df858020 ld a1,-32736\(gp\)
+ 10000114: df858020 ld a1,-32736\(gp\)
+ 10000118: 64a5000c daddiu a1,a1,12
+ 1000011c: df858020 ld a1,-32736\(gp\)
+ 10000120: 3c010001 lui at,0x1
+ 10000124: 3421e240 ori at,at,0xe240
+ 10000128: 00a1282d daddu a1,a1,at
+ 1000012c: df858020 ld a1,-32736\(gp\)
+ 10000130: 00b1282d daddu a1,a1,s1
+ 10000134: df858020 ld a1,-32736\(gp\)
+ 10000138: 64a5000c daddiu a1,a1,12
+ 1000013c: 00b1282d daddu a1,a1,s1
+ 10000140: df858020 ld a1,-32736\(gp\)
+ 10000144: 3c010001 lui at,0x1
+ 10000148: 3421e240 ori at,at,0xe240
+ 1000014c: 00a1282d daddu a1,a1,at
+ 10000150: 00b1282d daddu a1,a1,s1
+ 10000154: df858028 ld a1,-32728\(gp\)
+ 10000158: dca5055c ld a1,1372\(a1\)
+ 1000015c: df858028 ld a1,-32728\(gp\)
+ 10000160: dca50568 ld a1,1384\(a1\)
+ 10000164: df858028 ld a1,-32728\(gp\)
+ 10000168: 00b1282d daddu a1,a1,s1
+ 1000016c: dca5055c ld a1,1372\(a1\)
+ 10000170: df858028 ld a1,-32728\(gp\)
+ 10000174: 00b1282d daddu a1,a1,s1
+ 10000178: dca50568 ld a1,1384\(a1\)
+ 1000017c: df818028 ld at,-32728\(gp\)
+ 10000180: 0025082d daddu at,at,a1
+ 10000184: dc25057e ld a1,1406\(at\)
+ 10000188: df818028 ld at,-32728\(gp\)
+ 1000018c: 0025082d daddu at,at,a1
+ 10000190: fc250594 sd a1,1428\(at\)
+ 10000194: df818020 ld at,-32736\(gp\)
+ 10000198: 88250000 lwl a1,0\(at\)
+ 1000019c: 98250003 lwr a1,3\(at\)
+ 100001a0: df818020 ld at,-32736\(gp\)
+ 100001a4: 6421000c daddiu at,at,12
+ 100001a8: 88250000 lwl a1,0\(at\)
+ 100001ac: 98250003 lwr a1,3\(at\)
+ 100001b0: df818020 ld at,-32736\(gp\)
+ 100001b4: 0031082d daddu at,at,s1
+ 100001b8: 88250000 lwl a1,0\(at\)
+ 100001bc: 98250003 lwr a1,3\(at\)
+ 100001c0: df818020 ld at,-32736\(gp\)
+ 100001c4: 6421000c daddiu at,at,12
+ 100001c8: 0031082d daddu at,at,s1
+ 100001cc: 88250000 lwl a1,0\(at\)
+ 100001d0: 98250003 lwr a1,3\(at\)
+ 100001d4: df818020 ld at,-32736\(gp\)
+ 100001d8: 64210022 daddiu at,at,34
+ 100001dc: 0025082d daddu at,at,a1
+ 100001e0: 88250000 lwl a1,0\(at\)
+ 100001e4: 98250003 lwr a1,3\(at\)
+ 100001e8: df818020 ld at,-32736\(gp\)
+ 100001ec: 64210038 daddiu at,at,56
+ 100001f0: 0025082d daddu at,at,a1
+ 100001f4: a8250000 swl a1,0\(at\)
+ 100001f8: b8250003 swr a1,3\(at\)
+ 100001fc: df858020 ld a1,-32736\(gp\)
+ 10000200: df858030 ld a1,-32720\(gp\)
+ 10000204: df858038 ld a1,-32712\(gp\)
+ 10000208: df858020 ld a1,-32736\(gp\)
+ 1000020c: 00b1282d daddu a1,a1,s1
+ 10000210: df858030 ld a1,-32720\(gp\)
+ 10000214: 00b1282d daddu a1,a1,s1
+ 10000218: df858038 ld a1,-32712\(gp\)
+ 1000021c: 00b1282d daddu a1,a1,s1
+ 10000220: df858028 ld a1,-32728\(gp\)
+ 10000224: dca5055c ld a1,1372\(a1\)
+ 10000228: df858028 ld a1,-32728\(gp\)
+ 1000022c: dca50568 ld a1,1384\(a1\)
+ 10000230: df858028 ld a1,-32728\(gp\)
+ 10000234: 00b1282d daddu a1,a1,s1
+ 10000238: dca5055c ld a1,1372\(a1\)
+ 1000023c: df858028 ld a1,-32728\(gp\)
+ 10000240: 00b1282d daddu a1,a1,s1
+ 10000244: dca50568 ld a1,1384\(a1\)
+ 10000248: df818028 ld at,-32728\(gp\)
+ 1000024c: 0025082d daddu at,at,a1
+ 10000250: dc25057e ld a1,1406\(at\)
+ 10000254: df818028 ld at,-32728\(gp\)
+ 10000258: 0025082d daddu at,at,a1
+ 1000025c: fc250594 sd a1,1428\(at\)
+ 10000260: df818020 ld at,-32736\(gp\)
+ 10000264: 88250000 lwl a1,0\(at\)
+ 10000268: 98250003 lwr a1,3\(at\)
+ 1000026c: df818030 ld at,-32720\(gp\)
10000270: 88250000 lwl a1,0\(at\)
10000274: 98250003 lwr a1,3\(at\)
- 10000278: df818048 ld at,-32696\(gp\)
- 1000027c: 0025082d daddu at,at,a1
- 10000280: a8250000 swl a1,0\(at\)
- 10000284: b8250003 swr a1,3\(at\)
- 10000288: df8580a8 ld a1,-32600\(gp\)
- 1000028c: df858050 ld a1,-32688\(gp\)
- 10000290: df9980a8 ld t9,-32600\(gp\)
- 10000294: df998050 ld t9,-32688\(gp\)
- 10000298: df9980a8 ld t9,-32600\(gp\)
- 1000029c: 0320f809 jalr t9
- 100002a0: 00000000 nop
- 100002a4: df998050 ld t9,-32688\(gp\)
- 100002a8: 0320f809 jalr t9
- 100002ac: 00000000 nop
- 100002b0: df8580c0 ld a1,-32576\(gp\)
- 100002b4: df8580c0 ld a1,-32576\(gp\)
- 100002b8: 64a5000c daddiu a1,a1,12
- 100002bc: df8580c0 ld a1,-32576\(gp\)
- 100002c0: 3c010002 lui at,0x2
- 100002c4: 6421e240 daddiu at,at,-7616
- 100002c8: 00a1282d daddu a1,a1,at
- 100002cc: df8580c0 ld a1,-32576\(gp\)
- 100002d0: 00b1282d daddu a1,a1,s1
- 100002d4: df8580c0 ld a1,-32576\(gp\)
- 100002d8: 64a5000c daddiu a1,a1,12
- 100002dc: 00b1282d daddu a1,a1,s1
- 100002e0: df8580c0 ld a1,-32576\(gp\)
- 100002e4: 3c010002 lui at,0x2
- 100002e8: 6421e240 daddiu at,at,-7616
- 100002ec: 00a1282d daddu a1,a1,at
- 100002f0: 00b1282d daddu a1,a1,s1
- 100002f4: df8580c0 ld a1,-32576\(gp\)
- 100002f8: dca50000 ld a1,0\(a1\)
- 100002fc: df8580c0 ld a1,-32576\(gp\)
- 10000300: dca5000c ld a1,12\(a1\)
- 10000304: df8580c0 ld a1,-32576\(gp\)
- 10000308: 00b1282d daddu a1,a1,s1
- 1000030c: dca50000 ld a1,0\(a1\)
- 10000310: df8580c0 ld a1,-32576\(gp\)
- 10000314: 00b1282d daddu a1,a1,s1
- 10000318: dca5000c ld a1,12\(a1\)
- 1000031c: df8180c0 ld at,-32576\(gp\)
- 10000320: 0025082d daddu at,at,a1
- 10000324: dc250022 ld a1,34\(at\)
- 10000328: df8180c0 ld at,-32576\(gp\)
- 1000032c: 0025082d daddu at,at,a1
- 10000330: fc250038 sd a1,56\(at\)
- 10000334: df8180c0 ld at,-32576\(gp\)
- 10000338: 88250000 lwl a1,0\(at\)
- 1000033c: 98250003 lwr a1,3\(at\)
- 10000340: df8180c0 ld at,-32576\(gp\)
- 10000344: 6421000c daddiu at,at,12
- 10000348: 88250000 lwl a1,0\(at\)
- 1000034c: 98250003 lwr a1,3\(at\)
- 10000350: df8180c0 ld at,-32576\(gp\)
- 10000354: 0031082d daddu at,at,s1
- 10000358: 88250000 lwl a1,0\(at\)
- 1000035c: 98250003 lwr a1,3\(at\)
- 10000360: df8180c0 ld at,-32576\(gp\)
- 10000364: 6421000c daddiu at,at,12
- 10000368: 0031082d daddu at,at,s1
- 1000036c: 88250000 lwl a1,0\(at\)
- 10000370: 98250003 lwr a1,3\(at\)
- 10000374: df8180c0 ld at,-32576\(gp\)
- 10000378: 64210022 daddiu at,at,34
- 1000037c: 0025082d daddu at,at,a1
- 10000380: 88250000 lwl a1,0\(at\)
- 10000384: 98250003 lwr a1,3\(at\)
- 10000388: df8180c0 ld at,-32576\(gp\)
- 1000038c: 64210038 daddiu at,at,56
- 10000390: 0025082d daddu at,at,a1
- 10000394: a8250000 swl a1,0\(at\)
- 10000398: b8250003 swr a1,3\(at\)
- 1000039c: df858058 ld a1,-32680\(gp\)
- 100003a0: df858060 ld a1,-32672\(gp\)
- 100003a4: df858068 ld a1,-32664\(gp\)
- 100003a8: df858058 ld a1,-32680\(gp\)
- 100003ac: 00b1282d daddu a1,a1,s1
- 100003b0: df858060 ld a1,-32672\(gp\)
- 100003b4: 00b1282d daddu a1,a1,s1
- 100003b8: df858068 ld a1,-32664\(gp\)
- 100003bc: 00b1282d daddu a1,a1,s1
- 100003c0: df858038 ld a1,-32712\(gp\)
- 100003c4: dca505a4 ld a1,1444\(a1\)
- 100003c8: df858038 ld a1,-32712\(gp\)
- 100003cc: dca505b0 ld a1,1456\(a1\)
- 100003d0: df858038 ld a1,-32712\(gp\)
- 100003d4: 00b1282d daddu a1,a1,s1
- 100003d8: dca505a4 ld a1,1444\(a1\)
- 100003dc: df858038 ld a1,-32712\(gp\)
- 100003e0: 00b1282d daddu a1,a1,s1
- 100003e4: dca505b0 ld a1,1456\(a1\)
- 100003e8: df818038 ld at,-32712\(gp\)
- 100003ec: 0025082d daddu at,at,a1
- 100003f0: dc2505c6 ld a1,1478\(at\)
- 100003f4: df818038 ld at,-32712\(gp\)
- 100003f8: 0025082d daddu at,at,a1
- 100003fc: fc2505dc sd a1,1500\(at\)
- 10000400: df818058 ld at,-32680\(gp\)
- 10000404: 88250000 lwl a1,0\(at\)
- 10000408: 98250003 lwr a1,3\(at\)
- 1000040c: df818060 ld at,-32672\(gp\)
- 10000410: 88250000 lwl a1,0\(at\)
- 10000414: 98250003 lwr a1,3\(at\)
- 10000418: df818058 ld at,-32680\(gp\)
- 1000041c: 0031082d daddu at,at,s1
- 10000420: 88250000 lwl a1,0\(at\)
- 10000424: 98250003 lwr a1,3\(at\)
- 10000428: df818060 ld at,-32672\(gp\)
- 1000042c: 0031082d daddu at,at,s1
- 10000430: 88250000 lwl a1,0\(at\)
- 10000434: 98250003 lwr a1,3\(at\)
- 10000438: df818070 ld at,-32656\(gp\)
- 1000043c: 0025082d daddu at,at,a1
+ 10000278: df818020 ld at,-32736\(gp\)
+ 1000027c: 0031082d daddu at,at,s1
+ 10000280: 88250000 lwl a1,0\(at\)
+ 10000284: 98250003 lwr a1,3\(at\)
+ 10000288: df818030 ld at,-32720\(gp\)
+ 1000028c: 0031082d daddu at,at,s1
+ 10000290: 88250000 lwl a1,0\(at\)
+ 10000294: 98250003 lwr a1,3\(at\)
+ 10000298: df818040 ld at,-32704\(gp\)
+ 1000029c: 0025082d daddu at,at,a1
+ 100002a0: 88250000 lwl a1,0\(at\)
+ 100002a4: 98250003 lwr a1,3\(at\)
+ 100002a8: df818048 ld at,-32696\(gp\)
+ 100002ac: 0025082d daddu at,at,a1
+ 100002b0: a8250000 swl a1,0\(at\)
+ 100002b4: b8250003 swr a1,3\(at\)
+ 100002b8: df858050 ld a1,-32688\(gp\)
+ 100002bc: df858050 ld a1,-32688\(gp\)
+ 100002c0: df998050 ld t9,-32688\(gp\)
+ 100002c4: df998050 ld t9,-32688\(gp\)
+ 100002c8: df998050 ld t9,-32688\(gp\)
+ 100002cc: 0411ff90 bal 10000110 <fn>
+ 100002d0: 00000000 nop
+ 100002d4: df998050 ld t9,-32688\(gp\)
+ 100002d8: 0411ff8d bal 10000110 <fn>
+ 100002dc: 00000000 nop
+ 100002e0: df858058 ld a1,-32680\(gp\)
+ 100002e4: df858058 ld a1,-32680\(gp\)
+ 100002e8: 64a5000c daddiu a1,a1,12
+ 100002ec: df858058 ld a1,-32680\(gp\)
+ 100002f0: 3c010001 lui at,0x1
+ 100002f4: 3421e240 ori at,at,0xe240
+ 100002f8: 00a1282d daddu a1,a1,at
+ 100002fc: df858058 ld a1,-32680\(gp\)
+ 10000300: 00b1282d daddu a1,a1,s1
+ 10000304: df858058 ld a1,-32680\(gp\)
+ 10000308: 64a5000c daddiu a1,a1,12
+ 1000030c: 00b1282d daddu a1,a1,s1
+ 10000310: df858058 ld a1,-32680\(gp\)
+ 10000314: 3c010001 lui at,0x1
+ 10000318: 3421e240 ori at,at,0xe240
+ 1000031c: 00a1282d daddu a1,a1,at
+ 10000320: 00b1282d daddu a1,a1,s1
+ 10000324: df858028 ld a1,-32728\(gp\)
+ 10000328: dca505d4 ld a1,1492\(a1\)
+ 1000032c: df858028 ld a1,-32728\(gp\)
+ 10000330: dca505e0 ld a1,1504\(a1\)
+ 10000334: df858028 ld a1,-32728\(gp\)
+ 10000338: 00b1282d daddu a1,a1,s1
+ 1000033c: dca505d4 ld a1,1492\(a1\)
+ 10000340: df858028 ld a1,-32728\(gp\)
+ 10000344: 00b1282d daddu a1,a1,s1
+ 10000348: dca505e0 ld a1,1504\(a1\)
+ 1000034c: df818028 ld at,-32728\(gp\)
+ 10000350: 0025082d daddu at,at,a1
+ 10000354: dc2505f6 ld a1,1526\(at\)
+ 10000358: df818028 ld at,-32728\(gp\)
+ 1000035c: 0025082d daddu at,at,a1
+ 10000360: fc25060c sd a1,1548\(at\)
+ 10000364: df818058 ld at,-32680\(gp\)
+ 10000368: 88250000 lwl a1,0\(at\)
+ 1000036c: 98250003 lwr a1,3\(at\)
+ 10000370: df818058 ld at,-32680\(gp\)
+ 10000374: 6421000c daddiu at,at,12
+ 10000378: 88250000 lwl a1,0\(at\)
+ 1000037c: 98250003 lwr a1,3\(at\)
+ 10000380: df818058 ld at,-32680\(gp\)
+ 10000384: 0031082d daddu at,at,s1
+ 10000388: 88250000 lwl a1,0\(at\)
+ 1000038c: 98250003 lwr a1,3\(at\)
+ 10000390: df818058 ld at,-32680\(gp\)
+ 10000394: 6421000c daddiu at,at,12
+ 10000398: 0031082d daddu at,at,s1
+ 1000039c: 88250000 lwl a1,0\(at\)
+ 100003a0: 98250003 lwr a1,3\(at\)
+ 100003a4: df818058 ld at,-32680\(gp\)
+ 100003a8: 64210022 daddiu at,at,34
+ 100003ac: 0025082d daddu at,at,a1
+ 100003b0: 88250000 lwl a1,0\(at\)
+ 100003b4: 98250003 lwr a1,3\(at\)
+ 100003b8: df818058 ld at,-32680\(gp\)
+ 100003bc: 64210038 daddiu at,at,56
+ 100003c0: 0025082d daddu at,at,a1
+ 100003c4: a8250000 swl a1,0\(at\)
+ 100003c8: b8250003 swr a1,3\(at\)
+ 100003cc: df858058 ld a1,-32680\(gp\)
+ 100003d0: df858060 ld a1,-32672\(gp\)
+ 100003d4: df858068 ld a1,-32664\(gp\)
+ 100003d8: df858058 ld a1,-32680\(gp\)
+ 100003dc: 00b1282d daddu a1,a1,s1
+ 100003e0: df858060 ld a1,-32672\(gp\)
+ 100003e4: 00b1282d daddu a1,a1,s1
+ 100003e8: df858068 ld a1,-32664\(gp\)
+ 100003ec: 00b1282d daddu a1,a1,s1
+ 100003f0: df858028 ld a1,-32728\(gp\)
+ 100003f4: dca505d4 ld a1,1492\(a1\)
+ 100003f8: df858028 ld a1,-32728\(gp\)
+ 100003fc: dca505e0 ld a1,1504\(a1\)
+ 10000400: df858028 ld a1,-32728\(gp\)
+ 10000404: 00b1282d daddu a1,a1,s1
+ 10000408: dca505d4 ld a1,1492\(a1\)
+ 1000040c: df858028 ld a1,-32728\(gp\)
+ 10000410: 00b1282d daddu a1,a1,s1
+ 10000414: dca505e0 ld a1,1504\(a1\)
+ 10000418: df818028 ld at,-32728\(gp\)
+ 1000041c: 0025082d daddu at,at,a1
+ 10000420: dc2505f6 ld a1,1526\(at\)
+ 10000424: df818028 ld at,-32728\(gp\)
+ 10000428: 0025082d daddu at,at,a1
+ 1000042c: fc25060c sd a1,1548\(at\)
+ 10000430: df818058 ld at,-32680\(gp\)
+ 10000434: 88250000 lwl a1,0\(at\)
+ 10000438: 98250003 lwr a1,3\(at\)
+ 1000043c: df818060 ld at,-32672\(gp\)
10000440: 88250000 lwl a1,0\(at\)
10000444: 98250003 lwr a1,3\(at\)
- 10000448: df818078 ld at,-32648\(gp\)
- 1000044c: 0025082d daddu at,at,a1
- 10000450: a8250000 swl a1,0\(at\)
- 10000454: b8250003 swr a1,3\(at\)
- 10000458: df8580b0 ld a1,-32592\(gp\)
- 1000045c: df858080 ld a1,-32640\(gp\)
- 10000460: df9980b0 ld t9,-32592\(gp\)
- 10000464: df998080 ld t9,-32640\(gp\)
- 10000468: df9980b0 ld t9,-32592\(gp\)
- 1000046c: 0320f809 jalr t9
- 10000470: 00000000 nop
- 10000474: df998080 ld t9,-32640\(gp\)
- 10000478: 0320f809 jalr t9
- 1000047c: 00000000 nop
- 10000480: 1000ff17 b 100000e0 <fn>
- 10000484: df8580b8 ld a1,-32584\(gp\)
- 10000488: df8580c0 ld a1,-32576\(gp\)
- 1000048c: 10000015 b 100004e4 <fn2>
- 10000490: dca50000 ld a1,0\(a1\)
- 10000494: 1000ff12 b 100000e0 <fn>
- 10000498: df858020 ld a1,-32736\(gp\)
- 1000049c: df858060 ld a1,-32672\(gp\)
- 100004a0: 10000010 b 100004e4 <fn2>
- 100004a4: 00000000 nop
- 100004a8: df858030 ld a1,-32720\(gp\)
- 100004ac: 1000ff0c b 100000e0 <fn>
- 100004b0: 00000000 nop
- 100004b4: df858038 ld a1,-32712\(gp\)
- 100004b8: 1000000a b 100004e4 <fn2>
- 100004bc: dca505a4 ld a1,1444\(a1\)
- 100004c0: df858038 ld a1,-32712\(gp\)
- 100004c4: 1000ff06 b 100000e0 <fn>
- 100004c8: dca50538 ld a1,1336\(a1\)
- 100004cc: df818038 ld at,-32712\(gp\)
- 100004d0: 0025082d daddu at,at,a1
- 100004d4: 10000003 b 100004e4 <fn2>
- 100004d8: dc2505c6 ld a1,1478\(at\)
+ 10000448: df818058 ld at,-32680\(gp\)
+ 1000044c: 0031082d daddu at,at,s1
+ 10000450: 88250000 lwl a1,0\(at\)
+ 10000454: 98250003 lwr a1,3\(at\)
+ 10000458: df818060 ld at,-32672\(gp\)
+ 1000045c: 0031082d daddu at,at,s1
+ 10000460: 88250000 lwl a1,0\(at\)
+ 10000464: 98250003 lwr a1,3\(at\)
+ 10000468: df818070 ld at,-32656\(gp\)
+ 1000046c: 0025082d daddu at,at,a1
+ 10000470: 88250000 lwl a1,0\(at\)
+ 10000474: 98250003 lwr a1,3\(at\)
+ 10000478: df818078 ld at,-32648\(gp\)
+ 1000047c: 0025082d daddu at,at,a1
+ 10000480: a8250000 swl a1,0\(at\)
+ 10000484: b8250003 swr a1,3\(at\)
+ 10000488: df858080 ld a1,-32640\(gp\)
+ 1000048c: df858080 ld a1,-32640\(gp\)
+ 10000490: df998080 ld t9,-32640\(gp\)
+ 10000494: df998080 ld t9,-32640\(gp\)
+ 10000498: df998080 ld t9,-32640\(gp\)
+ 1000049c: 0411001d bal 10000514 <fn2>
+ 100004a0: 00000000 nop
+ 100004a4: df998080 ld t9,-32640\(gp\)
+ 100004a8: 0411001a bal 10000514 <fn2>
+ 100004ac: 00000000 nop
+ 100004b0: 1000ff17 b 10000110 <fn>
+ 100004b4: df858020 ld a1,-32736\(gp\)
+ 100004b8: df858028 ld a1,-32728\(gp\)
+ 100004bc: 10000015 b 10000514 <fn2>
+ 100004c0: dca505d4 ld a1,1492\(a1\)
+ 100004c4: 1000ff12 b 10000110 <fn>
+ 100004c8: df858020 ld a1,-32736\(gp\)
+ 100004cc: df858060 ld a1,-32672\(gp\)
+ 100004d0: 10000010 b 10000514 <fn2>
+ 100004d4: 00000000 nop
+ 100004d8: df858038 ld a1,-32712\(gp\)
+ 100004dc: 1000ff0c b 10000110 <fn>
+ 100004e0: 00000000 nop
+ 100004e4: df858028 ld a1,-32728\(gp\)
+ 100004e8: 1000000a b 10000514 <fn2>
+ 100004ec: dca505d4 ld a1,1492\(a1\)
+ 100004f0: df858028 ld a1,-32728\(gp\)
+ 100004f4: 1000ff06 b 10000110 <fn>
+ 100004f8: dca50568 ld a1,1384\(a1\)
+ 100004fc: df818028 ld at,-32728\(gp\)
+ 10000500: 0025082d daddu at,at,a1
+ 10000504: 10000003 b 10000514 <fn2>
+ 10000508: dc2505f6 ld a1,1526\(at\)
\.\.\.
-00000000100004e4 <fn2>:
+0000000010000514 <fn2>:
\.\.\.
Disassembly of section \.data:
-00000000101004f0 <_fdata>:
+0000000010010520 <_fdata>:
\.\.\.
-000000001010052c <dg1>:
+000000001001055c <dg1>:
\.\.\.
-0000000010100568 <sp2>:
+0000000010010598 <sp2>:
\.\.\.
-00000000101005a4 <dg2>:
+00000000100105d4 <dg2>:
\.\.\.
Disassembly of section \.got:
-00000000101005e0 <_GLOBAL_OFFSET_TABLE_>:
+0000000010010610 <_GLOBAL_OFFSET_TABLE_>:
\.\.\.
- 101005e8: 80000000 .*
- 101005ec: 00000000 .*
- 101005f0: 00000000 .*
- 101005f4: 1010052c .*
- 101005f8: 00000000 .*
- 101005fc: 10100538 .*
- 10100600: 00000000 .*
- 10100604: 1011e76c .*
- 10100608: 00000000 .*
- 1010060c: 10100000 .*
- 10100610: 00000000 .*
- 10100614: 1010054e .*
- 10100618: 00000000 .*
- 1010061c: 10100564 .*
- 10100620: 00000000 .*
- 10100624: 100000e0 .*
- 10100628: 00000000 .*
- 1010062c: 101005a4 .*
- 10100630: 00000000 .*
- 10100634: 101005b0 .*
- 10100638: 00000000 .*
- 1010063c: 1011e7e4 .*
- 10100640: 00000000 .*
- 10100644: 101005c6 .*
- 10100648: 00000000 .*
- 1010064c: 101005dc .*
- 10100650: 00000000 .*
- 10100654: 100004e4 .*
- 10100658: 00000000 .*
+ 10010618: 80000000 .*
+ \.\.\.
+ 10010624: 1001055c .*
+ 10010628: 00000000 .*
+ 1001062c: 10010000 .*
+ 10010630: 00000000 .*
+ 10010634: 10010568 .*
+ 10010638: 00000000 .*
+ 1001063c: 1002e79c .*
+ 10010640: 00000000 .*
+ 10010644: 1001057e .*
+ 10010648: 00000000 .*
+ 1001064c: 10010594 .*
+ 10010650: 00000000 .*
+ 10010654: 10000110 .*
+ 10010658: 00000000 .*
+ 1001065c: 100105d4 .*
+ 10010660: 00000000 .*
+ 10010664: 100105e0 .*
+ 10010668: 00000000 .*
+ 1001066c: 1002e814 .*
+ 10010670: 00000000 .*
+ 10010674: 100105f6 .*
+ 10010678: 00000000 .*
+ 1001067c: 1001060c .*
+ 10010680: 00000000 .*
+ 10010684: 10000514 .*
+ 10010688: 00000000 .*
\.\.\.
- 1010067c: 100000e0 .*
- 10100680: 00000000 .*
- 10100684: 100004e4 .*
- 10100688: 00000000 .*
- 1010068c: 1010052c .*
- 10100690: 00000000 .*
- 10100694: 101005a4 .*
#name: MIPS ELF xgot reloc n32
-#as: -EB -n32 -KPIC -xgot
+#as: -march=from-abi -EB -n32 -KPIC -xgot
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
-#ld: -melf32btsmipn32
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf32-n.*mips.*
10000098 <\.reginfo>:
10000098: 92020022 .*
\.\.\.
-100000ac: 10018790 .*
+100000ac: 100187a0 .*
Disassembly of section \.text:
10000224: a8250000 swl a1,0\(at\)
10000228: b8250003 swr a1,3\(at\)
1000022c: 8f85801c lw a1,-32740\(gp\)
-10000230: 24a506ec addiu a1,a1,1772
+10000230: 24a506fc addiu a1,a1,1788
10000234: 8f85801c lw a1,-32740\(gp\)
-10000238: 24a506f8 addiu a1,a1,1784
+10000238: 24a50708 addiu a1,a1,1800
1000023c: 8f858020 lw a1,-32736\(gp\)
-10000240: 24a5e92c addiu a1,a1,-5844
+10000240: 24a5e93c addiu a1,a1,-5828
10000244: 8f85801c lw a1,-32740\(gp\)
-10000248: 24a506ec addiu a1,a1,1772
+10000248: 24a506fc addiu a1,a1,1788
1000024c: 00b12821 addu a1,a1,s1
10000250: 8f85801c lw a1,-32740\(gp\)
-10000254: 24a506f8 addiu a1,a1,1784
+10000254: 24a50708 addiu a1,a1,1800
10000258: 00b12821 addu a1,a1,s1
1000025c: 8f858020 lw a1,-32736\(gp\)
-10000260: 24a5e92c addiu a1,a1,-5844
+10000260: 24a5e93c addiu a1,a1,-5828
10000264: 00b12821 addu a1,a1,s1
10000268: 8f85801c lw a1,-32740\(gp\)
-1000026c: 8ca506ec lw a1,1772\(a1\)
+1000026c: 8ca506fc lw a1,1788\(a1\)
10000270: 8f85801c lw a1,-32740\(gp\)
-10000274: 8ca506f8 lw a1,1784\(a1\)
+10000274: 8ca50708 lw a1,1800\(a1\)
10000278: 8f85801c lw a1,-32740\(gp\)
1000027c: 00b12821 addu a1,a1,s1
-10000280: 8ca506ec lw a1,1772\(a1\)
+10000280: 8ca506fc lw a1,1788\(a1\)
10000284: 8f85801c lw a1,-32740\(gp\)
10000288: 00b12821 addu a1,a1,s1
-1000028c: 8ca506f8 lw a1,1784\(a1\)
+1000028c: 8ca50708 lw a1,1800\(a1\)
10000290: 8f81801c lw at,-32740\(gp\)
10000294: 00250821 addu at,at,a1
-10000298: 8c25070e lw a1,1806\(at\)
+10000298: 8c25071e lw a1,1822\(at\)
1000029c: 8f81801c lw at,-32740\(gp\)
100002a0: 00250821 addu at,at,a1
-100002a4: ac250724 sw a1,1828\(at\)
+100002a4: ac250734 sw a1,1844\(at\)
100002a8: 8f81801c lw at,-32740\(gp\)
-100002ac: 242106ec addiu at,at,1772
+100002ac: 242106fc addiu at,at,1788
100002b0: 88250000 lwl a1,0\(at\)
100002b4: 98250003 lwr a1,3\(at\)
100002b8: 8f81801c lw at,-32740\(gp\)
-100002bc: 242106f8 addiu at,at,1784
+100002bc: 24210708 addiu at,at,1800
100002c0: 88250000 lwl a1,0\(at\)
100002c4: 98250003 lwr a1,3\(at\)
100002c8: 8f81801c lw at,-32740\(gp\)
-100002cc: 242106ec addiu at,at,1772
+100002cc: 242106fc addiu at,at,1788
100002d0: 00310821 addu at,at,s1
100002d4: 88250000 lwl a1,0\(at\)
100002d8: 98250003 lwr a1,3\(at\)
100002dc: 8f81801c lw at,-32740\(gp\)
-100002e0: 242106f8 addiu at,at,1784
+100002e0: 24210708 addiu at,at,1800
100002e4: 00310821 addu at,at,s1
100002e8: 88250000 lwl a1,0\(at\)
100002ec: 98250003 lwr a1,3\(at\)
100002f0: 8f81801c lw at,-32740\(gp\)
-100002f4: 2421070e addiu at,at,1806
+100002f4: 2421071e addiu at,at,1822
100002f8: 00250821 addu at,at,a1
100002fc: 88250000 lwl a1,0\(at\)
10000300: 98250003 lwr a1,3\(at\)
10000304: 8f81801c lw at,-32740\(gp\)
-10000308: 24210724 addiu at,at,1828
+10000308: 24210734 addiu at,at,1844
1000030c: 00250821 addu at,at,a1
10000310: a8250000 swl a1,0\(at\)
10000314: b8250003 swr a1,3\(at\)
100004d8: a8250000 swl a1,0\(at\)
100004dc: b8250003 swr a1,3\(at\)
100004e0: 8f85801c lw a1,-32740\(gp\)
-100004e4: 24a50764 addiu a1,a1,1892
+100004e4: 24a50774 addiu a1,a1,1908
100004e8: 8f85801c lw a1,-32740\(gp\)
-100004ec: 24a50770 addiu a1,a1,1904
+100004ec: 24a50780 addiu a1,a1,1920
100004f0: 8f858020 lw a1,-32736\(gp\)
-100004f4: 24a5e9a4 addiu a1,a1,-5724
+100004f4: 24a5e9b4 addiu a1,a1,-5708
100004f8: 8f85801c lw a1,-32740\(gp\)
-100004fc: 24a50764 addiu a1,a1,1892
+100004fc: 24a50774 addiu a1,a1,1908
10000500: 00b12821 addu a1,a1,s1
10000504: 8f85801c lw a1,-32740\(gp\)
-10000508: 24a50770 addiu a1,a1,1904
+10000508: 24a50780 addiu a1,a1,1920
1000050c: 00b12821 addu a1,a1,s1
10000510: 8f858020 lw a1,-32736\(gp\)
-10000514: 24a5e9a4 addiu a1,a1,-5724
+10000514: 24a5e9b4 addiu a1,a1,-5708
10000518: 00b12821 addu a1,a1,s1
1000051c: 8f85801c lw a1,-32740\(gp\)
-10000520: 8ca50764 lw a1,1892\(a1\)
+10000520: 8ca50774 lw a1,1908\(a1\)
10000524: 8f85801c lw a1,-32740\(gp\)
-10000528: 8ca50770 lw a1,1904\(a1\)
+10000528: 8ca50780 lw a1,1920\(a1\)
1000052c: 8f85801c lw a1,-32740\(gp\)
10000530: 00b12821 addu a1,a1,s1
-10000534: 8ca50764 lw a1,1892\(a1\)
+10000534: 8ca50774 lw a1,1908\(a1\)
10000538: 8f85801c lw a1,-32740\(gp\)
1000053c: 00b12821 addu a1,a1,s1
-10000540: 8ca50770 lw a1,1904\(a1\)
+10000540: 8ca50780 lw a1,1920\(a1\)
10000544: 8f81801c lw at,-32740\(gp\)
10000548: 00250821 addu at,at,a1
-1000054c: 8c250786 lw a1,1926\(at\)
+1000054c: 8c250796 lw a1,1942\(at\)
10000550: 8f81801c lw at,-32740\(gp\)
10000554: 00250821 addu at,at,a1
-10000558: ac25079c sw a1,1948\(at\)
+10000558: ac2507ac sw a1,1964\(at\)
1000055c: 8f81801c lw at,-32740\(gp\)
-10000560: 24210764 addiu at,at,1892
+10000560: 24210774 addiu at,at,1908
10000564: 88250000 lwl a1,0\(at\)
10000568: 98250003 lwr a1,3\(at\)
1000056c: 8f81801c lw at,-32740\(gp\)
-10000570: 24210770 addiu at,at,1904
+10000570: 24210780 addiu at,at,1920
10000574: 88250000 lwl a1,0\(at\)
10000578: 98250003 lwr a1,3\(at\)
1000057c: 8f81801c lw at,-32740\(gp\)
-10000580: 24210764 addiu at,at,1892
+10000580: 24210774 addiu at,at,1908
10000584: 00310821 addu at,at,s1
10000588: 88250000 lwl a1,0\(at\)
1000058c: 98250003 lwr a1,3\(at\)
10000590: 8f81801c lw at,-32740\(gp\)
-10000594: 24210770 addiu at,at,1904
+10000594: 24210780 addiu at,at,1920
10000598: 00310821 addu at,at,s1
1000059c: 88250000 lwl a1,0\(at\)
100005a0: 98250003 lwr a1,3\(at\)
100005a4: 8f81801c lw at,-32740\(gp\)
-100005a8: 24210786 addiu at,at,1926
+100005a8: 24210796 addiu at,at,1942
100005ac: 00250821 addu at,at,a1
100005b0: 88250000 lwl a1,0\(at\)
100005b4: 98250003 lwr a1,3\(at\)
100005b8: 8f81801c lw at,-32740\(gp\)
-100005bc: 2421079c addiu at,at,1948
+100005bc: 242107ac addiu at,at,1964
100005c0: 00250821 addu at,at,a1
100005c4: a8250000 swl a1,0\(at\)
100005c8: b8250003 swr a1,3\(at\)
1000063c: 1000001c b 100006b0 <fn2>
10000640: 00000000 nop
10000644: 8f85801c lw a1,-32740\(gp\)
-10000648: 24a506ec addiu a1,a1,1772
+10000648: 24a506fc addiu a1,a1,1788
1000064c: 1000fe98 b 100000b0 <fn>
10000650: 00000000 nop
10000654: 8f85801c lw a1,-32740\(gp\)
-10000658: 24a50770 addiu a1,a1,1904
+10000658: 24a50780 addiu a1,a1,1920
1000065c: 10000014 b 100006b0 <fn2>
10000660: 00000000 nop
10000664: 8f858020 lw a1,-32736\(gp\)
-10000668: 24a5e92c addiu a1,a1,-5844
+10000668: 24a5e93c addiu a1,a1,-5828
1000066c: 1000fe90 b 100000b0 <fn>
10000670: 00000000 nop
10000674: 8f85801c lw a1,-32740\(gp\)
-10000678: 8ca50764 lw a1,1892\(a1\)
+10000678: 8ca50774 lw a1,1908\(a1\)
1000067c: 1000000c b 100006b0 <fn2>
10000680: 00000000 nop
10000684: 8f85801c lw a1,-32740\(gp\)
-10000688: 8ca506f8 lw a1,1784\(a1\)
+10000688: 8ca50708 lw a1,1800\(a1\)
1000068c: 1000fe88 b 100000b0 <fn>
10000690: 00000000 nop
10000694: 8f81801c lw at,-32740\(gp\)
10000698: 00250821 addu at,at,a1
-1000069c: 8c250786 lw a1,1926\(at\)
+1000069c: 8c250796 lw a1,1942\(at\)
100006a0: 10000003 b 100006b0 <fn2>
100006a4: 00000000 nop
\.\.\.
+100006b0 <fn2>:
+ \.\.\.
+
Disassembly of section \.data:
-100106b0 <_fdata>:
+100106c0 <_fdata>:
\.\.\.
-100106ec <dg1>:
+100106fc <dg1>:
\.\.\.
-10010728 <sp2>:
+10010738 <sp2>:
\.\.\.
-10010764 <dg2>:
+10010774 <dg2>:
\.\.\.
Disassembly of section \.got:
-100107a0 <_GLOBAL_OFFSET_TABLE_>:
-100107a0: 00000000 .*
-100107a4: 80000000 .*
-100107a8: 100106ec .*
-100107ac: 10010000 .*
-100107b0: 10030000 .*
-100107b4: 100000b0 .*
-100107b8: 10000000 .*
-100107bc: 10010764 .*
-100107c0: 100006b0 .*
-100107c4: 00000000 .*
-100107c8: 00000000 .*
+100107b0 <_GLOBAL_OFFSET_TABLE_>:
+100107b0: 00000000 .*
+100107b4: 80000000 .*
+100107b8: 100106fc .*
+100107bc: 10010000 .*
+100107c0: 10030000 .*
+100107c4: 100000b0 .*
+100107c8: 10000000 .*
+100107cc: 10010774 .*
+100107d0: 100006b0 .*
+100107d4: 00000000 .*
+100107d8: 00000000 .*
#pass
#name: MIPS ELF xgot reloc n64
-#as: -EB -64 -KPIC -xgot
+#as: -march=from-abi -EB -64 -KPIC -xgot
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
1200000b8: 92020022 .*
\.\.\.
1200000d0: 00000001 .*
- 1200000d4: 200187c0 .*
+ 1200000d4: 200187d0 .*
Disassembly of section \.text:
120000254: a8250000 swl a1,0\(at\)
120000258: b8250003 swr a1,3\(at\)
12000025c: df858028 ld a1,-32728\(gp\)
- 120000260: 64a5071c daddiu a1,a1,1820
+ 120000260: 64a5072c daddiu a1,a1,1836
120000264: df858028 ld a1,-32728\(gp\)
- 120000268: 64a50728 daddiu a1,a1,1832
+ 120000268: 64a50738 daddiu a1,a1,1848
12000026c: df858030 ld a1,-32720\(gp\)
- 120000270: 64a5e95c daddiu a1,a1,-5796
+ 120000270: 64a5e96c daddiu a1,a1,-5780
120000274: df858028 ld a1,-32728\(gp\)
- 120000278: 64a5071c daddiu a1,a1,1820
+ 120000278: 64a5072c daddiu a1,a1,1836
12000027c: 00b1282d daddu a1,a1,s1
120000280: df858028 ld a1,-32728\(gp\)
- 120000284: 64a50728 daddiu a1,a1,1832
+ 120000284: 64a50738 daddiu a1,a1,1848
120000288: 00b1282d daddu a1,a1,s1
12000028c: df858030 ld a1,-32720\(gp\)
- 120000290: 64a5e95c daddiu a1,a1,-5796
+ 120000290: 64a5e96c daddiu a1,a1,-5780
120000294: 00b1282d daddu a1,a1,s1
120000298: df858028 ld a1,-32728\(gp\)
- 12000029c: dca5071c ld a1,1820\(a1\)
+ 12000029c: dca5072c ld a1,1836\(a1\)
1200002a0: df858028 ld a1,-32728\(gp\)
- 1200002a4: dca50728 ld a1,1832\(a1\)
+ 1200002a4: dca50738 ld a1,1848\(a1\)
1200002a8: df858028 ld a1,-32728\(gp\)
1200002ac: 00b1282d daddu a1,a1,s1
- 1200002b0: dca5071c ld a1,1820\(a1\)
+ 1200002b0: dca5072c ld a1,1836\(a1\)
1200002b4: df858028 ld a1,-32728\(gp\)
1200002b8: 00b1282d daddu a1,a1,s1
- 1200002bc: dca50728 ld a1,1832\(a1\)
+ 1200002bc: dca50738 ld a1,1848\(a1\)
1200002c0: df818028 ld at,-32728\(gp\)
1200002c4: 0025082d daddu at,at,a1
- 1200002c8: dc25073e ld a1,1854\(at\)
+ 1200002c8: dc25074e ld a1,1870\(at\)
1200002cc: df818028 ld at,-32728\(gp\)
1200002d0: 0025082d daddu at,at,a1
- 1200002d4: fc250754 sd a1,1876\(at\)
+ 1200002d4: fc250764 sd a1,1892\(at\)
1200002d8: df818028 ld at,-32728\(gp\)
- 1200002dc: 6421071c daddiu at,at,1820
+ 1200002dc: 6421072c daddiu at,at,1836
1200002e0: 88250000 lwl a1,0\(at\)
1200002e4: 98250003 lwr a1,3\(at\)
1200002e8: df818028 ld at,-32728\(gp\)
- 1200002ec: 64210728 daddiu at,at,1832
+ 1200002ec: 64210738 daddiu at,at,1848
1200002f0: 88250000 lwl a1,0\(at\)
1200002f4: 98250003 lwr a1,3\(at\)
1200002f8: df818028 ld at,-32728\(gp\)
- 1200002fc: 6421071c daddiu at,at,1820
+ 1200002fc: 6421072c daddiu at,at,1836
120000300: 0031082d daddu at,at,s1
120000304: 88250000 lwl a1,0\(at\)
120000308: 98250003 lwr a1,3\(at\)
12000030c: df818028 ld at,-32728\(gp\)
- 120000310: 64210728 daddiu at,at,1832
+ 120000310: 64210738 daddiu at,at,1848
120000314: 0031082d daddu at,at,s1
120000318: 88250000 lwl a1,0\(at\)
12000031c: 98250003 lwr a1,3\(at\)
120000320: df818028 ld at,-32728\(gp\)
- 120000324: 6421073e daddiu at,at,1854
+ 120000324: 6421074e daddiu at,at,1870
120000328: 0025082d daddu at,at,a1
12000032c: 88250000 lwl a1,0\(at\)
120000330: 98250003 lwr a1,3\(at\)
120000334: df818028 ld at,-32728\(gp\)
- 120000338: 64210754 daddiu at,at,1876
+ 120000338: 64210764 daddiu at,at,1892
12000033c: 0025082d daddu at,at,a1
120000340: a8250000 swl a1,0\(at\)
120000344: b8250003 swr a1,3\(at\)
120000508: a8250000 swl a1,0\(at\)
12000050c: b8250003 swr a1,3\(at\)
120000510: df858028 ld a1,-32728\(gp\)
- 120000514: 64a50794 daddiu a1,a1,1940
+ 120000514: 64a507a4 daddiu a1,a1,1956
120000518: df858028 ld a1,-32728\(gp\)
- 12000051c: 64a507a0 daddiu a1,a1,1952
+ 12000051c: 64a507b0 daddiu a1,a1,1968
120000520: df858030 ld a1,-32720\(gp\)
- 120000524: 64a5e9d4 daddiu a1,a1,-5676
+ 120000524: 64a5e9e4 daddiu a1,a1,-5660
120000528: df858028 ld a1,-32728\(gp\)
- 12000052c: 64a50794 daddiu a1,a1,1940
+ 12000052c: 64a507a4 daddiu a1,a1,1956
120000530: 00b1282d daddu a1,a1,s1
120000534: df858028 ld a1,-32728\(gp\)
- 120000538: 64a507a0 daddiu a1,a1,1952
+ 120000538: 64a507b0 daddiu a1,a1,1968
12000053c: 00b1282d daddu a1,a1,s1
120000540: df858030 ld a1,-32720\(gp\)
- 120000544: 64a5e9d4 daddiu a1,a1,-5676
+ 120000544: 64a5e9e4 daddiu a1,a1,-5660
120000548: 00b1282d daddu a1,a1,s1
12000054c: df858028 ld a1,-32728\(gp\)
- 120000550: dca50794 ld a1,1940\(a1\)
+ 120000550: dca507a4 ld a1,1956\(a1\)
120000554: df858028 ld a1,-32728\(gp\)
- 120000558: dca507a0 ld a1,1952\(a1\)
+ 120000558: dca507b0 ld a1,1968\(a1\)
12000055c: df858028 ld a1,-32728\(gp\)
120000560: 00b1282d daddu a1,a1,s1
- 120000564: dca50794 ld a1,1940\(a1\)
+ 120000564: dca507a4 ld a1,1956\(a1\)
120000568: df858028 ld a1,-32728\(gp\)
12000056c: 00b1282d daddu a1,a1,s1
- 120000570: dca507a0 ld a1,1952\(a1\)
+ 120000570: dca507b0 ld a1,1968\(a1\)
120000574: df818028 ld at,-32728\(gp\)
120000578: 0025082d daddu at,at,a1
- 12000057c: dc2507b6 ld a1,1974\(at\)
+ 12000057c: dc2507c6 ld a1,1990\(at\)
120000580: df818028 ld at,-32728\(gp\)
120000584: 0025082d daddu at,at,a1
- 120000588: fc2507cc sd a1,1996\(at\)
+ 120000588: fc2507dc sd a1,2012\(at\)
12000058c: df818028 ld at,-32728\(gp\)
- 120000590: 64210794 daddiu at,at,1940
+ 120000590: 642107a4 daddiu at,at,1956
120000594: 88250000 lwl a1,0\(at\)
120000598: 98250003 lwr a1,3\(at\)
12000059c: df818028 ld at,-32728\(gp\)
- 1200005a0: 642107a0 daddiu at,at,1952
+ 1200005a0: 642107b0 daddiu at,at,1968
1200005a4: 88250000 lwl a1,0\(at\)
1200005a8: 98250003 lwr a1,3\(at\)
1200005ac: df818028 ld at,-32728\(gp\)
- 1200005b0: 64210794 daddiu at,at,1940
+ 1200005b0: 642107a4 daddiu at,at,1956
1200005b4: 0031082d daddu at,at,s1
1200005b8: 88250000 lwl a1,0\(at\)
1200005bc: 98250003 lwr a1,3\(at\)
1200005c0: df818028 ld at,-32728\(gp\)
- 1200005c4: 642107a0 daddiu at,at,1952
+ 1200005c4: 642107b0 daddiu at,at,1968
1200005c8: 0031082d daddu at,at,s1
1200005cc: 88250000 lwl a1,0\(at\)
1200005d0: 98250003 lwr a1,3\(at\)
1200005d4: df818028 ld at,-32728\(gp\)
- 1200005d8: 642107b6 daddiu at,at,1974
+ 1200005d8: 642107c6 daddiu at,at,1990
1200005dc: 0025082d daddu at,at,a1
1200005e0: 88250000 lwl a1,0\(at\)
1200005e4: 98250003 lwr a1,3\(at\)
1200005e8: df818028 ld at,-32728\(gp\)
- 1200005ec: 642107cc daddiu at,at,1996
+ 1200005ec: 642107dc daddiu at,at,2012
1200005f0: 0025082d daddu at,at,a1
1200005f4: a8250000 swl a1,0\(at\)
1200005f8: b8250003 swr a1,3\(at\)
12000066c: 1000001c b 1200006e0 <fn2>
120000670: 00000000 nop
120000674: df858028 ld a1,-32728\(gp\)
- 120000678: 64a5071c daddiu a1,a1,1820
+ 120000678: 64a5072c daddiu a1,a1,1836
12000067c: 1000fe98 b 1200000e0 <fn>
120000680: 00000000 nop
120000684: df858028 ld a1,-32728\(gp\)
- 120000688: 64a507a0 daddiu a1,a1,1952
+ 120000688: 64a507b0 daddiu a1,a1,1968
12000068c: 10000014 b 1200006e0 <fn2>
120000690: 00000000 nop
120000694: df858030 ld a1,-32720\(gp\)
- 120000698: 64a5e95c daddiu a1,a1,-5796
+ 120000698: 64a5e96c daddiu a1,a1,-5780
12000069c: 1000fe90 b 1200000e0 <fn>
1200006a0: 00000000 nop
1200006a4: df858028 ld a1,-32728\(gp\)
- 1200006a8: dca50794 ld a1,1940\(a1\)
+ 1200006a8: dca507a4 ld a1,1956\(a1\)
1200006ac: 1000000c b 1200006e0 <fn2>
1200006b0: 00000000 nop
1200006b4: df858028 ld a1,-32728\(gp\)
- 1200006b8: dca50728 ld a1,1832\(a1\)
+ 1200006b8: dca50738 ld a1,1848\(a1\)
1200006bc: 1000fe88 b 1200000e0 <fn>
1200006c0: 00000000 nop
1200006c4: df818028 ld at,-32728\(gp\)
1200006c8: 0025082d daddu at,at,a1
- 1200006cc: dc2507b6 ld a1,1974\(at\)
+ 1200006cc: dc2507c6 ld a1,1990\(at\)
1200006d0: 10000003 b 1200006e0 <fn2>
1200006d4: 00000000 nop
\.\.\.
+00000001200006e0 <fn2>:
+ \.\.\.
+
Disassembly of section \.data:
-00000001200106e0 <_fdata>:
+00000001200106f0 <_fdata>:
\.\.\.
-000000012001071c <dg1>:
+000000012001072c <dg1>:
\.\.\.
-0000000120010758 <sp2>:
+0000000120010768 <sp2>:
\.\.\.
-0000000120010794 <dg2>:
+00000001200107a4 <dg2>:
\.\.\.
Disassembly of section \.got:
-00000001200107d0 <_GLOBAL_OFFSET_TABLE_>:
+00000001200107e0 <_GLOBAL_OFFSET_TABLE_>:
\.\.\.
- 1200107d8: 80000000 .*
- 1200107dc: 00000000 .*
- 1200107e0: 00000001 .*
- 1200107e4: 2001071c .*
- 1200107e8: 00000001 .*
- 1200107ec: 20010000 .*
+ 1200107e8: 80000000 .*
+ 1200107ec: 00000000 .*
1200107f0: 00000001 .*
- 1200107f4: 20030000 .*
+ 1200107f4: 2001072c .*
1200107f8: 00000001 .*
- 1200107fc: 200000e0 .*
+ 1200107fc: 20010000 .*
120010800: 00000001 .*
- 120010804: 20000000 .*
+ 120010804: 20030000 .*
120010808: 00000001 .*
- 12001080c: 20010794 .*
+ 12001080c: 200000e0 .*
120010810: 00000001 .*
- 120010814: 200006e0 .*
+ 120010814: 20000000 .*
+ 120010818: 00000001 .*
+ 12001081c: 200107a4 .*
+ 120010820: 00000001 .*
+ 120010824: 200006e0 .*
\.\.\.
#pass
#name: MIPS ELF xgot reloc n64
-#as: -EB -64 -KPIC -xgot
+#as: -march=from-abi -EB -64 -KPIC -xgot
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
Disassembly of section \.MIPS\.options:
-00000000100000b0 <\.MIPS\.options>:
- 100000b0: 01280000 .*
- 100000b4: 00000000 .*
- 100000b8: 92020022 .*
+00000000100000e8 <\.MIPS\.options>:
+ 100000e8: 01280000 .*
+ 100000ec: 00000000 .*
+ 100000f0: 92020022 .*
\.\.\.
- 100000d4: 101087c0 .*
+ 1000010c: 10018800 .*
Disassembly of section \.text:
-00000000100000e0 <fn>:
- 100000e0: 3c050000 lui a1,0x0
- 100000e4: 00bc282d daddu a1,a1,gp
- 100000e8: dca58058 ld a1,-32680\(a1\)
- 100000ec: 3c050000 lui a1,0x0
- 100000f0: 00bc282d daddu a1,a1,gp
- 100000f4: dca58058 ld a1,-32680\(a1\)
- 100000f8: 64a5000c daddiu a1,a1,12
- 100000fc: 3c050000 lui a1,0x0
- 10000100: 00bc282d daddu a1,a1,gp
- 10000104: dca58058 ld a1,-32680\(a1\)
- 10000108: 3c010002 lui at,0x2
- 1000010c: 6421e240 daddiu at,at,-7616
- 10000110: 00a1282d daddu a1,a1,at
- 10000114: 3c050000 lui a1,0x0
- 10000118: 00bc282d daddu a1,a1,gp
- 1000011c: dca58058 ld a1,-32680\(a1\)
- 10000120: 00b1282d daddu a1,a1,s1
- 10000124: 3c050000 lui a1,0x0
- 10000128: 00bc282d daddu a1,a1,gp
- 1000012c: dca58058 ld a1,-32680\(a1\)
- 10000130: 64a5000c daddiu a1,a1,12
- 10000134: 00b1282d daddu a1,a1,s1
- 10000138: 3c050000 lui a1,0x0
- 1000013c: 00bc282d daddu a1,a1,gp
- 10000140: dca58058 ld a1,-32680\(a1\)
- 10000144: 3c010002 lui at,0x2
- 10000148: 6421e240 daddiu at,at,-7616
- 1000014c: 00a1282d daddu a1,a1,at
+0000000010000110 <fn>:
+ 10000110: 3c050000 lui a1,0x0
+ 10000114: 00bc282d daddu a1,a1,gp
+ 10000118: dca58020 ld a1,-32736\(a1\)
+ 1000011c: 3c050000 lui a1,0x0
+ 10000120: 00bc282d daddu a1,a1,gp
+ 10000124: dca58020 ld a1,-32736\(a1\)
+ 10000128: 64a5000c daddiu a1,a1,12
+ 1000012c: 3c050000 lui a1,0x0
+ 10000130: 00bc282d daddu a1,a1,gp
+ 10000134: dca58020 ld a1,-32736\(a1\)
+ 10000138: 3c010001 lui at,0x1
+ 1000013c: 3421e240 ori at,at,0xe240
+ 10000140: 00a1282d daddu a1,a1,at
+ 10000144: 3c050000 lui a1,0x0
+ 10000148: 00bc282d daddu a1,a1,gp
+ 1000014c: dca58020 ld a1,-32736\(a1\)
10000150: 00b1282d daddu a1,a1,s1
10000154: 3c050000 lui a1,0x0
10000158: 00bc282d daddu a1,a1,gp
- 1000015c: dca58058 ld a1,-32680\(a1\)
- 10000160: dca50000 ld a1,0\(a1\)
- 10000164: 3c050000 lui a1,0x0
- 10000168: 00bc282d daddu a1,a1,gp
- 1000016c: dca58058 ld a1,-32680\(a1\)
- 10000170: dca5000c ld a1,12\(a1\)
- 10000174: 3c050000 lui a1,0x0
- 10000178: 00bc282d daddu a1,a1,gp
- 1000017c: dca58058 ld a1,-32680\(a1\)
+ 1000015c: dca58020 ld a1,-32736\(a1\)
+ 10000160: 64a5000c daddiu a1,a1,12
+ 10000164: 00b1282d daddu a1,a1,s1
+ 10000168: 3c050000 lui a1,0x0
+ 1000016c: 00bc282d daddu a1,a1,gp
+ 10000170: dca58020 ld a1,-32736\(a1\)
+ 10000174: 3c010001 lui at,0x1
+ 10000178: 3421e240 ori at,at,0xe240
+ 1000017c: 00a1282d daddu a1,a1,at
10000180: 00b1282d daddu a1,a1,s1
- 10000184: dca50000 ld a1,0\(a1\)
- 10000188: 3c050000 lui a1,0x0
- 1000018c: 00bc282d daddu a1,a1,gp
- 10000190: dca58058 ld a1,-32680\(a1\)
- 10000194: 00b1282d daddu a1,a1,s1
- 10000198: dca5000c ld a1,12\(a1\)
- 1000019c: 3c010000 lui at,0x0
- 100001a0: 003c082d daddu at,at,gp
- 100001a4: dc218058 ld at,-32680\(at\)
- 100001a8: 0025082d daddu at,at,a1
- 100001ac: dc250022 ld a1,34\(at\)
- 100001b0: 3c010000 lui at,0x0
- 100001b4: 003c082d daddu at,at,gp
- 100001b8: dc218058 ld at,-32680\(at\)
- 100001bc: 0025082d daddu at,at,a1
- 100001c0: fc250038 sd a1,56\(at\)
- 100001c4: 3c010000 lui at,0x0
- 100001c8: 003c082d daddu at,at,gp
- 100001cc: dc218058 ld at,-32680\(at\)
- 100001d0: 88250000 lwl a1,0\(at\)
- 100001d4: 98250003 lwr a1,3\(at\)
- 100001d8: 3c010000 lui at,0x0
- 100001dc: 003c082d daddu at,at,gp
- 100001e0: dc218058 ld at,-32680\(at\)
- 100001e4: 6421000c daddiu at,at,12
- 100001e8: 88250000 lwl a1,0\(at\)
- 100001ec: 98250003 lwr a1,3\(at\)
- 100001f0: 3c010000 lui at,0x0
- 100001f4: 003c082d daddu at,at,gp
- 100001f8: dc218058 ld at,-32680\(at\)
- 100001fc: 0031082d daddu at,at,s1
+ 10000184: 3c050000 lui a1,0x0
+ 10000188: 00bc282d daddu a1,a1,gp
+ 1000018c: dca58020 ld a1,-32736\(a1\)
+ 10000190: dca50000 ld a1,0\(a1\)
+ 10000194: 3c050000 lui a1,0x0
+ 10000198: 00bc282d daddu a1,a1,gp
+ 1000019c: dca58020 ld a1,-32736\(a1\)
+ 100001a0: dca5000c ld a1,12\(a1\)
+ 100001a4: 3c050000 lui a1,0x0
+ 100001a8: 00bc282d daddu a1,a1,gp
+ 100001ac: dca58020 ld a1,-32736\(a1\)
+ 100001b0: 00b1282d daddu a1,a1,s1
+ 100001b4: dca50000 ld a1,0\(a1\)
+ 100001b8: 3c050000 lui a1,0x0
+ 100001bc: 00bc282d daddu a1,a1,gp
+ 100001c0: dca58020 ld a1,-32736\(a1\)
+ 100001c4: 00b1282d daddu a1,a1,s1
+ 100001c8: dca5000c ld a1,12\(a1\)
+ 100001cc: 3c010000 lui at,0x0
+ 100001d0: 003c082d daddu at,at,gp
+ 100001d4: dc218020 ld at,-32736\(at\)
+ 100001d8: 0025082d daddu at,at,a1
+ 100001dc: dc250022 ld a1,34\(at\)
+ 100001e0: 3c010000 lui at,0x0
+ 100001e4: 003c082d daddu at,at,gp
+ 100001e8: dc218020 ld at,-32736\(at\)
+ 100001ec: 0025082d daddu at,at,a1
+ 100001f0: fc250038 sd a1,56\(at\)
+ 100001f4: 3c010000 lui at,0x0
+ 100001f8: 003c082d daddu at,at,gp
+ 100001fc: dc218020 ld at,-32736\(at\)
10000200: 88250000 lwl a1,0\(at\)
10000204: 98250003 lwr a1,3\(at\)
10000208: 3c010000 lui at,0x0
1000020c: 003c082d daddu at,at,gp
- 10000210: dc218058 ld at,-32680\(at\)
+ 10000210: dc218020 ld at,-32736\(at\)
10000214: 6421000c daddiu at,at,12
- 10000218: 0031082d daddu at,at,s1
- 1000021c: 88250000 lwl a1,0\(at\)
- 10000220: 98250003 lwr a1,3\(at\)
- 10000224: 3c010000 lui at,0x0
- 10000228: 003c082d daddu at,at,gp
- 1000022c: dc218058 ld at,-32680\(at\)
- 10000230: 64210022 daddiu at,at,34
- 10000234: 0025082d daddu at,at,a1
- 10000238: 88250000 lwl a1,0\(at\)
- 1000023c: 98250003 lwr a1,3\(at\)
- 10000240: 3c010000 lui at,0x0
- 10000244: 003c082d daddu at,at,gp
- 10000248: dc218058 ld at,-32680\(at\)
- 1000024c: 64210038 daddiu at,at,56
- 10000250: 0025082d daddu at,at,a1
- 10000254: a8250000 swl a1,0\(at\)
- 10000258: b8250003 swr a1,3\(at\)
- 1000025c: df858020 ld a1,-32736\(gp\)
- 10000260: 64a5071c daddiu a1,a1,1820
- 10000264: df858020 ld a1,-32736\(gp\)
- 10000268: 64a50728 daddiu a1,a1,1832
- 1000026c: df858028 ld a1,-32728\(gp\)
- 10000270: 64a5e95c daddiu a1,a1,-5796
- 10000274: df858020 ld a1,-32736\(gp\)
- 10000278: 64a5071c daddiu a1,a1,1820
- 1000027c: 00b1282d daddu a1,a1,s1
- 10000280: df858020 ld a1,-32736\(gp\)
- 10000284: 64a50728 daddiu a1,a1,1832
- 10000288: 00b1282d daddu a1,a1,s1
+ 10000218: 88250000 lwl a1,0\(at\)
+ 1000021c: 98250003 lwr a1,3\(at\)
+ 10000220: 3c010000 lui at,0x0
+ 10000224: 003c082d daddu at,at,gp
+ 10000228: dc218020 ld at,-32736\(at\)
+ 1000022c: 0031082d daddu at,at,s1
+ 10000230: 88250000 lwl a1,0\(at\)
+ 10000234: 98250003 lwr a1,3\(at\)
+ 10000238: 3c010000 lui at,0x0
+ 1000023c: 003c082d daddu at,at,gp
+ 10000240: dc218020 ld at,-32736\(at\)
+ 10000244: 6421000c daddiu at,at,12
+ 10000248: 0031082d daddu at,at,s1
+ 1000024c: 88250000 lwl a1,0\(at\)
+ 10000250: 98250003 lwr a1,3\(at\)
+ 10000254: 3c010000 lui at,0x0
+ 10000258: 003c082d daddu at,at,gp
+ 1000025c: dc218020 ld at,-32736\(at\)
+ 10000260: 64210022 daddiu at,at,34
+ 10000264: 0025082d daddu at,at,a1
+ 10000268: 88250000 lwl a1,0\(at\)
+ 1000026c: 98250003 lwr a1,3\(at\)
+ 10000270: 3c010000 lui at,0x0
+ 10000274: 003c082d daddu at,at,gp
+ 10000278: dc218020 ld at,-32736\(at\)
+ 1000027c: 64210038 daddiu at,at,56
+ 10000280: 0025082d daddu at,at,a1
+ 10000284: a8250000 swl a1,0\(at\)
+ 10000288: b8250003 swr a1,3\(at\)
1000028c: df858028 ld a1,-32728\(gp\)
- 10000290: 64a5e95c daddiu a1,a1,-5796
- 10000294: 00b1282d daddu a1,a1,s1
- 10000298: df858020 ld a1,-32736\(gp\)
- 1000029c: dca5071c ld a1,1820\(a1\)
- 100002a0: df858020 ld a1,-32736\(gp\)
- 100002a4: dca50728 ld a1,1832\(a1\)
- 100002a8: df858020 ld a1,-32736\(gp\)
+ 10000290: 64a5075c daddiu a1,a1,1884
+ 10000294: df858028 ld a1,-32728\(gp\)
+ 10000298: 64a50768 daddiu a1,a1,1896
+ 1000029c: df858030 ld a1,-32720\(gp\)
+ 100002a0: 64a5e99c daddiu a1,a1,-5732
+ 100002a4: df858028 ld a1,-32728\(gp\)
+ 100002a8: 64a5075c daddiu a1,a1,1884
100002ac: 00b1282d daddu a1,a1,s1
- 100002b0: dca5071c ld a1,1820\(a1\)
- 100002b4: df858020 ld a1,-32736\(gp\)
+ 100002b0: df858028 ld a1,-32728\(gp\)
+ 100002b4: 64a50768 daddiu a1,a1,1896
100002b8: 00b1282d daddu a1,a1,s1
- 100002bc: dca50728 ld a1,1832\(a1\)
- 100002c0: df818020 ld at,-32736\(gp\)
- 100002c4: 0025082d daddu at,at,a1
- 100002c8: dc25073e ld a1,1854\(at\)
- 100002cc: df818020 ld at,-32736\(gp\)
- 100002d0: 0025082d daddu at,at,a1
- 100002d4: fc250754 sd a1,1876\(at\)
- 100002d8: df818020 ld at,-32736\(gp\)
- 100002dc: 6421071c daddiu at,at,1820
- 100002e0: 88250000 lwl a1,0\(at\)
- 100002e4: 98250003 lwr a1,3\(at\)
- 100002e8: df818020 ld at,-32736\(gp\)
- 100002ec: 64210728 daddiu at,at,1832
- 100002f0: 88250000 lwl a1,0\(at\)
- 100002f4: 98250003 lwr a1,3\(at\)
- 100002f8: df818020 ld at,-32736\(gp\)
- 100002fc: 6421071c daddiu at,at,1820
- 10000300: 0031082d daddu at,at,s1
- 10000304: 88250000 lwl a1,0\(at\)
- 10000308: 98250003 lwr a1,3\(at\)
- 1000030c: df818020 ld at,-32736\(gp\)
- 10000310: 64210728 daddiu at,at,1832
- 10000314: 0031082d daddu at,at,s1
- 10000318: 88250000 lwl a1,0\(at\)
- 1000031c: 98250003 lwr a1,3\(at\)
- 10000320: df818020 ld at,-32736\(gp\)
- 10000324: 6421073e daddiu at,at,1854
- 10000328: 0025082d daddu at,at,a1
- 1000032c: 88250000 lwl a1,0\(at\)
- 10000330: 98250003 lwr a1,3\(at\)
- 10000334: df818020 ld at,-32736\(gp\)
- 10000338: 64210754 daddiu at,at,1876
- 1000033c: 0025082d daddu at,at,a1
- 10000340: a8250000 swl a1,0\(at\)
- 10000344: b8250003 swr a1,3\(at\)
- 10000348: 3c050000 lui a1,0x0
- 1000034c: 00bc282d daddu a1,a1,gp
- 10000350: dca58048 ld a1,-32696\(a1\)
- 10000354: df858030 ld a1,-32720\(gp\)
- 10000358: 64a500e0 daddiu a1,a1,224
- 1000035c: 3c190000 lui t9,0x0
- 10000360: 033cc82d daddu t9,t9,gp
- 10000364: df398048 ld t9,-32696\(t9\)
- 10000368: df998030 ld t9,-32720\(gp\)
- 1000036c: 673900e0 daddiu t9,t9,224
- 10000370: 3c190000 lui t9,0x0
- 10000374: 033cc82d daddu t9,t9,gp
- 10000378: df398048 ld t9,-32696\(t9\)
- 1000037c: 0320f809 jalr t9
- 10000380: 00000000 nop
- 10000384: df998030 ld t9,-32720\(gp\)
- 10000388: 673900e0 daddiu t9,t9,224
- 1000038c: 0320f809 jalr t9
- 10000390: 00000000 nop
- 10000394: 3c050000 lui a1,0x0
- 10000398: 00bc282d daddu a1,a1,gp
- 1000039c: dca58060 ld a1,-32672\(a1\)
- 100003a0: 3c050000 lui a1,0x0
- 100003a4: 00bc282d daddu a1,a1,gp
- 100003a8: dca58060 ld a1,-32672\(a1\)
- 100003ac: 64a5000c daddiu a1,a1,12
- 100003b0: 3c050000 lui a1,0x0
- 100003b4: 00bc282d daddu a1,a1,gp
- 100003b8: dca58060 ld a1,-32672\(a1\)
- 100003bc: 3c010002 lui at,0x2
- 100003c0: 6421e240 daddiu at,at,-7616
- 100003c4: 00a1282d daddu a1,a1,at
- 100003c8: 3c050000 lui a1,0x0
- 100003cc: 00bc282d daddu a1,a1,gp
- 100003d0: dca58060 ld a1,-32672\(a1\)
- 100003d4: 00b1282d daddu a1,a1,s1
- 100003d8: 3c050000 lui a1,0x0
- 100003dc: 00bc282d daddu a1,a1,gp
- 100003e0: dca58060 ld a1,-32672\(a1\)
- 100003e4: 64a5000c daddiu a1,a1,12
- 100003e8: 00b1282d daddu a1,a1,s1
- 100003ec: 3c050000 lui a1,0x0
- 100003f0: 00bc282d daddu a1,a1,gp
- 100003f4: dca58060 ld a1,-32672\(a1\)
- 100003f8: 3c010002 lui at,0x2
- 100003fc: 6421e240 daddiu at,at,-7616
- 10000400: 00a1282d daddu a1,a1,at
+ 100002bc: df858030 ld a1,-32720\(gp\)
+ 100002c0: 64a5e99c daddiu a1,a1,-5732
+ 100002c4: 00b1282d daddu a1,a1,s1
+ 100002c8: df858028 ld a1,-32728\(gp\)
+ 100002cc: dca5075c ld a1,1884\(a1\)
+ 100002d0: df858028 ld a1,-32728\(gp\)
+ 100002d4: dca50768 ld a1,1896\(a1\)
+ 100002d8: df858028 ld a1,-32728\(gp\)
+ 100002dc: 00b1282d daddu a1,a1,s1
+ 100002e0: dca5075c ld a1,1884\(a1\)
+ 100002e4: df858028 ld a1,-32728\(gp\)
+ 100002e8: 00b1282d daddu a1,a1,s1
+ 100002ec: dca50768 ld a1,1896\(a1\)
+ 100002f0: df818028 ld at,-32728\(gp\)
+ 100002f4: 0025082d daddu at,at,a1
+ 100002f8: dc25077e ld a1,1918\(at\)
+ 100002fc: df818028 ld at,-32728\(gp\)
+ 10000300: 0025082d daddu at,at,a1
+ 10000304: fc250794 sd a1,1940\(at\)
+ 10000308: df818028 ld at,-32728\(gp\)
+ 1000030c: 6421075c daddiu at,at,1884
+ 10000310: 88250000 lwl a1,0\(at\)
+ 10000314: 98250003 lwr a1,3\(at\)
+ 10000318: df818028 ld at,-32728\(gp\)
+ 1000031c: 64210768 daddiu at,at,1896
+ 10000320: 88250000 lwl a1,0\(at\)
+ 10000324: 98250003 lwr a1,3\(at\)
+ 10000328: df818028 ld at,-32728\(gp\)
+ 1000032c: 6421075c daddiu at,at,1884
+ 10000330: 0031082d daddu at,at,s1
+ 10000334: 88250000 lwl a1,0\(at\)
+ 10000338: 98250003 lwr a1,3\(at\)
+ 1000033c: df818028 ld at,-32728\(gp\)
+ 10000340: 64210768 daddiu at,at,1896
+ 10000344: 0031082d daddu at,at,s1
+ 10000348: 88250000 lwl a1,0\(at\)
+ 1000034c: 98250003 lwr a1,3\(at\)
+ 10000350: df818028 ld at,-32728\(gp\)
+ 10000354: 6421077e daddiu at,at,1918
+ 10000358: 0025082d daddu at,at,a1
+ 1000035c: 88250000 lwl a1,0\(at\)
+ 10000360: 98250003 lwr a1,3\(at\)
+ 10000364: df818028 ld at,-32728\(gp\)
+ 10000368: 64210794 daddiu at,at,1940
+ 1000036c: 0025082d daddu at,at,a1
+ 10000370: a8250000 swl a1,0\(at\)
+ 10000374: b8250003 swr a1,3\(at\)
+ 10000378: 3c050000 lui a1,0x0
+ 1000037c: 00bc282d daddu a1,a1,gp
+ 10000380: dca58038 ld a1,-32712\(a1\)
+ 10000384: df858040 ld a1,-32704\(gp\)
+ 10000388: 64a50110 daddiu a1,a1,272
+ 1000038c: 3c190000 lui t9,0x0
+ 10000390: 033cc82d daddu t9,t9,gp
+ 10000394: df398038 ld t9,-32712\(t9\)
+ 10000398: df998040 ld t9,-32704\(gp\)
+ 1000039c: 67390110 daddiu t9,t9,272
+ 100003a0: 3c190000 lui t9,0x0
+ 100003a4: 033cc82d daddu t9,t9,gp
+ 100003a8: df398038 ld t9,-32712\(t9\)
+ 100003ac: 0411ff58 bal 10000110 <fn>
+ 100003b0: 00000000 nop
+ 100003b4: df998040 ld t9,-32704\(gp\)
+ 100003b8: 67390110 daddiu t9,t9,272
+ 100003bc: 0411ff54 bal 10000110 <fn>
+ 100003c0: 00000000 nop
+ 100003c4: 3c050000 lui a1,0x0
+ 100003c8: 00bc282d daddu a1,a1,gp
+ 100003cc: dca58048 ld a1,-32696\(a1\)
+ 100003d0: 3c050000 lui a1,0x0
+ 100003d4: 00bc282d daddu a1,a1,gp
+ 100003d8: dca58048 ld a1,-32696\(a1\)
+ 100003dc: 64a5000c daddiu a1,a1,12
+ 100003e0: 3c050000 lui a1,0x0
+ 100003e4: 00bc282d daddu a1,a1,gp
+ 100003e8: dca58048 ld a1,-32696\(a1\)
+ 100003ec: 3c010001 lui at,0x1
+ 100003f0: 3421e240 ori at,at,0xe240
+ 100003f4: 00a1282d daddu a1,a1,at
+ 100003f8: 3c050000 lui a1,0x0
+ 100003fc: 00bc282d daddu a1,a1,gp
+ 10000400: dca58048 ld a1,-32696\(a1\)
10000404: 00b1282d daddu a1,a1,s1
10000408: 3c050000 lui a1,0x0
1000040c: 00bc282d daddu a1,a1,gp
- 10000410: dca58060 ld a1,-32672\(a1\)
- 10000414: dca50000 ld a1,0\(a1\)
- 10000418: 3c050000 lui a1,0x0
- 1000041c: 00bc282d daddu a1,a1,gp
- 10000420: dca58060 ld a1,-32672\(a1\)
- 10000424: dca5000c ld a1,12\(a1\)
- 10000428: 3c050000 lui a1,0x0
- 1000042c: 00bc282d daddu a1,a1,gp
- 10000430: dca58060 ld a1,-32672\(a1\)
+ 10000410: dca58048 ld a1,-32696\(a1\)
+ 10000414: 64a5000c daddiu a1,a1,12
+ 10000418: 00b1282d daddu a1,a1,s1
+ 1000041c: 3c050000 lui a1,0x0
+ 10000420: 00bc282d daddu a1,a1,gp
+ 10000424: dca58048 ld a1,-32696\(a1\)
+ 10000428: 3c010001 lui at,0x1
+ 1000042c: 3421e240 ori at,at,0xe240
+ 10000430: 00a1282d daddu a1,a1,at
10000434: 00b1282d daddu a1,a1,s1
- 10000438: dca50000 ld a1,0\(a1\)
- 1000043c: 3c050000 lui a1,0x0
- 10000440: 00bc282d daddu a1,a1,gp
- 10000444: dca58060 ld a1,-32672\(a1\)
- 10000448: 00b1282d daddu a1,a1,s1
- 1000044c: dca5000c ld a1,12\(a1\)
- 10000450: 3c010000 lui at,0x0
- 10000454: 003c082d daddu at,at,gp
- 10000458: dc218060 ld at,-32672\(at\)
- 1000045c: 0025082d daddu at,at,a1
- 10000460: dc250022 ld a1,34\(at\)
- 10000464: 3c010000 lui at,0x0
- 10000468: 003c082d daddu at,at,gp
- 1000046c: dc218060 ld at,-32672\(at\)
- 10000470: 0025082d daddu at,at,a1
- 10000474: fc250038 sd a1,56\(at\)
- 10000478: 3c010000 lui at,0x0
- 1000047c: 003c082d daddu at,at,gp
- 10000480: dc218060 ld at,-32672\(at\)
- 10000484: 88250000 lwl a1,0\(at\)
- 10000488: 98250003 lwr a1,3\(at\)
- 1000048c: 3c010000 lui at,0x0
- 10000490: 003c082d daddu at,at,gp
- 10000494: dc218060 ld at,-32672\(at\)
- 10000498: 6421000c daddiu at,at,12
- 1000049c: 88250000 lwl a1,0\(at\)
- 100004a0: 98250003 lwr a1,3\(at\)
- 100004a4: 3c010000 lui at,0x0
- 100004a8: 003c082d daddu at,at,gp
- 100004ac: dc218060 ld at,-32672\(at\)
- 100004b0: 0031082d daddu at,at,s1
+ 10000438: 3c050000 lui a1,0x0
+ 1000043c: 00bc282d daddu a1,a1,gp
+ 10000440: dca58048 ld a1,-32696\(a1\)
+ 10000444: dca50000 ld a1,0\(a1\)
+ 10000448: 3c050000 lui a1,0x0
+ 1000044c: 00bc282d daddu a1,a1,gp
+ 10000450: dca58048 ld a1,-32696\(a1\)
+ 10000454: dca5000c ld a1,12\(a1\)
+ 10000458: 3c050000 lui a1,0x0
+ 1000045c: 00bc282d daddu a1,a1,gp
+ 10000460: dca58048 ld a1,-32696\(a1\)
+ 10000464: 00b1282d daddu a1,a1,s1
+ 10000468: dca50000 ld a1,0\(a1\)
+ 1000046c: 3c050000 lui a1,0x0
+ 10000470: 00bc282d daddu a1,a1,gp
+ 10000474: dca58048 ld a1,-32696\(a1\)
+ 10000478: 00b1282d daddu a1,a1,s1
+ 1000047c: dca5000c ld a1,12\(a1\)
+ 10000480: 3c010000 lui at,0x0
+ 10000484: 003c082d daddu at,at,gp
+ 10000488: dc218048 ld at,-32696\(at\)
+ 1000048c: 0025082d daddu at,at,a1
+ 10000490: dc250022 ld a1,34\(at\)
+ 10000494: 3c010000 lui at,0x0
+ 10000498: 003c082d daddu at,at,gp
+ 1000049c: dc218048 ld at,-32696\(at\)
+ 100004a0: 0025082d daddu at,at,a1
+ 100004a4: fc250038 sd a1,56\(at\)
+ 100004a8: 3c010000 lui at,0x0
+ 100004ac: 003c082d daddu at,at,gp
+ 100004b0: dc218048 ld at,-32696\(at\)
100004b4: 88250000 lwl a1,0\(at\)
100004b8: 98250003 lwr a1,3\(at\)
100004bc: 3c010000 lui at,0x0
100004c0: 003c082d daddu at,at,gp
- 100004c4: dc218060 ld at,-32672\(at\)
+ 100004c4: dc218048 ld at,-32696\(at\)
100004c8: 6421000c daddiu at,at,12
- 100004cc: 0031082d daddu at,at,s1
- 100004d0: 88250000 lwl a1,0\(at\)
- 100004d4: 98250003 lwr a1,3\(at\)
- 100004d8: 3c010000 lui at,0x0
- 100004dc: 003c082d daddu at,at,gp
- 100004e0: dc218060 ld at,-32672\(at\)
- 100004e4: 64210022 daddiu at,at,34
- 100004e8: 0025082d daddu at,at,a1
- 100004ec: 88250000 lwl a1,0\(at\)
- 100004f0: 98250003 lwr a1,3\(at\)
- 100004f4: 3c010000 lui at,0x0
- 100004f8: 003c082d daddu at,at,gp
- 100004fc: dc218060 ld at,-32672\(at\)
- 10000500: 64210038 daddiu at,at,56
- 10000504: 0025082d daddu at,at,a1
- 10000508: a8250000 swl a1,0\(at\)
- 1000050c: b8250003 swr a1,3\(at\)
- 10000510: df858020 ld a1,-32736\(gp\)
- 10000514: 64a50794 daddiu a1,a1,1940
- 10000518: df858020 ld a1,-32736\(gp\)
- 1000051c: 64a507a0 daddiu a1,a1,1952
- 10000520: df858028 ld a1,-32728\(gp\)
- 10000524: 64a5e9d4 daddiu a1,a1,-5676
- 10000528: df858020 ld a1,-32736\(gp\)
- 1000052c: 64a50794 daddiu a1,a1,1940
- 10000530: 00b1282d daddu a1,a1,s1
- 10000534: df858020 ld a1,-32736\(gp\)
- 10000538: 64a507a0 daddiu a1,a1,1952
- 1000053c: 00b1282d daddu a1,a1,s1
+ 100004cc: 88250000 lwl a1,0\(at\)
+ 100004d0: 98250003 lwr a1,3\(at\)
+ 100004d4: 3c010000 lui at,0x0
+ 100004d8: 003c082d daddu at,at,gp
+ 100004dc: dc218048 ld at,-32696\(at\)
+ 100004e0: 0031082d daddu at,at,s1
+ 100004e4: 88250000 lwl a1,0\(at\)
+ 100004e8: 98250003 lwr a1,3\(at\)
+ 100004ec: 3c010000 lui at,0x0
+ 100004f0: 003c082d daddu at,at,gp
+ 100004f4: dc218048 ld at,-32696\(at\)
+ 100004f8: 6421000c daddiu at,at,12
+ 100004fc: 0031082d daddu at,at,s1
+ 10000500: 88250000 lwl a1,0\(at\)
+ 10000504: 98250003 lwr a1,3\(at\)
+ 10000508: 3c010000 lui at,0x0
+ 1000050c: 003c082d daddu at,at,gp
+ 10000510: dc218048 ld at,-32696\(at\)
+ 10000514: 64210022 daddiu at,at,34
+ 10000518: 0025082d daddu at,at,a1
+ 1000051c: 88250000 lwl a1,0\(at\)
+ 10000520: 98250003 lwr a1,3\(at\)
+ 10000524: 3c010000 lui at,0x0
+ 10000528: 003c082d daddu at,at,gp
+ 1000052c: dc218048 ld at,-32696\(at\)
+ 10000530: 64210038 daddiu at,at,56
+ 10000534: 0025082d daddu at,at,a1
+ 10000538: a8250000 swl a1,0\(at\)
+ 1000053c: b8250003 swr a1,3\(at\)
10000540: df858028 ld a1,-32728\(gp\)
- 10000544: 64a5e9d4 daddiu a1,a1,-5676
- 10000548: 00b1282d daddu a1,a1,s1
- 1000054c: df858020 ld a1,-32736\(gp\)
- 10000550: dca50794 ld a1,1940\(a1\)
- 10000554: df858020 ld a1,-32736\(gp\)
- 10000558: dca507a0 ld a1,1952\(a1\)
- 1000055c: df858020 ld a1,-32736\(gp\)
+ 10000544: 64a507d4 daddiu a1,a1,2004
+ 10000548: df858028 ld a1,-32728\(gp\)
+ 1000054c: 64a507e0 daddiu a1,a1,2016
+ 10000550: df858030 ld a1,-32720\(gp\)
+ 10000554: 64a5ea14 daddiu a1,a1,-5612
+ 10000558: df858028 ld a1,-32728\(gp\)
+ 1000055c: 64a507d4 daddiu a1,a1,2004
10000560: 00b1282d daddu a1,a1,s1
- 10000564: dca50794 ld a1,1940\(a1\)
- 10000568: df858020 ld a1,-32736\(gp\)
+ 10000564: df858028 ld a1,-32728\(gp\)
+ 10000568: 64a507e0 daddiu a1,a1,2016
1000056c: 00b1282d daddu a1,a1,s1
- 10000570: dca507a0 ld a1,1952\(a1\)
- 10000574: df818020 ld at,-32736\(gp\)
- 10000578: 0025082d daddu at,at,a1
- 1000057c: dc250794 ld a1,1940\(at\)
- 10000580: df818020 ld at,-32736\(gp\)
- 10000584: 0025082d daddu at,at,a1
- 10000588: fc2507cc sd a1,1996\(at\)
- 1000058c: df818020 ld at,-32736\(gp\)
- 10000590: 64210794 daddiu at,at,1940
- 10000594: 88250000 lwl a1,0\(at\)
- 10000598: 98250003 lwr a1,3\(at\)
- 1000059c: df818020 ld at,-32736\(gp\)
- 100005a0: 642107a0 daddiu at,at,1952
- 100005a4: 88250000 lwl a1,0\(at\)
- 100005a8: 98250003 lwr a1,3\(at\)
- 100005ac: df818020 ld at,-32736\(gp\)
- 100005b0: 64210794 daddiu at,at,1940
- 100005b4: 0031082d daddu at,at,s1
- 100005b8: 88250000 lwl a1,0\(at\)
- 100005bc: 98250003 lwr a1,3\(at\)
- 100005c0: df818020 ld at,-32736\(gp\)
- 100005c4: 642107a0 daddiu at,at,1952
- 100005c8: 0031082d daddu at,at,s1
- 100005cc: 88250000 lwl a1,0\(at\)
- 100005d0: 98250003 lwr a1,3\(at\)
- 100005d4: df818020 ld at,-32736\(gp\)
- 100005d8: 642107b6 daddiu at,at,1974
- 100005dc: 0025082d daddu at,at,a1
- 100005e0: 88250000 lwl a1,0\(at\)
- 100005e4: 98250003 lwr a1,3\(at\)
- 100005e8: df818020 ld at,-32736\(gp\)
- 100005ec: 642107cc daddiu at,at,1996
- 100005f0: 0025082d daddu at,at,a1
- 100005f4: a8250000 swl a1,0\(at\)
- 100005f8: b8250003 swr a1,3\(at\)
- 100005fc: 3c050000 lui a1,0x0
- 10000600: 00bc282d daddu a1,a1,gp
- 10000604: dca58050 ld a1,-32688\(a1\)
- 10000608: df858030 ld a1,-32720\(gp\)
- 1000060c: 64a506e0 daddiu a1,a1,1760
- 10000610: 3c190000 lui t9,0x0
- 10000614: 033cc82d daddu t9,t9,gp
- 10000618: df398050 ld t9,-32688\(t9\)
- 1000061c: df998030 ld t9,-32720\(gp\)
- 10000620: 673906e0 daddiu t9,t9,1760
- 10000624: 3c190000 lui t9,0x0
- 10000628: 033cc82d daddu t9,t9,gp
- 1000062c: df398050 ld t9,-32688\(t9\)
- 10000630: 0320f809 jalr t9
- 10000634: 00000000 nop
- 10000638: df998030 ld t9,-32720\(gp\)
- 1000063c: 673906e0 daddiu t9,t9,1760
- 10000640: 0320f809 jalr t9
- 10000644: 00000000 nop
- 10000648: 3c050000 lui a1,0x0
- 1000064c: 00bc282d daddu a1,a1,gp
- 10000650: dca58058 ld a1,-32680\(a1\)
- 10000654: 1000fea2 b 100000e0 <fn>
- 10000658: 00000000 nop
- 1000065c: 3c050000 lui a1,0x0
- 10000660: 00bc282d daddu a1,a1,gp
- 10000664: dca58060 ld a1,-32672\(a1\)
- 10000668: dca50000 ld a1,0\(a1\)
- 1000066c: 1000001c b 100006e0 <fn2>
- 10000670: 00000000 nop
- 10000674: df858020 ld a1,-32736\(gp\)
- 10000678: 64a5071c daddiu a1,a1,1820
- 1000067c: 1000fe98 b 100000e0 <fn>
- 10000680: 00000000 nop
- 10000684: df858020 ld a1,-32736\(gp\)
- 10000688: 64a507a0 daddiu a1,a1,1952
- 1000068c: 10000014 b 100006e0 <fn2>
- 10000690: 00000000 nop
- 10000694: df858028 ld a1,-32728\(gp\)
- 10000698: 64a5e95c daddiu a1,a1,-5796
- 1000069c: 1000fe90 b 100000e0 <fn>
+ 10000570: df858030 ld a1,-32720\(gp\)
+ 10000574: 64a5ea14 daddiu a1,a1,-5612
+ 10000578: 00b1282d daddu a1,a1,s1
+ 1000057c: df858028 ld a1,-32728\(gp\)
+ 10000580: dca507d4 ld a1,2004\(a1\)
+ 10000584: df858028 ld a1,-32728\(gp\)
+ 10000588: dca507e0 ld a1,2016\(a1\)
+ 1000058c: df858028 ld a1,-32728\(gp\)
+ 10000590: 00b1282d daddu a1,a1,s1
+ 10000594: dca507d4 ld a1,2004\(a1\)
+ 10000598: df858028 ld a1,-32728\(gp\)
+ 1000059c: 00b1282d daddu a1,a1,s1
+ 100005a0: dca507e0 ld a1,2016\(a1\)
+ 100005a4: df818028 ld at,-32728\(gp\)
+ 100005a8: 0025082d daddu at,at,a1
+ 100005ac: dc2507f6 ld a1,2038\(at\)
+ 100005b0: df818028 ld at,-32728\(gp\)
+ 100005b4: 0025082d daddu at,at,a1
+ 100005b8: fc25080c sd a1,2060\(at\)
+ 100005bc: df818028 ld at,-32728\(gp\)
+ 100005c0: 642107d4 daddiu at,at,2004
+ 100005c4: 88250000 lwl a1,0\(at\)
+ 100005c8: 98250003 lwr a1,3\(at\)
+ 100005cc: df818028 ld at,-32728\(gp\)
+ 100005d0: 642107e0 daddiu at,at,2016
+ 100005d4: 88250000 lwl a1,0\(at\)
+ 100005d8: 98250003 lwr a1,3\(at\)
+ 100005dc: df818028 ld at,-32728\(gp\)
+ 100005e0: 642107d4 daddiu at,at,2004
+ 100005e4: 0031082d daddu at,at,s1
+ 100005e8: 88250000 lwl a1,0\(at\)
+ 100005ec: 98250003 lwr a1,3\(at\)
+ 100005f0: df818028 ld at,-32728\(gp\)
+ 100005f4: 642107e0 daddiu at,at,2016
+ 100005f8: 0031082d daddu at,at,s1
+ 100005fc: 88250000 lwl a1,0\(at\)
+ 10000600: 98250003 lwr a1,3\(at\)
+ 10000604: df818028 ld at,-32728\(gp\)
+ 10000608: 642107f6 daddiu at,at,2038
+ 1000060c: 0025082d daddu at,at,a1
+ 10000610: 88250000 lwl a1,0\(at\)
+ 10000614: 98250003 lwr a1,3\(at\)
+ 10000618: df818028 ld at,-32728\(gp\)
+ 1000061c: 6421080c daddiu at,at,2060
+ 10000620: 0025082d daddu at,at,a1
+ 10000624: a8250000 swl a1,0\(at\)
+ 10000628: b8250003 swr a1,3\(at\)
+ 1000062c: 3c050000 lui a1,0x0
+ 10000630: 00bc282d daddu a1,a1,gp
+ 10000634: dca58050 ld a1,-32688\(a1\)
+ 10000638: df858040 ld a1,-32704\(gp\)
+ 1000063c: 64a50710 daddiu a1,a1,1808
+ 10000640: 3c190000 lui t9,0x0
+ 10000644: 033cc82d daddu t9,t9,gp
+ 10000648: df398050 ld t9,-32688\(t9\)
+ 1000064c: df998040 ld t9,-32704\(gp\)
+ 10000650: 67390710 daddiu t9,t9,1808
+ 10000654: 3c190000 lui t9,0x0
+ 10000658: 033cc82d daddu t9,t9,gp
+ 1000065c: df398050 ld t9,-32688\(t9\)
+ 10000660: 0411002b bal 10000710 <fn2>
+ 10000664: 00000000 nop
+ 10000668: df998040 ld t9,-32704\(gp\)
+ 1000066c: 67390710 daddiu t9,t9,1808
+ 10000670: 04110027 bal 10000710 <fn2>
+ 10000674: 00000000 nop
+ 10000678: 3c050000 lui a1,0x0
+ 1000067c: 00bc282d daddu a1,a1,gp
+ 10000680: dca58020 ld a1,-32736\(a1\)
+ 10000684: 1000fea2 b 10000110 <fn>
+ 10000688: 00000000 nop
+ 1000068c: 3c050000 lui a1,0x0
+ 10000690: 00bc282d daddu a1,a1,gp
+ 10000694: dca58048 ld a1,-32696\(a1\)
+ 10000698: dca50000 ld a1,0\(a1\)
+ 1000069c: 1000001c b 10000710 <fn2>
100006a0: 00000000 nop
- 100006a4: df858020 ld a1,-32736\(gp\)
- 100006a8: dca50794 ld a1,1940\(a1\)
- 100006ac: 1000000c b 100006e0 <fn2>
+ 100006a4: df858028 ld a1,-32728\(gp\)
+ 100006a8: 64a5075c daddiu a1,a1,1884
+ 100006ac: 1000fe98 b 10000110 <fn>
100006b0: 00000000 nop
- 100006b4: df858020 ld a1,-32736\(gp\)
- 100006b8: dca50728 ld a1,1832\(a1\)
- 100006bc: 1000fe88 b 100000e0 <fn>
+ 100006b4: df858028 ld a1,-32728\(gp\)
+ 100006b8: 64a507e0 daddiu a1,a1,2016
+ 100006bc: 10000014 b 10000710 <fn2>
100006c0: 00000000 nop
- 100006c4: df818020 ld at,-32736\(gp\)
- 100006c8: 0025082d daddu at,at,a1
- 100006cc: dc2507b6 ld a1,1974\(at\)
- 100006d0: 10000003 b 100006e0 <fn2>
- 100006d4: 00000000 nop
+ 100006c4: df858030 ld a1,-32720\(gp\)
+ 100006c8: 64a5e99c daddiu a1,a1,-5732
+ 100006cc: 1000fe90 b 10000110 <fn>
+ 100006d0: 00000000 nop
+ 100006d4: df858028 ld a1,-32728\(gp\)
+ 100006d8: dca507d4 ld a1,2004\(a1\)
+ 100006dc: 1000000c b 10000710 <fn2>
+ 100006e0: 00000000 nop
+ 100006e4: df858028 ld a1,-32728\(gp\)
+ 100006e8: dca50768 ld a1,1896\(a1\)
+ 100006ec: 1000fe88 b 10000110 <fn>
+ 100006f0: 00000000 nop
+ 100006f4: df818028 ld at,-32728\(gp\)
+ 100006f8: 0025082d daddu at,at,a1
+ 100006fc: dc2507f6 ld a1,2038\(at\)
+ 10000700: 10000003 b 10000710 <fn2>
+ 10000704: 00000000 nop
+ \.\.\.
+
+0000000010000710 <fn2>:
\.\.\.
Disassembly of section \.data:
-00000000101006e0 <_fdata>:
+0000000010010720 <_fdata>:
\.\.\.
-000000001010071c <dg1>:
+000000001001075c <dg1>:
\.\.\.
-0000000010100758 <sp2>:
+0000000010010798 <sp2>:
\.\.\.
-0000000010100794 <dg2>:
+00000000100107d4 <dg2>:
\.\.\.
Disassembly of section \.got:
-00000000101007d0 <_GLOBAL_OFFSET_TABLE_>:
+0000000010010810 <_GLOBAL_OFFSET_TABLE_>:
+ \.\.\.
+ 10010818: 80000000 .*
\.\.\.
- 101007d8: 80000000 .*
- 101007dc: 00000000 .*
- 101007e0: 00000000 .*
- 101007e4: 10100000 .*
- 101007e8: 00000000 .*
- 101007ec: 10120000 .*
- 101007f0: 00000000 .*
- 101007f4: 10000000 .*
- 101007f8: 00000000 .*
+ 10010824: 1001075c .*
+ 10010828: 00000000 .*
+ 1001082c: 10010000 .*
+ 10010830: 00000000 .*
+ 10010834: 10030000 .*
+ 10010838: 00000000 .*
+ 1001083c: 10000110 .*
+ 10010840: 00000000 .*
+ 10010844: 10000000 .*
+ 10010848: 00000000 .*
+ 1001084c: 100107d4 .*
+ 10010850: 00000000 .*
+ 10010854: 10000710 .*
+ 10010858: 00000000 .*
\.\.\.
- 1010080c: 100000e0 .*
- 10100810: 00000000 .*
- 10100814: 100006e0 .*
- 10100818: 00000000 .*
- 1010081c: 1010071c .*
- 10100820: 00000000 .*
- 10100824: 10100794 .*
#name: Emit relocs 1
-#source: emit-relocs-1a.s -mabi=n32 -EB
-#source: emit-relocs-1b.s -mabi=n32 -EB
+#source: emit-relocs-1a.s -march=from-abi -mabi=n32 -EB
+#source: emit-relocs-1b.s -march=from-abi -mabi=n32 -EB
#ld: -q -T emit-relocs-1.ld -melf32btsmipn32
#objdump: -sr
.text
+ .align 4
.globl _start
_start:
jr $31
D: .4byte 0x200
.data
+ .align 4
E: .4byte E
.4byte E + 0x1000
.4byte A
D: .4byte 0x200
.data
+ .align 4
E: .4byte E
.4byte E + 0x1000
.4byte A
. = 0x60000;
.data : { *(.data) }
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
}
. = 0x1236000000000;
.data : { *(.data) }
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
}
.text : { *(.text) }
. = ALIGN (0x10000);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = ALIGN (0x400);
#name: GOT page test 2
#source: got-page-2.s
-#as: -EB -n32
+#as: -march=from-abi -EB -n32
#ld: -T got-page-1.ld -shared -melf32btsmipn32
#readelf: -d
#
nop
jal s2
nop
- nop
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
SORT(CONSTRUCTORS)
}
.data1 : { *(.data1) }
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN(16) + 0x7ff0);
.got : { *(.got.plt) *(.got) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
return
}
-set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]]
+set has_newabi [expr [istarget *-*-irix6*] \
+ || [istarget mips*-*-linux*] \
+ || [istarget mips*-sde-elf*]]
set linux_gnu [expr [istarget mips*-*-linux*]]
set embedded_elf [expr [istarget mips*-*-elf]]
+# Set defaults.
+set abi_asflags(o32) ""
+set abi_asflags(n32) "-march=from-abi -n32 -EB"
+set abi_asflags(n64) "-march=from-abi -64 -EB"
+set abi_ldflags(o32) ""
+set abi_ldflags(n32) -melf32bmipn32
+set abi_ldflags(n64) -melf64bmip
+
+# Override as needed.
+if { [istarget *-*-irix6*] } {
+ set abi_asflags(o32) "-32 -EB"
+ set abi_ldflags(o32) -melf32bsmip
+} elseif { [istarget mips64*-linux*] } {
+ set abi_asflags(o32) "-32 -EB"
+ set abi_ldflags(o32) -melf32btsmip
+} elseif { [istarget mips64*-*freebsd*] } {
+ set abi_asflags(o32) "-32 -EB"
+ set abi_ldflags(o32) -melf32btsmip_fbsd
+}
+if { [istarget mips*-*-linux*] || [istarget mips*-sde-elf*] } {
+ set abi_ldflags(n32) -melf32btsmipn32
+ set abi_ldflags(n64) -melf64btsmip
+} elseif { [istarget mips64*-*freebsd*] } {
+ set abi_ldflags(n32) -melf32btsmipn32_fbsd
+ set abi_ldflags(n64) -melf64btsmip_fbsd
+}
+
if { $linux_gnu } {
run_ld_link_tests [list \
[list "Dummy shared library for MIPS16 PIC test 1" \
"mips16-pic-4"]]
}
-if { [istarget mips64*-linux-gnu] } {
- set o32_as_flags "-32 -EB"
- set o32_ld_flags "-melf32btsmip"
-} elseif { [istarget mips64*-*freebsd*] } {
- set o32_as_flags "-32 -EB"
- set o32_ld_flags "-melf32btsmip_fbsd"
-} else {
- set o32_as_flags ""
- set o32_ld_flags ""
-}
-
# Check MIPS16 markings being passed through link.
run_dump_test "mips16-1"
}
if $has_newabi {
- run_dump_test "elf-rel-got-n32"
- run_dump_test "elf-rel-xgot-n32"
+ if { $embedded_elf } {
+ run_dump_test "elf-rel-got-n32-embed" \
+ [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "elf-rel-xgot-n32-embed" \
+ [list [list ld $abi_ldflags(n32)]]
+ } else {
+ run_dump_test "elf-rel-got-n32" [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "elf-rel-xgot-n32" [list [list ld $abi_ldflags(n32)]]
+ }
if { $linux_gnu } {
- run_dump_test "elf-rel-got-n64-linux"
- run_dump_test "elf-rel-xgot-n64-linux"
+ run_dump_test "elf-rel-got-n64-linux" \
+ [list [list ld $abi_ldflags(n64)]]
+ run_dump_test "elf-rel-xgot-n64-linux" \
+ [list [list ld $abi_ldflags(n64)]]
+ } elseif { $embedded_elf } {
+ run_dump_test "elf-rel-got-n64-embed" \
+ [list [list ld $abi_ldflags(n64)]]
+ run_dump_test "elf-rel-xgot-n64-embed" \
+ [list [list ld $abi_ldflags(n64)]]
} else {
- run_dump_test "elf-rel-got-n64"
- run_dump_test "elf-rel-xgot-n64"
+ run_dump_test "elf-rel-got-n64" [list [list ld $abi_ldflags(n64)]]
+ run_dump_test "elf-rel-xgot-n64" [list [list ld $abi_ldflags(n64)]]
}
run_dump_test "relax-jalr-n32"
"readelf --symbols pic-and-nonpic-6-${abi}.nd" \
"readelf -d pic-and-nonpic-6-${abi}.ad"] \
"pic-and-nonpic-6-${abi}"]]
+
+ # This checks whether our linker scripts get the scope of _gp right,
+ # and must therefore use default scripts. If they don't, then -- in
+ # addition to dumps failing to match -- the final link fails with:
+ #
+ # ld: gp-hidden.o: undefined reference to symbol '_gp'
+ # ld: note: '_gp' is defined in DSO ./tmpdir/gp-hidden-lib-${abi}.so
+ # so try adding it to the linker command line
+ #
+ set suff64 [string map {o32 "" n32 "" n64 -64} $abi]
+ run_ld_link_tests [list \
+ [list \
+ "_gp scope test ($abi shared library)" \
+ "$abi_ldflags($abi) -shared" \
+ "$abi_asflags($abi) -KPIC" \
+ { gp-hidden-lib.s } \
+ [list \
+ "readelf --relocs gp-hidden-lib${suff64}.rd" \
+ "readelf --syms gp-hidden.sd"] \
+ "gp-hidden-lib-${abi}.so"] \
+ [list \
+ "_gp scope test ($abi versioned library)" \
+ "$abi_ldflags($abi) -shared -version-script gp-hidden-ver.ver tmpdir/gp-hidden-lib-${abi}.so" \
+ "$abi_asflags($abi) -KPIC" \
+ { gp-hidden-ver.s } \
+ [list \
+ "readelf --relocs gp-hidden-ver${suff64}.rd" \
+ "readelf --syms gp-hidden.sd"] \
+ "gp-hidden-ver-${abi}.so"] \
+ [list \
+ "_gp scope test ($abi executable)" \
+ "$abi_ldflags($abi) -e 0 -rpath-link . tmpdir/gp-hidden-ver-${abi}.so" \
+ "$abi_asflags($abi) -call_nonpic" \
+ { gp-hidden.s } \
+ [list \
+ "readelf --relocs gp-hidden${suff64}.rd" \
+ "readelf --syms gp-hidden.sd"] \
+ "gp-hidden-${abi}"]]
}
}
run_dump_test "reloc-1-rel"
}
if $has_newabi {
- run_dump_test "reloc-1-n32"
- if $linux_gnu {
- # Uses a linux-specific ld -m switch
- run_dump_test "reloc-1-n64"
- }
+ run_dump_test "reloc-1-n32" [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "reloc-1-n64" [list [list ld $abi_ldflags(n64)]]
}
run_dump_test "reloc-2"
run_dump_test "reloc-merge-lo16"
run_dump_test "reloc-4"
run_dump_test "reloc-5"
if { $has_newabi } {
- run_ld_link_tests {
- {"reloc test 6a" "-shared"
- "-n32" "reloc-6a.s"
- {}
- "reloc-6a.so"}
- {"reloc test 6b" "tmpdir/reloc-6a.so"
- "-n32" "reloc-6b.s"
- {}
- "reloc-6b"}
- }
+ run_ld_link_tests [list \
+ [list \
+ "reloc test 6a" \
+ "-shared $abi_ldflags(n32)" \
+ "$abi_asflags(n32)" \
+ "reloc-6a.s" \
+ {} \
+ "reloc-6a.so"] \
+ [list \
+ "reloc test 6b" \
+ "$abi_ldflags(n32) tmpdir/reloc-6a.so" \
+ "$abi_asflags(n32)" \
+ "reloc-6b.s" \
+ {} \
+ "reloc-6b"]]
}
if {$has_newabi && $linux_gnu} {
run_dump_test "jaloverflow"
run_dump_test "jaloverflow-2"
if {$has_newabi} {
- run_dump_test "jalbal"
+ run_dump_test "jalbal" [list [list ld $abi_ldflags(n32)]]
}
run_dump_test "mode-change-error-1"
#
# the null symbol entry
# the .MIPS.stubs section symbol
- # _gp
# _GLOBAL_OFFSET_TABLE_
- set base_syms 4
+ set base_syms 3
foreach dynsym { 7fff 8000 fff0 10000 2fe80 } {
run_ld_link_tests \
[list [list \
set mips16_call_global_test [list \
[list "Global calls from mips16" \
- "$o32_ld_flags -T no-shared-1.ld" \
- "$o32_as_flags -mips32r2" \
+ "$abi_ldflags(o32) -T no-shared-1.ld" \
+ "$abi_asflags(o32) -mips32r2" \
{mips16-call-global-1.s mips16-call-global-2.s mips16-call-global-3.s} \
{{objdump -dr mips16-call-global.d}} \
"mips16-call-global"]]
set mips16_intermix_test [list \
[list "Intermixing mips32 and mips16 functions" \
- "$o32_ld_flags" \
- "$o32_as_flags -mips32r2" \
+ "$abi_ldflags(o32)" \
+ "$abi_asflags(o32) -mips32r2" \
{mips16-intermix-1.s mips16-intermix-2.s} \
{{objdump -t mips16-intermix.d}} \
"mips16-intermix"]]
# MIPS16 and microMIPS interlinking test.
run_dump_test "mips16-and-micromips"
+
+# Export class call relocation tests.
+set abis [concat o32 [expr {$has_newabi ? "n32 n64" : ""}]]
+foreach { abi } $abis {
+ set loadaddr [string map \
+ {o32 0x12340000 n32 0x12340000 n64 0x123456789abc0000} $abi]
+ set suff [subst \
+ [expr { [istarget *-*-irix*] \
+ ? [string map {o32 o32-irix n32 n32 n64 n64} $abi] \
+ : $abi }]]
+ run_ld_link_tests [list \
+ [list \
+ "MIPS export class call relocation test ($abi)" \
+ "$abi_ldflags($abi) -shared -Ttext $loadaddr -T export-class-call16.ld" \
+ "$abi_asflags($abi) -mips3 -KPIC" \
+ [list export-class-call16-${abi}.s export-class-call16-def.s] \
+ [list \
+ "objdump -d export-class-call16-${suff}.dd" \
+ "readelf -A export-class-call16-${abi}.gd"] \
+ "export-class-call16-${abi}.so"]]
+}
SORT(CONSTRUCTORS)
}
.data1 : { *(.data1) }
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN(16) + 0x7ff0);
.got : { *(.got.plt) *(.got) }
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
.rel.plt : { *(.rel.plt) }
.rel.dyn : { *(.rel.dyn) }
. = 0x50000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0x50400;
.data : { *(.data) }
# [MIPS_GOTSYM, MIPS_SYMTABNO) covers used4...used7.
#...
- .* \(MIPS_SYMTABNO\) * 10
+ .* \(MIPS_SYMTABNO\) * 9
#...
- .* \(MIPS_GOTSYM\) * 0x6
+ .* \(MIPS_GOTSYM\) * 0x5
#pass
# used8 should come before MIPS_GOTSYM.
#...
- +4: 000405bc +36 +FUNC +GLOBAL +DEFAULT .* used8
- +5: .* _GLOBAL_OFFSET_TABLE_
- +6: 00040574 +36 +FUNC +GLOBAL +DEFAULT .* used6
- +7: 00040598 +36 +FUNC +GLOBAL +DEFAULT .* used7
- +8: 00040550 +36 +FUNC +GLOBAL +DEFAULT .* used5
- +9: 0004052c +36 +FUNC +GLOBAL +DEFAULT .* used4
+ +3: 000405bc +36 +FUNC +GLOBAL +DEFAULT .* used8
+ +4: .* _GLOBAL_OFFSET_TABLE_
+ +5: 00040574 +36 +FUNC +GLOBAL +DEFAULT .* used6
+ +6: 00040598 +36 +FUNC +GLOBAL +DEFAULT .* used7
+ +7: 00040550 +36 +FUNC +GLOBAL +DEFAULT .* used5
+ +8: 0004052c +36 +FUNC +GLOBAL +DEFAULT .* used4
#pass
#source: mode-change-error-1a.s
#source: mode-change-error-1b.s
#ld: -e 0x8000000
-#error: .*: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled.
+#error: .*: Unsupported jump between ISA modes; consider recompiling with interlinking enabled.
-#as: -mabi=n32 -EB
+#as: -march=from-abi -mabi=n32 -EB
#source: no-shared-1-o32.s
#ld: -melf32btsmipn32 -T no-shared-1.ld
#objdump: -dr -j.text -j.data -j.got
-#as: -mabi=64 -EB
+#as: -march=from-abi -mabi=64 -EB
#ld: -melf64btsmip -T no-shared-1.ld
#objdump: -dr -j.text -j.data -j.got
. = 0x60000;
.data : { *(.data) }
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
}
.pdr : { *(.pdr) }
. = 0x41000;
.text : { *(.text) }
- _gp = 0x68000;
+ HIDDEN (_gp = 0x68000);
}
#...
+.*: 00068000 +0 +NOTYPE +LOCAL +DEFAULT +ABS _gp
.*: 00041018 +8 +FUNC +LOCAL +DEFAULT .* .pic.f1
.*: 00041000 +16 +FUNC +LOCAL +DEFAULT .* .pic.f2
.*: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +UND _gp_disp
-.*: 00068000 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _gp
.*: 00041050 +14 +FUNC +GLOBAL +DEFAULT +\[MIPS16\] .* f3
.*: 00041060 +24 +FUNC +GLOBAL +DEFAULT .* __start
.*: 0004103c +20 +FUNC +GLOBAL +DEFAULT .* f2
c00: 8f998010 lw t9,-32752\(gp\)
c04: 03e07821 move t7,ra
c08: 0320f809 jalr t9
- c0c: 24180007 li t8,7
+ c0c: 24180006 li t8,6
\.\.\.
.data : { *(.data) }
. = ALIGN (0x400);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
}
# This must be the number of GOT entries - 1, the last entry being for "bar".
0x7000000a \(MIPS_LOCAL_GOTNO\) * 3
# This must be MIPS_GOTSYM + 1.
- 0x70000011 \(MIPS_SYMTABNO\) * 8
+ 0x70000011 \(MIPS_SYMTABNO\) * 7
0x70000012 \(MIPS_UNREFEXTNO\) .*
# This must be the index of "bar".
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43000
0x00000002 \(PLTRELSZ\) * 8 \(bytes\)
.*: 8f998010 lw t9,-32752\(gp\)
.*: 03e07821 move t7,ra
.*: 0320f809 jalr t9
-.*: 24180007 li t8,7
+.*: 24180006 li t8,6
\.\.\.
.got.plt : { *(.got.plt) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
.*: 00000000 +0 +FUNC +GLOBAL +DEFAULT +UND +foo
# The index on the next line should correspond to MIPS_GOTSYM.
#...
- *7: 00044030 +0 +FUNC +GLOBAL +DEFAULT +UND +bar
+ *6: 00044030 +0 +FUNC +GLOBAL +DEFAULT +UND +bar
#pass
Relocation section '\.rel\.plt' at offset .* contains .*:
* Offset * Info * Type * Sym\.Value * Sym\. Name
-00081008 * 0000057f * R_MIPS_JUMP_SLOT * 00000000 * foo
+00081008 * 0000047f * R_MIPS_JUMP_SLOT * 00000000 * foo
# This must be the number of GOT entries - 1, the last entry being for "obj3".
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
# This must be MIPS_GOTSYM + 1.
- 0x70000011 \(MIPS_SYMTABNO\) * 8
+ 0x70000011 \(MIPS_SYMTABNO\) * 7
0x70000012 \(MIPS_UNREFEXTNO\) .*
# This must be the index of "obj3".
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000000 \(NULL\) * 0x0
.rld_map : { *(.rld_map) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
.*: 000a2008 +4 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +obj2
# The index on the next line should correspond to MIPS_GOTSYM.
#...
- *7: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj3
+ *6: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj3
#pass
* Offset * Info * Type * Sym\.Value * Sym\. Name
00000000 * 00000000 * R_MIPS_NONE *
000a2000 * 0000017e * R_MIPS_COPY * 000a2000 * obj1
-000a2008 * 0000047e * R_MIPS_COPY * 000a2008 * obj2
-000a1004 * 00000703 * R_MIPS_REL32 * 00000000 * obj3
+000a2008 * 0000037e * R_MIPS_COPY * 000a2008 * obj2
+000a1004 * 00000603 * R_MIPS_REL32 * 00000000 * obj3
# for "bar" and "obj2".
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
# This must be MIPS_GOTSYM + 2.
- 0x70000011 \(MIPS_SYMTABNO\) * 10
+ 0x70000011 \(MIPS_SYMTABNO\) * 9
0x70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x70000013 \(MIPS_GOTSYM\) * 0x8
+ 0x70000013 \(MIPS_GOTSYM\) * 0x7
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43030
0x00000002 \(PLTRELSZ\) * 8 \(bytes\)
.got.plt : { *(.got.plt) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
.*: 00043060 +0 +FUNC +GLOBAL +DEFAULT +\[MIPS PLT\] +UND +foo
# The index on the next line should correspond to MIPS_GOTSYM.
#...
- *8: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj2
- *9: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +bar
+ *7: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj2
+ *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +bar
#pass
0x70000005 \(MIPS_FLAGS\) * NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x70000011 \(MIPS_SYMTABNO\) * 14
+ 0x70000011 \(MIPS_SYMTABNO\) * 13
0x70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43028
0x00000002 \(PLTRELSZ\) * 24 \(bytes\)
440a0: 8f998010 lw t9,-32752\(gp\)
440a4: 03e07821 move t3,ra
440a8: 0320f809 jalr t9
- 440ac: 2418000a li t8,10
+ 440ac: 24180009 li t8,9
\.\.\.
# and the remaining symbols should have the same order as the
# GOT layout given in the *.dd dump.
#...
- *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
- *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
- *9: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
- *10: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
- *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
- *12: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
- *13: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
+ *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
+ *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
+ *8: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
+ *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
+ *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
+ *11: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
+ *12: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
#pass
0x0+70000005 \(MIPS_FLAGS\) * NOTPOT
0x0+70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x0+70000011 \(MIPS_SYMTABNO\) * 14
+ 0x0+70000011 \(MIPS_SYMTABNO\) * 13
0x0+70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x0+70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x0+70000013 \(MIPS_GOTSYM\) * 0x6
0x0+00000014 \(PLTREL\) * REL
0x0+00000017 \(JMPREL\) * 0x43050
0x0+00000002 \(PLTRELSZ\) * 48 \(bytes\)
440a0: df998010 ld t9,-32752\(gp\)
440a4: 03e0782d move t3,ra
440a8: 0320f809 jalr t9
- 440ac: 6418000a daddiu t8,zero,10
+ 440ac: 64180009 daddiu t8,zero,9
\.\.\.
# and the remaining symbols should have the same order as the
# GOT layout given in the *.dd dump.
#...
- *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
- *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
- *9: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
- *10: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
- *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
- *12: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
- *13: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
+ *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
+ *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
+ *8: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
+ *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
+ *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
+ *11: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
+ *12: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
#pass
0x70000005 \(MIPS_FLAGS\) * NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x70000011 \(MIPS_SYMTABNO\) * 14
+ 0x70000011 \(MIPS_SYMTABNO\) * 13
0x70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43028
0x00000002 \(PLTRELSZ\) * 24 \(bytes\)
440a0: 8f998010 lw t9,-32752\(gp\)
440a4: 03e07821 move t7,ra
440a8: 0320f809 jalr t9
- 440ac: 2418000a li t8,10
+ 440ac: 24180009 li t8,9
\.\.\.
# and the remaining symbols should have the same order as the
# GOT layout given in the *.dd dump.
#...
- *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
- *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
- *9: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
- *10: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
- *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
- *12: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
- *13: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
+ *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
+ *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
+ *8: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
+ *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
+ *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
+ *11: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
+ *12: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
#pass
.got.plt : { *(.got.plt) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
#name: MIPS rel32 n32
#source: rel32.s
-#as: -KPIC -EB -n32
+#as: -march=from-abi -KPIC -EB -n32
#readelf: -x .text -r
#ld: -shared -melf32btsmipn32
[0-9a-f ]+R_MIPS_REL32
Hex dump of section '.text':
- 0x000002e0 00000000 00000000 00000000 00000000 ................
- 0x000002f0 000002f0 00000000 00000000 00000000 ................
- 0x00000300 00000000 00000000 00000000 00000000 ................
+ 0x000002d0 00000000 00000000 00000000 00000000 ................
+ 0x000002e0 000002e0 00000000 00000000 00000000 ................
+ 0x000002f0 00000000 00000000 00000000 00000000 ................
[0-9a-f ]+R_MIPS_REL32
Hex dump of section '.text':
+ 0x000002c0 00000000 00000000 00000000 00000000 ................
+ 0x000002d0 000002d0 00000000 00000000 00000000 ................
0x000002e0 00000000 00000000 00000000 00000000 ................
- 0x000002f0 000002f0 00000000 00000000 00000000 ................
- 0x00000300 00000000 00000000 00000000 00000000 ................
#name: MIPS rel64 n64
#source: rel64.s
-#as: -KPIC -EB -64
+#as: -march=from-abi -KPIC -EB -64
#readelf: -x .text -r
#ld: -shared -melf64btsmip
+Type3: R_MIPS_NONE
Hex dump of section '.text':
+ 0x00000430 00000000 00000000 00000000 00000000 ................
+ 0x00000440 00000000 00000440 00000000 00000000 ................
0x00000450 00000000 00000000 00000000 00000000 ................
- 0x00000460 00000000 00000460 00000000 00000000 ................
- 0x00000470 00000000 00000000 00000000 00000000 ................
#name: MIPS relax-jalr-shared n32
#source: relax-jalr.s
-#as: -KPIC -n32 -EB
+#as: -march=from-abi -KPIC -n32 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -shared -melf32btsmipn32
#name: MIPS relax-jalr n32
#source: relax-jalr.s
-#as: -KPIC -n32 -EB
+#as: -march=from-abi -KPIC -n32 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -melf32btsmipn32
#name: MIPS relax-jalr-shared n64
#source: relax-jalr.s
-#as: -KPIC -64 -EB
+#as: -march=from-abi -KPIC -64 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -shared -melf64btsmip
#name: MIPS relax-jalr n64
#source: relax-jalr.s
-#as: -KPIC -64 -EB
+#as: -march=from-abi -KPIC -64 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -melf64btsmip
-#source: reloc-1a.s -mabi=n32
-#source: reloc-1b.s -mabi=n32
+#source: reloc-1a.s -march=from-abi -mabi=n32 -EB
+#source: reloc-1b.s -march=from-abi -mabi=n32 -EB
#ld: -r
#readelf: --relocs
-#source: reloc-1a.s -mabi=64 -EB
-#source: reloc-1b.s -mabi=64 -EB
-#ld: -melf64btsmip -r
+#source: reloc-1a.s -march=from-abi -mabi=64 -EB
+#source: reloc-1b.s -march=from-abi -mabi=64 -EB
+#ld: -r
#readelf: --relocs
Relocation section '\.rela\.text' .*
. = 0x208000;
.text : { *(.text) }
. = 0x400000;
- _gp = 0x401234;
+ HIDDEN (_gp = 0x401234);
.sdata : { *(.sdata) }
/DISCARD/ : { *(*) }
}
.data : { *(.data) }
. = ALIGN (0x400);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
}
.text : { *(.text) }
. = ALIGN (0x10000);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
/DISCARD/ : { *(.reginfo) }
#name: MIPS textrel-1
#source: textrel-1.s
-#as: -EB -n32
+#as: -march=from-abi -EB -n32
#ld: -shared -melf32btsmipn32
#readelf: -d
.text : { *(.text) }
. = ALIGN (0x10000);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = ALIGN (0x400);
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
00000000 R_MIPS_NONE \*ABS\*
-0013f830 R_MIPS_TLS_DTPMOD32 \*ABS\*
-0014948c R_MIPS_TLS_DTPMOD32 \*ABS\*
-0013f83c R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0013f840 R_MIPS_TLS_DTPREL32 tlsvar_gd
-00149498 R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0014949c R_MIPS_TLS_DTPREL32 tlsvar_gd
-0013f838 R_MIPS_TLS_TPREL32 tlsvar_ie
-00149494 R_MIPS_TLS_TPREL32 tlsvar_ie
-00143e38 R_MIPS_REL32 sym_1_9526
+0013f820 R_MIPS_TLS_DTPMOD32 \*ABS\*
+0014947c R_MIPS_TLS_DTPMOD32 \*ABS\*
+0013f82c R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0013f830 R_MIPS_TLS_DTPREL32 tlsvar_gd
+00149488 R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0014948c R_MIPS_TLS_DTPREL32 tlsvar_gd
+0013f828 R_MIPS_TLS_TPREL32 tlsvar_ie
+00149484 R_MIPS_TLS_TPREL32 tlsvar_ie
+00143e28 R_MIPS_REL32 sym_1_9526
#...
-00139ab8 R_MIPS_REL32 sym_2_8654
+00139aa8 R_MIPS_REL32 sym_2_8654
Contents of section .got:
- 122360 00000000 80000000 000d7f98 000d65f4 .*
- 122370 000d1fa4 000d6010 000d5a48 000d19c0 .*
+ 122350 00000000 80000000 000d7f88 000d65e4 .*
+ 122360 000d1f94 000d6000 000d5a38 000d19b0 .*
#...
- 135be0 000cf204 000e0e48 00000000 80000000 .*
- 135bf0 00000000 00000000 00000000 00000000 .*
+ 135bd0 000cf1f4 000e0e38 00000000 80000000 .*
+ 135be0 00000000 00000000 00000000 00000000 .*
#...
+ 13f810 00000000 00000000 00000000 00000000 .*
13f820 00000000 00000000 00000000 00000000 .*
- 13f830 00000000 00000000 00000000 00000000 .*
- 13f840 00000000 00000000 80000000 00000000 .*
+ 13f830 00000000 00000000 80000000 00000000 .*
#...
+ 149440 00000000 00000000 00000000 00000000 .*
149450 00000000 00000000 00000000 00000000 .*
149460 00000000 00000000 00000000 00000000 .*
149470 00000000 00000000 00000000 00000000 .*
149480 00000000 00000000 00000000 00000000 .*
- 149490 00000000 00000000 00000000 00000000 .*
#pass
0x00000004 \(HASH\) 0x1c4
0x00000005 \(STRTAB\).*
0x00000006 \(SYMTAB\).*
- 0x0000000a \(STRSZ\) 220091 \(bytes\)
+ 0x0000000a \(STRSZ\) 220087 \(bytes\)
0x0000000b \(SYMENT\) 16 \(bytes\)
- 0x00000003 \(PLTGOT\) 0x122360
- 0x00000011 \(REL\) 0xa7978
+ 0x00000003 \(PLTGOT\) 0x122350
+ 0x00000011 \(REL\) 0xa7960
0x00000012 \(RELSZ\) 160072 \(bytes\)
0x00000013 \(RELENT\) 8 \(bytes\)
0x70000001 \(MIPS_RLD_VERSION\) 1
0x70000005 \(MIPS_FLAGS\) NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) 0x0
0x7000000a \(MIPS_LOCAL_GOTNO\) 2
- 0x70000011 \(MIPS_SYMTABNO\) 20013
+ 0x70000011 \(MIPS_SYMTABNO\) 20012
0x70000012 \(MIPS_UNREFEXTNO\) 10
- 0x70000013 \(MIPS_GOTSYM\) 0xd
+ 0x70000013 \(MIPS_GOTSYM\) 0xc
0x0000001e \(FLAGS\) STATIC_TLS
0x00000000 \(NULL\) 0x0
[0-9a-f ]+R_MIPS_TLS_DTPREL 00000000 tlsvar_gd
[0-9a-f ]+R_MIPS_TLS_TPREL3 00000004 tlsvar_ie
[0-9a-f ]+R_MIPS_TLS_TPREL3 00000004 tlsvar_ie
-[0-9a-f ]+R_MIPS_REL32 000d7f98 sym_1_9526
-[0-9a-f ]+R_MIPS_REL32 000d65f4 sym_1_7885
+[0-9a-f ]+R_MIPS_REL32 000d7f88 sym_1_9526
+[0-9a-f ]+R_MIPS_REL32 000d65e4 sym_1_7885
#...
-[0-9a-f ]+R_MIPS_REL32 000cf204 sym_1_0465
-[0-9a-f ]+R_MIPS_REL32 000e0e48 sym_2_8654
+[0-9a-f ]+R_MIPS_REL32 000cf1f4 sym_1_0465
+[0-9a-f ]+R_MIPS_REL32 000e0e38 sym_2_8654
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7bf0 addiu gp,gp,31728
+ .*: 279c7c10 addiu gp,gp,31760
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
.* <other>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7b30 addiu gp,gp,31536
+ .*: 279c7b50 addiu gp,gp,31568
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 004004cc 00000001 .........@......
+ 10000020 00000000 80000000 004004ac 00000001 .........@......
10000030 00000000 00000000 00000000 00000000 ................
10000040 00000000 00000000 00000000 ............
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7bf0 addiu gp,gp,31728
+ .*: 279c7c10 addiu gp,gp,31760
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
.* <other>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7b30 addiu gp,gp,31536
+ .*: 279c7b50 addiu gp,gp,31568
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 004004cc 00000000 .*
+ 10000020 00000000 80000000 004004ac 00000000 .*
10000030 00000000 00000000 00000000 00000000 .*
10000040 00000001 00000000 00000000 00000000 .*
10000050 00000000 00000000 .*
.* <other>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7bf0 addiu gp,gp,31728
+ .*: 279c7c10 addiu gp,gp,31760
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7b40 addiu gp,gp,31552
+ .*: 279c7b60 addiu gp,gp,31584
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 0040057c 00000000 .*
+ 10000020 00000000 80000000 0040055c 00000000 .*
10000030 00000000 00000000 00000000 00000000 .*
10000040 00000001 00000000 00000000 00000000 .*
10000050 00000000 00000000 .*
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7ba0 addiu gp,gp,31648
+ .*: 279c7bc0 addiu gp,gp,31680
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 0040051c 00000001 ................
+ 10000020 00000000 80000000 004004fc 00000001 ................
10000030 00000000 00000000 00000000 00000000 ................
10000040 00000000 00000000 00000000 ............
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
00000000 R_MIPS_NONE \*ABS\*
-00040520 R_MIPS_TLS_DTPMOD32 \*ABS\*
-00040528 R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0004052c R_MIPS_TLS_DTPREL32 tlsvar_gd
-0004051c R_MIPS_TLS_TPREL32 tlsvar_ie
+00040500 R_MIPS_TLS_DTPMOD32 \*ABS\*
+00040508 R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0004050c R_MIPS_TLS_DTPREL32 tlsvar_gd
+000404fc R_MIPS_TLS_TPREL32 tlsvar_ie
Contents of section .got:
- 40510 00000000 80000000 000004e0 00000000 ................
- 40520 00000000 00000000 00000000 00000000 ................
+ 404f0 00000000 80000000 000004c0 00000000 ................
+ 40500 00000000 00000000 00000000 00000000 ................
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
00000000 R_MIPS_NONE \*ABS\*
-00040480 R_MIPS_TLS_DTPMOD32 \*ABS\*
-00040488 R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0004048c R_MIPS_TLS_DTPREL32 tlsvar_gd
-0004047c R_MIPS_TLS_TPREL32 tlsvar_ie
+00040460 R_MIPS_TLS_DTPMOD32 \*ABS\*
+00040468 R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0004046c R_MIPS_TLS_DTPREL32 tlsvar_gd
+0004045c R_MIPS_TLS_TPREL32 tlsvar_ie
Contents of section .got:
- 40470 00000000 80000000 00000440 00000000 ................
- 40480 00000000 00000000 00000000 00000000 ................
+ 40450 00000000 80000000 00000420 00000000 ................
+ 40460 00000000 00000000 00000000 00000000 ................
set state [remote_exec host $CC --version]
set tmp "[lindex $state 1]\n"
# Look for (eg) 4.6.1 in the version output.
- regexp " .* (\[1-9\])\\.(\[0-9\])\\.\[0-9\]* .*" "$tmp" fred maj min
+ set ver_re "\[^\\.0-9\]+(\[1-9\]\[0-9\]*)\\.(\[0-9\]+)(?:\\.\[0-9\]+)?"
+ regexp $ver_re $tmp fred maj min
verbose "gcc version: $tmp"
+ if { ![info exists maj] || ![info exists min] } then {
+ perror "can't decipher gcc version number, fix the framework!"
+ return 0
+ }
verbose "major gcc version is $maj, want at least $major"
if { $maj == $major } then {
verbose "minor gcc version is $min, want at least $minor"
- return [expr $min >= $minor ]
+ return [expr $min >= $minor]
} else {
- return [expr $maj > $major ]
+ return [expr $maj > $major]
}
}
return $flags
}
-# run_dump_test FILE
+# run_dump_test FILE (optional:) EXTRA_OPTIONS
# Copied from gas testsuite, tweaked and further extended.
#
# Assemble a .s file, then run some utility on it and check the output.
# list ends with the first line that doesn't match the above syntax
# (hmm, not great for error detection).
#
+# The optional EXTRA_OPTIONS argument to `run_dump_test' is a list of
+# two-element lists. The first element of each is an option name, and
+# the second additional arguments to be added on to the end of the
+# option list as given in FILE.d. (If omitted, no additional options
+# are added.)
+#
# The interesting options are:
#
# name: TEST-NAME
# More than one "source" directive can be given, which is useful
# when testing linking.
#
+# dump: DUMP
+# Match against DUMP.d. If omitted, this defaults to FILE.d. This
+# is useful if several .d files differ by options only. Options are
+# always read from FILE.d.
+#
# xfail: TARGET
# The test is expected to fail on TARGET. This may occur more than
# once.
# regexps in FILE.d. `regexp_diff' is defined in binutils-common.exp;
# see further comments there.
#
-proc run_dump_test { name } {
+proc run_dump_test { name {extra_options {}} } {
global subdir srcdir
global OBJDUMP NM AS OBJCOPY READELF LD
global OBJDUMPFLAGS NMFLAGS ASFLAGS OBJCOPYFLAGS READELFFLAGS LDFLAGS
set opts(name) {}
set opts(PROG) {}
set opts(source) {}
+ set opts(dump) {}
set opts(error) {}
set opts(warning) {}
set opts(objcopy_linked_file) {}
}
}
}
+
+ foreach i $extra_options {
+ set opt_name [lindex $i 0]
+ set opt_val [lindex $i 1]
+ if ![info exists opts($opt_name)] {
+ perror "unknown option $opt_name given in extra_opts"
+ unresolved $subdir/$name
+ return
+ }
+ # Add extra option to end of existing option, adding space
+ # if necessary.
+ if { ![regexp "warning|error" $opt_name]
+ && [string length $opts($opt_name)] } {
+ append opts($opt_name) " "
+ }
+ append opts($opt_name) $opt_val
+ }
+
foreach opt { as ld } {
regsub {\[big_or_little_endian\]} $opts($opt) \
[big_or_little_endian] opts($opt)
}
}
+ if { $opts(dump) == "" } {
+ set dfile ${file}.d
+ } else {
+ set dfile $srcdir/$subdir/$opts(dump)
+ }
+
# Time to setup xfailures.
foreach targ $opts(xfail) {
setup_xfail $targ
}
if { $verbose > 2 } then { verbose "output is [file_contents $dumpfile]" 3 }
- if { [regexp_diff $dumpfile "${file}.d"] } then {
+ if { [regexp_diff $dumpfile "${dfile}"] } then {
fail $testname
if { $verbose == 2 } then { verbose "output is [file_contents $dumpfile]" 2 }
return
+2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
+ macros, use local variables for info struct member accesses,
+ update the type of the variable used to hold the instruction
+ word.
+ (print_insn_mips, print_mips16_insn_arg): Likewise.
+ (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
+ local variables for info struct member accesses.
+ (print_insn_micromips): Add GET_OP_S local macro.
+ (_print_insn_mips): Update the type of the variable used to hold
+ the instruction word.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (micromips_opcodes): Update comment.
+ * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
+ instructions for IOCT as appropriate.
+ * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
+ the result of a check for the -Wno-missing-field-initializers
+ GCC option.
+ * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
+ (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
+ compilation.
+ (mips16-opc.lo): Likewise.
+ (micromips-opc.lo): Likewise.
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+ * Makefile.in: Regenerate.
+
2012-08-01 Alan Modra <amodra@gmail.com>
* h8300-dis.c: Fix printf arg warnings.
WARN_CFLAGS = @WARN_CFLAGS@
NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
AM_CFLAGS = $(WARN_CFLAGS)
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(INCLUDES) $(AM_CPPFLAGS) \
$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
+micromips-opc.lo: micromips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
$(top_srcdir)/../config/override.m4 \
$(top_srcdir)/../config/po.m4 \
$(top_srcdir)/../config/progtest.m4 \
+ $(top_srcdir)/../config/warnings.m4 \
$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
$(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.in
NM = @NM@
NMEDIT = @NMEDIT@
NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
OBJDUMP = @OBJDUMP@
OBJEXT = @OBJEXT@
OTOOL = @OTOOL@
$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
+micromips-opc.lo: micromips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
m4_include([../config/override.m4])
m4_include([../config/po.m4])
m4_include([../config/progtest.m4])
+m4_include([../config/warnings.m4])
m4_include([../libtool.m4])
m4_include([../ltoptions.m4])
m4_include([../ltsugar.m4])
MAINT
MAINTAINER_MODE_FALSE
MAINTAINER_MODE_TRUE
+NO_WMISSING_FIELD_INITIALIZERS
NO_WERROR
WARN_CFLAGS
OTOOL64
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11137 "configure"
+#line 11138 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11243 "configure"
+#line 11244 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
+NO_WMISSING_FIELD_INITIALIZERS=
+save_CFLAGS="$CFLAGS"
+for real_option in -Wno-missing-field-initializers; do
+ # Do the check with the no- prefix removed since gcc silently
+ # accepts any -Wno-* option on purpose
+ case $real_option in
+ -Wno-*) option=-W`expr x$real_option : 'x-Wno-\(.*\)'` ;;
+ *) option=$real_option ;;
+ esac
+ as_acx_Woption=`$as_echo "acx_cv_prog_cc_warning_$option" | $as_tr_sh`
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC supports $option" >&5
+$as_echo_n "checking whether $CC supports $option... " >&6; }
+if { as_var=$as_acx_Woption; eval "test \"\${$as_var+set}\" = set"; }; then :
+ $as_echo_n "(cached) " >&6
+else
+ CFLAGS="$option"
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ eval "$as_acx_Woption=yes"
+else
+ eval "$as_acx_Woption=no"
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+fi
+eval ac_res=\$$as_acx_Woption
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+ if test `eval 'as_val=${'$as_acx_Woption'};$as_echo "$as_val"'` = yes; then :
+ NO_WMISSING_FIELD_INITIALIZERS="$NO_WMISSING_FIELD_INITIALIZERS${NO_WMISSING_FIELD_INITIALIZERS:+ }$real_option"
+fi
+ done
+CFLAGS="$save_CFLAGS"
+
ac_config_headers="$ac_config_headers config.h:config.in"
esac])dnl
AM_BINUTILS_WARNINGS
+ACX_PROG_CC_WARNING_OPTS([-Wno-missing-field-initializers],
+ [NO_WMISSING_FIELD_INITIALIZERS])
AC_CONFIG_HEADERS(config.h:config.in)
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
-/* name, args, match, mask, pinfo, pinfo2, membership */
+/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
static void
print_insn_args (const char *d,
- register unsigned long int l,
+ int l,
bfd_vma pc,
struct disassemble_info *info,
const struct mips_opcode *opp)
{
- int op, delta;
+ const fprintf_ftype infprintf = info->fprintf_func;
unsigned int lsb, msb, msbd;
+ void *is = info->stream;
+ int op;
lsb = 0;
+#define GET_OP(insn, field) \
+ (((insn) >> OP_SH_##field) & OP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((OP_MASK_##field >> 1) + 1)) \
+ - ((OP_MASK_##field >> 1) + 1))
for (; *d != '\0'; d++)
{
switch (*d)
case ')':
case '[':
case ']':
- (*info->fprintf_func) (info->stream, "%c", *d);
+ infprintf (is, "%c", *d);
break;
case '+':
{
case '\0':
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, incomplete extension sequence (+)"));
+ infprintf (is,
+ _("# internal error, "
+ "incomplete extension sequence (+)"));
return;
case 'A':
- lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
+ lsb = GET_OP (l, SHAMT);
+ infprintf (is, "0x%x", lsb);
break;
case 'B':
- msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
+ msb = GET_OP (l, INSMSB);
+ infprintf (is, "0x%x", msb - lsb + 1);
break;
case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI1) & OP_MASK_UDI1);
+ infprintf (is, "0x%x", GET_OP (l, UDI1));
break;
case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI2) & OP_MASK_UDI2);
+ infprintf (is, "0x%x", GET_OP (l, UDI2));
break;
case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI3) & OP_MASK_UDI3);
+ infprintf (is, "0x%x", GET_OP (l, UDI3));
break;
case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI4) & OP_MASK_UDI4);
+ infprintf (is, "0x%x", GET_OP (l, UDI4));
break;
case 'C':
case 'H':
- msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
+ msbd = GET_OP (l, EXTMSBD);
+ infprintf (is, "0x%x", msbd + 1);
break;
case 'D':
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
- cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+ cp0reg = GET_OP (l, RD);
+ sel = GET_OP (l, SEL);
/* CP0 register including 'sel' code for mtcN (et al.), to be
printed textually if known. If not known, print both
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
+ infprintf (is, "%s", n->name);
else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ infprintf (is, "$%d,%d", cp0reg, sel);
break;
}
case 'E':
- lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
+ lsb = GET_OP (l, SHAMT) + 32;
+ infprintf (is, "0x%x", lsb);
break;
case 'F':
- msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
+ msb = GET_OP (l, INSMSB) + 32;
+ infprintf (is, "0x%x", msb - lsb + 1);
break;
case 'G':
- msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
+ msbd = GET_OP (l, EXTMSBD) + 32;
+ infprintf (is, "0x%x", msbd + 1);
break;
case 't': /* Coprocessor 0 reg name */
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RT) &
- OP_MASK_RT]);
+ infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]);
break;
case 'T': /* Coprocessor 0 reg name */
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
- cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+ cp0reg = GET_OP (l, RT);
+ sel = GET_OP (l, SEL);
/* CP0 register including 'sel' code for mftc0, to be
printed textually if known. If not known, print both
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
+ infprintf (is, "%s", n->name);
else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ infprintf (is, "$%d,%d", cp0reg, sel);
break;
}
case 'x': /* bbit bit index */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
+ infprintf (is, "0x%x", GET_OP (l, BBITIND));
break;
case 'p': /* cins, cins32, exts and exts32 position */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
+ infprintf (is, "0x%x", GET_OP (l, CINSPOS));
break;
case 's': /* cins and exts length-minus-one */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
+ infprintf (is, "0x%x", GET_OP (l, CINSLM1));
break;
case 'S': /* cins32 and exts32 length-minus-one field */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
+ infprintf (is, "0x%x", GET_OP (l, CINSLM1));
break;
case 'Q': /* seqi/snei immediate field */
- op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
- /* Sign-extend it. */
- op = (op ^ 512) - 512;
- (*info->fprintf_func) (info->stream, "%d", op);
+ infprintf (is, "%d", GET_OP_S (l, SEQI));
break;
case 'a': /* 8-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_A;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_A));
break;
case 'b': /* 8-bit signed offset in bit 3 */
- delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_B;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_B));
break;
case 'c': /* 9-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C;
- if (delta & 0x100)
- delta |= ~OP_MASK_OFFSET_C;
/* Left shift 4 bits to print the real offset. */
- (*info->fprintf_func) (info->stream, "%d", delta << 4);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_C) << 4);
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RZ)]);
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined extension sequence (+%c)"),
- *d);
+ infprintf (is,
+ _("# internal error, "
+ "undefined extension sequence (+%c)"),
+ *d);
return;
}
break;
case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BP) & OP_MASK_BP);
+ infprintf (is, "0x%x", GET_OP (l, BP));
break;
case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA3) & OP_MASK_SA3);
+ infprintf (is, "0x%x", GET_OP (l, SA3));
break;
case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA4) & OP_MASK_SA4);
+ infprintf (is, "0x%x", GET_OP (l, SA4));
break;
case '5':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMM8) & OP_MASK_IMM8);
+ infprintf (is, "0x%x", GET_OP (l, IMM8));
break;
case '6':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RS) & OP_MASK_RS);
+ infprintf (is, "0x%x", GET_OP (l, RS));
break;
case '7':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
+ infprintf (is, "$ac%d", GET_OP (l, DSPACC));
break;
case '8':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
+ infprintf (is, "0x%x", GET_OP (l, WRDSP));
break;
case '9':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
+ infprintf (is, "$ac%d", GET_OP (l, DSPACC_S));
break;
case '0': /* dsp 6-bit signed immediate in bit 20 */
- delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
- if (delta & 0x20) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, DSPSFT));
break;
case ':': /* dsp 7-bit signed immediate in bit 19 */
- delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
- if (delta & 0x40) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT_7;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, DSPSFT_7));
break;
case '~':
- delta = (l >> OP_SH_OFFSET12) & OP_MASK_OFFSET12;
- if (delta & 0x800)
- delta |= ~0x7ff;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET12));
break;
case '\\':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_3BITPOS) & OP_MASK_3BITPOS);
+ infprintf (is, "0x%x", GET_OP (l, 3BITPOS));
break;
case '\'':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
+ infprintf (is, "0x%x", GET_OP (l, RDDSP));
break;
case '@': /* dsp 10-bit signed immediate in bit 16 */
- delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
- if (delta & 0x200) /* test sign bit */
- delta |= ~OP_MASK_IMM10;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, IMM10));
break;
case '!':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_U) & OP_MASK_MT_U);
+ infprintf (is, "%d", GET_OP (l, MT_U));
break;
case '$':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_H) & OP_MASK_MT_H);
+ infprintf (is, "%d", GET_OP (l, MT_H));
break;
case '*':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
+ infprintf (is, "$ac%d", GET_OP (l, MTACC_T));
break;
case '&':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
+ infprintf (is, "$ac%d", GET_OP (l, MTACC_D));
break;
case 'g':
/* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
+ infprintf (is, "$%d", GET_OP (l, RD));
break;
case 's':
case 'b':
case 'r':
case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RS)]);
break;
case 't':
case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
break;
case 'i':
case 'u':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
+ infprintf (is, "0x%x", GET_OP (l, IMMEDIATE));
break;
case 'j': /* Same as i, but sign-extended. */
case 'o':
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- (*info->fprintf_func) (info->stream, "%d",
- delta);
+ infprintf (is, "%d", GET_OP_S (l, DELTA));
break;
case 'h':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_PREFX)
- & OP_MASK_PREFX));
+ infprintf (is, "0x%x", GET_OP (l, PREFX));
break;
case 'k':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_CACHE)
- & OP_MASK_CACHE));
+ infprintf (is, "0x%x", GET_OP (l, CACHE));
break;
case 'a':
info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
- | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
+ | (GET_OP (l, TARGET) << 2));
/* For gdb disassembler, force odd address on jalx. */
if (info->flavour == bfd_target_unknown_flavour
&& strcmp (opp->name, "jalx") == 0)
case 'p':
/* Sign extend the displacement. */
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- info->target = (delta << 2) + pc + INSNLEN;
+ info->target = (GET_OP_S (l, DELTA) << 2) + pc + INSNLEN;
(*info->print_address_func) (info->target, info);
break;
case 'd':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RD)]);
break;
case 'U':
{
/* First check for both rd and rt being equal. */
- unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
- if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
+ unsigned int reg = GET_OP (l, RD);
+ if (reg == GET_OP (l, RT))
+ infprintf (is, "%s", mips_gpr_names[reg]);
else
{
/* If one is zero use the other. */
if (reg == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
- else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
+ else if (GET_OP (l, RT) == 0)
+ infprintf (is, "%s", mips_gpr_names[reg]);
else /* Bogus, result depends on processor. */
- (*info->fprintf_func) (info->stream, "%s or %s",
- mips_gpr_names[reg],
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ infprintf (is, "%s or %s",
+ mips_gpr_names[reg],
+ mips_gpr_names[GET_OP (l, RT)]);
}
}
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
+ infprintf (is, "%s", mips_gpr_names[0]);
break;
case '<':
case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
+ infprintf (is, "0x%x", GET_OP (l, SHAMT));
break;
case 'c':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE) & OP_MASK_CODE);
+ infprintf (is, "0x%x", GET_OP (l, CODE));
break;
case 'q':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE2) & OP_MASK_CODE2);
+ infprintf (is, "0x%x", GET_OP (l, CODE2));
break;
case 'C':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_COPZ) & OP_MASK_COPZ);
+ infprintf (is, "0x%x", GET_OP (l, COPZ));
break;
case 'B':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+ infprintf (is, "0x%x", GET_OP (l, CODE20));
break;
case 'J':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE19) & OP_MASK_CODE19);
+ infprintf (is, "0x%x", GET_OP (l, CODE19));
break;
case 'S':
case 'V':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FS)]);
break;
case 'T':
case 'W':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FT)]);
break;
case 'D':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FD)]);
break;
case 'R':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FR)]);
break;
case 'E':
'T' format. Therefore, until we gain understanding of
cp2 register names, we can simply print the register
numbers. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RT) & OP_MASK_RT);
+ infprintf (is, "$%d", GET_OP (l, RT));
break;
case 'G':
that FPU (cp1) instructions disassemble this field using
'S' format. Therefore, we only need to worry about cp0,
cp2, and cp3. */
- op = (l >> OP_SH_OP) & OP_MASK_OP;
+ op = GET_OP (l, OP);
if (op == OP_OP_COP0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_cp0_names[GET_OP (l, RD)]);
else
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
+ infprintf (is, "$%d", GET_OP (l, RD));
break;
case 'K':
- (*info->fprintf_func) (info->stream, "%s",
- mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_hwr_names[GET_OP (l, RD)]);
break;
case 'N':
- (*info->fprintf_func) (info->stream,
- ((opp->pinfo & (FP_D | FP_S)) != 0
- ? "$fcc%ld" : "$cc%ld"),
- (l >> OP_SH_BCC) & OP_MASK_BCC);
+ infprintf (is,
+ (opp->pinfo & (FP_D | FP_S)) != 0 ? "$fcc%d" : "$cc%d",
+ GET_OP (l, BCC));
break;
case 'M':
- (*info->fprintf_func) (info->stream, "$fcc%ld",
- (l >> OP_SH_CCC) & OP_MASK_CCC);
+ infprintf (is, "$fcc%d", GET_OP (l, CCC));
break;
case 'P':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
+ infprintf (is, "%d", GET_OP (l, PERFREG));
break;
case 'e':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
+ infprintf (is, "%d", GET_OP (l, VECBYTE));
break;
case '%':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
+ infprintf (is, "%d", GET_OP (l, VECALIGN));
break;
case 'H':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_SEL) & OP_MASK_SEL);
+ infprintf (is, "%d", GET_OP (l, SEL));
break;
case 'O':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_ALN) & OP_MASK_ALN);
+ infprintf (is, "%d", GET_OP (l, ALN));
break;
case 'Q':
{
- unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
+ unsigned int vsel = GET_OP (l, VSEL);
if ((vsel & 0x10) == 0)
{
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
if ((vsel & 1) == 0)
break;
- (*info->fprintf_func) (info->stream, "$v%ld[%d]",
- (l >> OP_SH_FT) & OP_MASK_FT,
- vsel >> 1);
+ infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1);
}
else if ((vsel & 0x08) == 0)
{
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "$v%d", GET_OP (l, FT));
}
else
{
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "0x%x", GET_OP (l, FT));
}
}
break;
case 'X':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FD) & OP_MASK_FD);
+ infprintf (is, "$v%d", GET_OP (l, FD));
break;
case 'Y':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FS) & OP_MASK_FS);
+ infprintf (is, "$v%d", GET_OP (l, FS));
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "$v%d", GET_OP (l, FT));
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined modifier (%c)"),
- *d);
+ infprintf (is, _("# internal error, undefined modifier (%c)"), *d);
return;
}
}
static int
print_insn_mips (bfd_vma memaddr,
- unsigned long int word,
+ int word,
struct disassemble_info *info)
{
+ static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ const fprintf_ftype infprintf = info->fprintf_func;
const struct mips_opcode *op;
static bfd_boolean init = 0;
- static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ void *is = info->stream;
/* Build a hash table to shorten the search time. */
if (! init)
if (op->pinfo == INSN_MACRO
|| (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
continue;
- if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
+ if (i == GET_OP (op->match, OP))
{
mips_hash[i] = op;
break;
info->target = 0;
info->target2 = 0;
- op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
+ op = mips_hash[GET_OP (word, OP)];
if (op != NULL)
{
for (; op < &mips_opcodes[NUMOPCODES]; op++)
const char *d;
/* We always allow to disassemble the jalx instruction. */
- if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
+ if (!opcode_is_member (op, mips_isa, mips_processor)
&& strcmp (op->name, "jalx"))
continue;
| INSN_LOAD_MEMORY_DELAY)) != 0)
info->insn_type = dis_dref;
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
d = op->args;
if (d != NULL && *d != '\0')
{
- (*info->fprintf_func) (info->stream, "\t");
+ infprintf (is, "\t");
print_insn_args (d, word, memaddr, info, op);
}
}
}
}
+#undef GET_OP_S
+#undef GET_OP
/* Handle undefined instructions. */
info->insn_type = dis_noninsn;
- (*info->fprintf_func) (info->stream, "0x%lx", word);
+ infprintf (is, "0x%x", word);
return INSNLEN;
}
\f
bfd_vma memaddr,
struct disassemble_info *info)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
+ void *is = info->stream;
+
+#define GET_OP(insn, field) \
+ (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \
+ - ((MIPS16OP_MASK_##field >> 1) + 1))
switch (type)
{
case ',':
case '(':
case ')':
- (*info->fprintf_func) (info->stream, "%c", type);
+ infprintf (is, "%c", type);
break;
case 'y':
case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RY)
- & MIPS16OP_MASK_RY)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY)));
break;
case 'x':
case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RX)
- & MIPS16OP_MASK_RX)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX)));
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RZ)
- & MIPS16OP_MASK_RZ)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ)));
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
- & MIPS16OP_MASK_MOVE32Z)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z)));
break;
case '0':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
+ infprintf (is, "%s", mips_gpr_names[0]);
break;
case 'S':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
+ infprintf (is, "%s", mips_gpr_names[29]);
break;
case 'P':
- (*info->fprintf_func) (info->stream, "$pc");
+ infprintf (is, "$pc");
break;
case 'R':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
+ infprintf (is, "%s", mips_gpr_names[31]);
break;
case 'X':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
- & MIPS16OP_MASK_REGR32)]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]);
break;
case 'Y':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
+ infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
break;
case '<':
{
case '<':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
+ immed = GET_OP (l, RZ);
extbits = 5;
extu = 1;
break;
case '>':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
+ immed = GET_OP (l, RX);
extbits = 5;
extu = 1;
break;
case '[':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
+ immed = GET_OP (l, RZ);
extbits = 6;
extu = 1;
break;
case ']':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
+ immed = GET_OP (l, RX);
extbits = 6;
extu = 1;
break;
case '4':
nbits = 4;
- immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
+ immed = GET_OP (l, IMM4);
signedp = 1;
extbits = 15;
break;
case '5':
nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 1;
break;
case 'H':
nbits = 5;
shift = 1;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 2;
break;
case 'W':
nbits = 5;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
&& (op->pinfo & MIPS16_INSN_READ_SP) == 0)
{
case 'D':
nbits = 5;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 8;
break;
case 'j':
nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
signedp = 1;
break;
case '6':
nbits = 6;
- immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
+ immed = GET_OP (l, IMM6);
break;
case '8':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
break;
case 'V':
nbits = 8;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
/* FIXME: This might be lw, or it might be addiu to $sp or
$pc. We assume it's load. */
info->insn_type = dis_dref;
case 'C':
nbits = 8;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
info->insn_type = dis_dref;
info->data_size = 8;
break;
case 'U':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
extu = 1;
break;
case 'k':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
break;
case 'K':
nbits = 8;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
break;
case 'p':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
pcrel = 1;
branch = 1;
break;
case 'q':
nbits = 11;
- immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
+ immed = GET_OP (l, IMM11);
signedp = 1;
pcrel = 1;
branch = 1;
case 'A':
nbits = 8;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
pcrel = 1;
/* FIXME: This can be lw or la. We assume it is lw. */
info->insn_type = dis_dref;
case 'B':
nbits = 5;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
pcrel = 1;
info->insn_type = dis_dref;
info->data_size = 8;
case 'E':
nbits = 5;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
pcrel = 1;
break;
default:
}
if (! pcrel)
- (*info->fprintf_func) (info->stream, "%d", immed);
+ infprintf (is, "%d", immed);
else
{
bfd_vma baseaddr;
need_comma = 0;
- l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
+ l = GET_OP (l, IMM6);
amask = (l >> 3) & 7;
if (amask > 0 && amask < 5)
{
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
+ infprintf (is, "%s", mips_gpr_names[4]);
if (amask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[amask + 3]);
+ infprintf (is, "-%s", mips_gpr_names[amask + 3]);
need_comma = 1;
}
smask = (l >> 1) & 3;
if (smask == 3)
{
- (*info->fprintf_func) (info->stream, "%s??",
- need_comma ? "," : "");
+ infprintf (is, "%s??", need_comma ? "," : "");
need_comma = 1;
}
else if (smask > 0)
{
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[16]);
+ infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]);
if (smask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[smask + 15]);
+ infprintf (is, "-%s", mips_gpr_names[smask + 15]);
need_comma = 1;
}
if (l & 1)
{
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[31]);
+ infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]);
need_comma = 1;
}
if (amask == 5 || amask == 6)
{
- (*info->fprintf_func) (info->stream, "%s$f0",
- need_comma ? "," : "");
+ infprintf (is, "%s$f0", need_comma ? "," : "");
if (amask == 6)
- (*info->fprintf_func) (info->stream, "-$f1");
+ infprintf (is, "-$f1");
}
}
break;
}
if (args > 0) {
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
+ infprintf (is, "%s", mips_gpr_names[4]);
if (args > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[4 + args - 1]);
+ infprintf (is, "-%s", mips_gpr_names[4 + args - 1]);
need_comma = 1;
}
if (framesz == 0 && !use_extend)
framesz = 128;
- (*info->fprintf_func) (info->stream, "%s%d",
- need_comma ? "," : "",
- framesz);
+ infprintf (is, "%s%d", need_comma ? "," : "", framesz);
if (l & 0x40) /* $ra */
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
+ infprintf (is, ",%s", mips_gpr_names[31]);
nsreg = (l >> 24) & 0x7;
smask = 0;
{
if (smask & (1 << i))
{
- (*info->fprintf_func) (info->stream, ",%s",
- mips_gpr_names[i == 8 ? 30 : (16 + i)]);
+ infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
/* Skip over string of set bits. */
for (j = i; smask & (2 << j); j++)
continue;
if (j > i)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[j == 8 ? 30 : (16 + j)]);
+ infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
i = j + 1;
}
}
/* Statics $ax - $a3. */
if (statics == 1)
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
+ infprintf (is, ",%s", mips_gpr_names[7]);
else if (statics > 0)
- (*info->fprintf_func) (info->stream, ",%s-%s",
- mips_gpr_names[7 - statics + 1],
- mips_gpr_names[7]);
+ infprintf (is, ",%s-%s",
+ mips_gpr_names[7 - statics + 1],
+ mips_gpr_names[7]);
}
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func)
- (info->stream,
- _("# internal disassembler error, unrecognised modifier (%c)"),
- type);
+ infprintf (is,
+ _("# internal disassembler error, "
+ "unrecognised modifier (%c)"),
+ type);
abort ();
}
}
static int
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
int status;
bfd_byte buffer[2];
int length;
bfd_boolean use_extend;
int extend = 0;
const struct mips_opcode *op, *opend;
+ void *is = info->stream;
info->bytes_per_chunk = 2;
info->display_endian = info->endian;
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
/* Check for an extend opcode followed by an extend opcode. */
if ((insn & 0xf800) == 0xf000)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length;
}
{
if (use_extend)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length - 2;
}
}
}
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
if (op->args[0] != '\0')
- (*info->fprintf_func) (info->stream, "\t");
+ infprintf (is, "\t");
for (s = op->args; *s != '\0'; s++)
{
if (*s == ','
&& s[1] == 'w'
- && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
- == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
+ && GET_OP (insn, RX) == GET_OP (insn, RY))
{
/* Skip the register and the comma. */
++s;
}
if (*s == ','
&& s[1] == 'v'
- && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
- == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
+ && GET_OP (insn, RZ) == GET_OP (insn, RX))
{
/* Skip the register and the comma. */
++s;
return length;
}
}
+#undef GET_OP_S
+#undef GET_OP
if (use_extend)
- (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
- (*info->fprintf_func) (info->stream, "0x%x", insn);
+ infprintf (is, "0x%x", extend | 0xf000);
+ infprintf (is, "0x%x", insn);
info->insn_type = dis_noninsn;
return length;
#define GET_OP(insn, field) \
(((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((MICROMIPSOP_MASK_##field >> 1) + 1)) \
+ - ((MICROMIPSOP_MASK_##field >> 1) + 1))
opend = micromips_opcodes + bfd_micromips_num_opcodes;
for (op = micromips_opcodes; op < opend; op++)
{
break;
case '.':
- delta = GET_OP (insn, OFFSET10);
- if (delta & 0x200)
- delta |= ~0x3ff;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, OFFSET10));
break;
case '1':
break;
case '~':
- delta = GET_OP (insn, OFFSET12);
- if (delta & 0x800)
- delta |= ~0x7ff;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, OFFSET12));
break;
case 'a':
| (GET_OP (insn, TARGET) << 2));
else
info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
- | ((GET_OP (insn, TARGET)) << 1));
+ | (GET_OP (insn, TARGET) << 1));
/* For gdb disassembler, force odd address on jalx. */
if (info->flavour == bfd_target_unknown_flavour
&& strcmp (op->name, "jalx") == 0)
case 'j': /* Same as i, but sign-extended. */
case 'o':
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, DELTA));
break;
case 'k':
case 'p':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
+ delta = GET_OP_S (insn, DELTA);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'A':
/* Sign-extend the immediate. */
- immed = ((GET_OP (insn, IMMA) ^ 0x40) - 0x40) << 2;
+ immed = GET_OP_S (insn, IMMA) << 2;
infprintf (is, "%d", immed);
break;
case 'D':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMMD) ^ 0x200) - 0x200;
+ delta = GET_OP_S (insn, IMMD);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'E':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMME) ^ 0x40) - 0x40;
+ delta = GET_OP_S (insn, IMME);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'Q':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMQ) ^ 0x400000) - 0x400000;
- immed <<= 2;
+ immed = GET_OP_S (insn, IMMQ) << 2;
infprintf (is, "%d", immed);
break;
case 'X':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMX) ^ 0x8) - 0x8;
+ immed = GET_OP_S (insn, IMMX);
infprintf (is, "%d", immed);
break;
case 'Y':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMY) ^ 0x100) - 0x100;
- if (immed >= -2 && immed <= 1)
- immed ^= 0x100;
- immed = immed << 2;
+ immed = GET_OP_S (insn, IMMY) << 2;
+ if ((unsigned int) (immed + 8) < 16)
+ immed ^= 0x400;
infprintf (is, "%d", immed);
break;
return length;
}
}
+#undef GET_OP_S
#undef GET_OP
infprintf (is, "0x%x", insn);
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
if (status == 0)
{
- unsigned long insn;
+ int insn;
if (endianness == BFD_ENDIAN_BIG)
- insn = (unsigned long) bfd_getb32 (buffer);
+ insn = bfd_getb32 (buffer);
else
- insn = (unsigned long) bfd_getl32 (buffer);
+ insn = bfd_getl32 (buffer);
return print_insn_mips (memaddr, insn, info);
}
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
-/* name, args, match, mask, pinfo, pinfo2, membership */
+/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
-{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
+{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1, IOCT|IOCTP|IOCT2 },
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
/* cfc2 is at the bottom of the table. */
/* cfc3 is at the bottom of the table. */
{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
-{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */
{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
-{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
/* ctc2 is at the bottom of the table. */
/* ctc3 is at the bottom of the table. */
{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
-{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
+{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
-{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
-{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
+{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
+{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
-{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT },
-{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
-{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
+{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
+{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
+{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT },
-{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
-{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
+{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
+{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
-{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
+{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
+{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
-{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
+{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55},
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
-{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
+{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
-{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
+{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
-{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
-{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
-{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT },
-{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
-{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
+{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,+D",0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
+{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
-{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT },
-{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
-{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
+{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
+{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
-{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
-{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
-{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
-{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
+{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
-{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
+{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
-{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
-{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
-{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
-{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
-{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
+{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
-{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
-{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
+{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, IOCT|IOCTP|IOCT2 },
{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
-{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
-{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
-{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
-{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
-{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
-{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
-{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
-{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
-{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
-{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
+{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64, IOCT|IOCTP|IOCT2 },
+{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
instructions, so they are here for the latters to take precedence. */
-{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
-{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
-{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
-{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
-{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
-{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
+{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
+{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
+{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
/* Move bc0* after mftr and mttr to avoid opcode collision. */
-{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
+{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
disassembler recognizes more specific versions first. */
-{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 },
+{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 },
-{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 },
-{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 },
-{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
+{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
+{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
+{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
-{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }
+{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
};
#define MIPS_NUM_OPCODES \
projects / thirdparty / binutils-gdb.git / commitdiff
