arm64: dts: apple: t8015: Add cpufreq nodes

Add cpufreq nodes for Apple A11 SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Sven Peter <sven@svenpeter.dev>

diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi
index fbff3a6c0ba405f7c58ded1194fc4fb7180eb196..b68647bebd20782ba7a125e670b3264c184b62cd 100644 (file)
--- a/arch/arm64/boot/dts/apple/t8015.dtsi
+++ b/arch/arm64/boot/dts/apple/t8015.dtsi
@@ -58,6 +58,9 @@
                        compatible = "apple,mistral";
                        reg = <0x0 0x0>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       performance-domains = <&cpufreq_e>;
+                       operating-points-v2 = <&mistral_opp>;
+                       capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
@@ -66,6 +69,9 @@
                        compatible = "apple,mistral";
                        reg = <0x0 0x1>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       performance-domains = <&cpufreq_e>;
+                       operating-points-v2 = <&mistral_opp>;
+                       capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
@@ -74,6 +80,9 @@
                        compatible = "apple,mistral";
                        reg = <0x0 0x2>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       performance-domains = <&cpufreq_e>;
+                       operating-points-v2 = <&mistral_opp>;
+                       capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
@@ -82,6 +91,9 @@
                        compatible = "apple,mistral";
                        reg = <0x0 0x3>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       performance-domains = <&cpufreq_e>;
+                       operating-points-v2 = <&mistral_opp>;
+                       capacity-dmips-mhz = <633>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
@@ -90,6 +102,9 @@
                        compatible = "apple,monsoon";
                        reg = <0x0 0x10004>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       performance-domains = <&cpufreq_p>;
+                       operating-points-v2 = <&monsoon_opp>;
+                       capacity-dmips-mhz = <1024>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
@@ -98,11 +113,107 @@
                        compatible = "apple,monsoon";
                        reg = <0x0 0x10005>;
                        cpu-release-addr = <0 0>; /* To be filled by loader */
+                       performance-domains = <&cpufreq_p>;
+                       operating-points-v2 = <&monsoon_opp>;
+                       capacity-dmips-mhz = <1024>;
                        enable-method = "spin-table";
                        device_type = "cpu";
                };
        };
 
+       mistral_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+
+               opp01 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-level = <1>;
+                       clock-latency-ns = <1800>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <453000000>;
+                       opp-level = <2>;
+                       clock-latency-ns = <140000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <672000000>;
+                       opp-level = <3>;
+                       clock-latency-ns = <105000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <972000000>;
+                       opp-level = <4>;
+                       clock-latency-ns = <115000>;
+               };
+               opp05 {
+                       opp-hz = /bits/ 64 <1272000000>;
+                       opp-level = <5>;
+                       clock-latency-ns = <125000>;
+               };
+               opp06 {
+                       opp-hz = /bits/ 64 <1572000000>;
+                       opp-level = <6>;
+                       clock-latency-ns = <135000>;
+               };
+#if 0
+               /* Not available until CPU deep sleep is implemented */
+               opp07 {
+                       opp-hz = /bits/ 64 <1680000000>;
+                       opp-level = <7>;
+                       clock-latency-ns = <135000>;
+                       turbo-mode;
+               };
+#endif
+       };
+
+       monsoon_opp: opp-table-1 {
+               compatible = "operating-points-v2";
+
+               opp01 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-level = <1>;
+                       clock-latency-ns = <1400>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <453000000>;
+                       opp-level = <2>;
+                       clock-latency-ns = <140000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <853000000>;
+                       opp-level = <3>;
+                       clock-latency-ns = <110000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <1332000000>;
+                       opp-level = <4>;
+                       clock-latency-ns = <110000>;
+               };
+               opp05 {
+                       opp-hz = /bits/ 64 <1812000000>;
+                       opp-level = <5>;
+                       clock-latency-ns = <125000>;
+               };
+               opp06 {
+                       opp-hz = /bits/ 64 <2064000000>;
+                       opp-level = <6>;
+                       clock-latency-ns = <130000>;
+               };
+               opp07 {
+                       opp-hz = /bits/ 64 <2304000000>;
+                       opp-level = <7>;
+                       clock-latency-ns = <140000>;
+               };
+#if 0
+               /* Not available until CPU deep sleep is implemented */
+               opp08 {
+                       opp-hz = /bits/ 64 <2376000000>;
+                       opp-level = <8>;
+                       clock-latency-ns = <140000>;
+                       turbo-mode;
+               };
+#endif
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;
@@ -110,6 +221,18 @@
                nonposted-mmio;
                ranges;
 
+               cpufreq_e: performance-controller@208e20000 {
+                       compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+                       reg = <0x2 0x08e20000 0 0x1000>;
+                       #performance-domain-cells = <0>;
+               };
+
+               cpufreq_p: performance-controller@208ea0000 {
+                       compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+                       reg = <0x2 0x08ea0000 0 0x1000>;
+                       #performance-domain-cells = <0>;
+               };
+
                serial0: serial@22e600000 {
                        compatible = "apple,s5l-uart";
                        reg = <0x2 0x2e600000 0x0 0x4000>;