Fix more int to pointer warnings.

No more produced with GCC 14 on OI.

diff --git a/VEX/priv/host_riscv64_defs.c b/VEX/priv/host_riscv64_defs.c
index 6296b2e7fee339c04dbc3558531c515010da20bc..7e6b95380ad50c66b685796bbdac2e627455d76d 100644 (file)
--- a/VEX/priv/host_riscv64_defs.c
+++ b/VEX/priv/host_riscv64_defs.c
@@ -2647,7 +2647,7 @@ VexInvalRange unchainXDirect_RISCV64(VexEndness  endness_host,
    UChar* p = place_to_unchain;
    vassert(((HWord)p & 1) == 0);
    vassert(is_addr48_to_ireg_EXACTLY_18B(p, 5 /*x5/t0*/,
-                                         (ULong)place_to_jump_to_EXPECTED));
+                                         (ULong)(HWord)place_to_jump_to_EXPECTED));
    vassert(p[18] == 0x82 && p[19] == 0x82);
 
    /* And what we want to change it to is:
@@ -2664,7 +2664,7 @@ VexInvalRange unchainXDirect_RISCV64(VexEndness  endness_host,
 
       The replacement has the same length as the original.
    */
-   (void)addr48_to_ireg_EXACTLY_18B(p, 5 /*x5/t0*/, (ULong)disp_cp_chain_me);
+   (void)addr48_to_ireg_EXACTLY_18B(p, 5 /*x5/t0*/, (ULong)(HWord)disp_cp_chain_me);
    p[18] = 0x82;
    p[19] = 0x89;
 
@@ -2686,7 +2686,7 @@ VexInvalRange patchProfInc_RISCV64(VexEndness   endness_host,
    vassert(p[18] == 0x83 && p[19] == 0x32 && p[20] == 0x03 && p[21] == 0x00);
    vassert(p[22] == 0x85 && p[23] == 0x02);
    vassert(p[24] == 0x23 && p[25] == 0x30 && p[26] == 0x53 && p[27] == 0x00);
-   (void)addr48_to_ireg_EXACTLY_18B(p, 6 /*x6/t1*/, (ULong)location_of_counter);
+   (void)addr48_to_ireg_EXACTLY_18B(p, 6 /*x6/t1*/, (ULong)(HWord)location_of_counter);
    VexInvalRange vir = {(HWord)p, 28};
    return vir;
 }

diff --git a/VEX/priv/host_riscv64_isel.c b/VEX/priv/host_riscv64_isel.c
index 6921a47db4d88fd1158f7bc4ba475bd893e7998d..c476d133c7e5df9ddccc5c64f0120168927f02ef 100644 (file)
--- a/VEX/priv/host_riscv64_isel.c
+++ b/VEX/priv/host_riscv64_isel.c
@@ -542,7 +542,7 @@ static Bool doHelperCall(/*OUT*/ UInt*   stackAdjustAfterCall,
       The same applies to nextFArgReg which records a number of used
       floating-point registers f10/fa0 .. f17/fa7.
     */
-   addInstr(env, RISCV64Instr_Call(*retloc, (Addr64)cee->addr, cond, nextArgReg,
+   addInstr(env, RISCV64Instr_Call(*retloc, (Addr64)(HWord)cee->addr, cond, nextArgReg,
                                    nextFArgReg));
 
    return True;

diff --git a/coregrind/m_gdbserver/valgrind-low-riscv64.c b/coregrind/m_gdbserver/valgrind-low-riscv64.c
index 75088fc1ec76b77d47b15cb590df45f1114625ad..5c200318c09c877e8bcee7b00bd2e5a77e8c0461 100644 (file)
--- a/coregrind/m_gdbserver/valgrind-low-riscv64.c
+++ b/coregrind/m_gdbserver/valgrind-low-riscv64.c
@@ -264,7 +264,7 @@ static CORE_ADDR** target_get_dtv (ThreadState *tst)
             void *private;
         } tcbhead_t;
    */
-   return (CORE_ADDR**)(void *)(riscv->guest_x4 - 2 * sizeof(void *));
+   return (CORE_ADDR**)(void *)((HWord)riscv->guest_x4 - 2 * sizeof(void *));
 }
 
 static struct valgrind_target_ops low_target = {