drm/amd/display: disable link before changing link settings

[ Upstream commit 15ae3b28f8ca406b449d36d36021e96b66aedb5d ]

[Why]
If link is already enabled at a different rate (for example 5.4 Gbps)
then calling VBIOS command table to switch to a new rate
(for example 2.7 Gbps) will not take effect.
This can lead to link training failure to occur.

[How]
If the requested link rate is different than the current link rate,
the link must be disabled in order to re-enable at the new
link rate.

In today's logic it is currently only impacting eDP since DP
connection types will always disable the link during display
detection, when initial link verification occurs.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 419e8de8c0f4890a1c24c5e15ae9e8910cfada6c..6072636da388a2564a04bb346ef1aa7b956fb0ab 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1399,6 +1399,15 @@ static enum dc_status enable_link_dp(
        /* get link settings for video mode timing */
        decide_link_settings(stream, &link_settings);
 
+       /* If link settings are different than current and link already enabled
+        * then need to disable before programming to new rate.
+        */
+       if (link->link_status.link_active &&
+               (link->cur_link_settings.lane_count != link_settings.lane_count ||
+                link->cur_link_settings.link_rate != link_settings.link_rate)) {
+               dp_disable_link_phy(link, pipe_ctx->stream->signal);
+       }
+
        pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
                        link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
        state->dccg->funcs->update_clocks(state->dccg, state, false);