media: rkisp1: Acquire pclk clock on i.MX8MP

The ISP instances in the NXP i.MX8MP need the input pixel clock to be
enabled in order to access the HDR stitching registers. The clock should
ideally be mandatory, but that would break backward compatibility with
old DT. Try to acquire it as an optional clock instead.

Link: https://lore.kernel.org/r/20250616011115.19515-5-laurent.pinchart@ideasonboard.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 0788b7a64ae9c3aa8599e0d1ce6354546b2c60e5..fb4ccf497bad981bc7a59eb699172b601d68d809 100644 (file)
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -584,6 +584,24 @@ static int rkisp1_init_clocks(struct rkisp1_device *rkisp1)
                return ret;
 
        rkisp1->clk_size = info->num_clocks;
+
+       /*
+        * On i.MX8MP the pclk clock is needed to access the HDR stitching
+        * registers, but wasn't required by DT bindings. Try to acquire it as
+        * an optional clock to avoid breaking backward compatibility.
+        */
+       if (info->isp_ver == RKISP1_V_IMX8MP) {
+               struct clk *clk;
+
+               clk = devm_clk_get_optional(rkisp1->dev, "pclk");
+               if (IS_ERR(clk))
+                       return dev_err_probe(rkisp1->dev, PTR_ERR(clk),
+                                            "Failed to acquire pclk clock\n");
+
+               if (clk)
+                       rkisp1->clks[rkisp1->clk_size++].clk = clk;
+       }
+
        return 0;
 }