]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
media: hantro: Prepare for other G2 codecs
authorAndrzej Pietrasiewicz <andrzej.p@collabora.com>
Tue, 16 Nov 2021 14:38:39 +0000 (14:38 +0000)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Mon, 22 Nov 2021 07:50:42 +0000 (07:50 +0000)
VeriSilicon Hantro G2 core supports other codecs besides hevc.
Factor out some common code in preparation for vp9 support.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/staging/media/hantro/Makefile
drivers/staging/media/hantro/hantro.h
drivers/staging/media/hantro/hantro_drv.c
drivers/staging/media/hantro/hantro_g2.c [new file with mode: 0644]
drivers/staging/media/hantro/hantro_g2_hevc_dec.c
drivers/staging/media/hantro/hantro_g2_regs.h
drivers/staging/media/hantro/hantro_hw.h

index 90036831fec4ce7db2fea9ef6c686b847bdd18e8..fe6d84871d074cbf061787b8945e0bcaf4c440a8 100644 (file)
@@ -12,6 +12,7 @@ hantro-vpu-y += \
                hantro_g1_mpeg2_dec.o \
                hantro_g2_hevc_dec.o \
                hantro_g1_vp8_dec.o \
+               hantro_g2.o \
                rockchip_vpu2_hw_jpeg_enc.o \
                rockchip_vpu2_hw_h264_dec.o \
                rockchip_vpu2_hw_mpeg2_dec.o \
index dd5e56765d4e8bd58b63bb7dcf8a0e72d9f0db09..d91eb2b1c50937b48f9a411292f0c9e0e772c158 100644 (file)
@@ -369,6 +369,13 @@ static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
        writel(val, vpu->dec_base + reg);
 }
 
+static inline void hantro_write_addr(struct hantro_dev *vpu,
+                                    unsigned long offset,
+                                    dma_addr_t addr)
+{
+       vdpu_write(vpu, addr & 0xffffffff, offset);
+}
+
 static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
 {
        u32 val = readl(vpu->dec_base + reg);
index fb82b9297a2bacf6f11d19fe178e87ea6e3791f5..bb72e5e208b72478ddcbc25bb5fbe1534e7ee5fe 100644 (file)
@@ -907,6 +907,11 @@ static int hantro_probe(struct platform_device *pdev)
        vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
        vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
 
+       /**
+        * TODO: Eventually allow taking advantage of full 64-bit address space.
+        * Until then we assume the MSB portion of buffers' base addresses is
+        * always 0 due to this masking operation.
+        */
        ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
        if (ret) {
                dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c
new file mode 100644 (file)
index 0000000..6f3e1f7
--- /dev/null
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Hantro VPU codec driver
+ *
+ * Copyright (C) 2021 Collabora Ltd, Andrzej Pietrasiewicz <andrzej.p@collabora.com>
+ */
+
+#include "hantro_hw.h"
+#include "hantro_g2_regs.h"
+
+void hantro_g2_check_idle(struct hantro_dev *vpu)
+{
+       int i;
+
+       for (i = 0; i < 3; i++) {
+               u32 status;
+
+               /* Make sure the VPU is idle */
+               status = vdpu_read(vpu, G2_REG_INTERRUPT);
+               if (status & G2_REG_INTERRUPT_DEC_E) {
+                       dev_warn(vpu->dev, "device still running, aborting");
+                       status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS;
+                       vdpu_write(vpu, status, G2_REG_INTERRUPT);
+               }
+       }
+}
index abae36f9b418205a4bbd703e1ccce2f78343609f..f62608b0b408bfa60e12cbc7de066d68419548b8 100644 (file)
@@ -8,20 +8,6 @@
 #include "hantro_hw.h"
 #include "hantro_g2_regs.h"
 
-#define HEVC_DEC_MODE  0xC
-
-#define BUS_WIDTH_32           0
-#define BUS_WIDTH_64           1
-#define BUS_WIDTH_128          2
-#define BUS_WIDTH_256          3
-
-static inline void hantro_write_addr(struct hantro_dev *vpu,
-                                    unsigned long offset,
-                                    dma_addr_t addr)
-{
-       vdpu_write(vpu, addr & 0xffffffff, offset);
-}
-
 static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
 {
        struct hantro_dev *vpu = ctx->dev;
@@ -566,23 +552,6 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
        hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
 }
 
-static void hantro_g2_check_idle(struct hantro_dev *vpu)
-{
-       int i;
-
-       for (i = 0; i < 3; i++) {
-               u32 status;
-
-               /* Make sure the VPU is idle */
-               status = vdpu_read(vpu, G2_REG_INTERRUPT);
-               if (status & G2_REG_INTERRUPT_DEC_E) {
-                       dev_warn(vpu->dev, "device still running, aborting");
-                       status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS;
-                       vdpu_write(vpu, status, G2_REG_INTERRUPT);
-               }
-       }
-}
-
 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
 {
        struct hantro_dev *vpu = ctx->dev;
index 24b18f839ff8a5d295e3f9f1c31360afd48b2d43..136ba6d98a1f3022d0f10c85878cfef307758bca 100644 (file)
 #define G2_REG_INTERRUPT_DEC_IRQ_DIS   BIT(4)
 #define G2_REG_INTERRUPT_DEC_E         BIT(0)
 
+#define HEVC_DEC_MODE                  0xc
+
+#define BUS_WIDTH_32                   0
+#define BUS_WIDTH_64                   1
+#define BUS_WIDTH_128                  2
+#define BUS_WIDTH_256                  3
+
 #define g2_strm_swap           G2_DEC_REG(2, 28, 0xf)
 #define g2_dirmv_swap          G2_DEC_REG(2, 20, 0xf)
 
index 2f85430682d86fb7eb3d3060ffa940404c0d6568..1d869abf90b2147051b09c45ddede12ad331e0d9 100644 (file)
@@ -312,4 +312,6 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
 void hantro_vp8_prob_update(struct hantro_ctx *ctx,
                            const struct v4l2_ctrl_vp8_frame *hdr);
 
+void hantro_g2_check_idle(struct hantro_dev *vpu);
+
 #endif /* HANTRO_HW_H_ */