arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1

Add a DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through
the PMOD1_3A interface available on the Renesas RZ SMARC Carrier II
board.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 698f790bd42524ba56623d032154641e87b72f5b..c81d0f7f528a5f121bbbbfbf4ab05548025c6bcc 100644 (file)
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -143,6 +143,9 @@ r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc
 dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb
 
 dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
+r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
+dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
new file mode 100644 (file)
index 0000000..4a81e3a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ *
+ * [Connection]
+ *
+ * SMARC Carrier II EVK
+ * +--------------------------------------------+
+ * |PMOD1_3A (PMOD1 PIN HEADER)                        |
+ * |   SCIF1_CTS# (pin1)  (pin7)  PMOD1_GPIO10 |
+ * |   SCIF1_TXD  (pin2)  (pin8)  PMOD1_GPIO11 |
+ * |   SCIF1_RXD  (pin3)  (pin9)  PMOD1_GPIO12 |
+ * |   SCIF1_RTS# (pin4)  (pin10) PMOD1_GPIO13 |
+ * |   GND        (pin5)  (pin11) GND          |
+ * |   PWR_PMOD1  (pin6)  (pin12) GND          |
+ * +--------------------------------------------+
+ *
+ * The following switches should be set as follows for SCIF1:
+ * - SW_CONFIG2:  ON
+ * - SW_OPT_MUX4: ON
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+#include "rzg3s-smarc-switches.h"
+
+&pinctrl {
+       scif1_pins: scif1-pins {
+               pinmux = <RZG2L_PORT_PINMUX(14, 0, 1)>, /* TXD */
+                        <RZG2L_PORT_PINMUX(14, 1, 1)>, /* RXD */
+                        <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS# */
+                        <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS# */
+       };
+};
+
+#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON
+&scif1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&scif1_pins>;
+       uart-has-rtscts;
+       status = "okay";
+};
+#endif

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
index 5c27c043afef47fc1f6fabdcf7c1610121072e3b..bbf908a5322c91a6ef1d8d7a02a98c76e44673e9 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -29,4 +29,12 @@
 #define SW_CONFIG2     SW_OFF
 #define SW_CONFIG3     SW_ON
 
+/*
+ * SW_OPT_MUX[x] switches' states:
+ * @SW_OPT_MUX4:
+ *     SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART
+ *     SW_ON  - The SMARC SER0 signals are routed to PMOD1
+ */
+#define SW_OPT_MUX4    SW_ON
+
 #endif /* __RZG3S_SMARC_SWITCHES_H__ */

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 0851e0b7ed408df650e0de3c97595202b1d55e52..5e044a4d023436425c3ee51518998463fe91332b 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -12,6 +12,7 @@
 / {
        aliases {
                i2c0 = &i2c0;
+               serial0 = &scif1;
                serial1 = &scif3;
                serial3 = &scif0;
                mmc1 = &sdhi1;