sim: cr16: add missing break statement

Doesn't seem to make sense for this to fall through
(although I'm not an expert in this ISA).

diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c
index 9a2363a6d5283b3dc9e696e22f21c9309a98ac24..0fa9a91c0132cc723805770f966579a81e64580d 100644 (file)
--- a/sim/cr16/interp.c
+++ b/sim/cr16/interp.c
@@ -288,6 +288,7 @@ get_operands (operand_desc *s, uint64_t ins, int isize, int nops)
             OP[i] = (ins) & 0x3FFF;
             OP[++i] = (ins >> 14) & 0x1;     /* get 1 bit for index-reg.  */
             OP[++i] = (ins >> 16) & 0xF;     /* get 4 bit for reg.  */
+            break;
           case rindex7_abs20:
           case rindex8_abs20:
             OP[i] = (ins) & 0xFFFFF;