[Morello] Add iclass to add/sub instructions

Add the proper iclass to add/sub so code relying on instruction
decoding can extract precise information.

opcodes/ChangeLog:

2020-10-20  Luis Machado  <luis.machado@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Update iclass field
	for add/sub

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 58df5c059d1229a1876488b2132ea978b146c391..427467fe7e15526c074b753a9843cdac8b589e62 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-10-20  Luis Machado  <luis.machado@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Update iclass field
+       for add/sub
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * aarch64-dis.c (get_sym_code_type): Fix C64 PLT disassembly.

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 25955c1e87b69c356f77fe302454388db4e89d31..24f92130254f3687c0ad51560bc306353a652f40 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3998,9 +3998,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
   A64C_INSN ("mov", 0x2a1f03e0, 0x7fffffe0, a64c, OP_MOV_C_ZR, OP2 (Cad, Can), QL2_A64C_CA_CA, F_ALIAS | F_SF | F_P1),
   A64C_INSN ("cpytype", 0xc2c02400, 0xffe0fc00, a64c, 0, OP3 (Cad, Can, Cam), QL3_A64C_CA_CA_CA, 0),
   A64C_INSN ("cpyvalue", 0xc2c06400, 0xffe0fc00, a64c, 0, OP3 (Cad, Can, Cam), QL3_A64C_CA_CA_CA, 0),
-  A64C_INSN ("add", 0x02000000, 0xff800000, a64c, OP_A64C_ADD, OP3 (Cad_SP, Can_SP, AIMM), QL3_A64C_CA_CA_NIL, 0),
+  A64C_INSN ("add", 0x02000000, 0xff800000, addsub_imm, OP_A64C_ADD, OP3 (Cad_SP, Can_SP, AIMM), QL3_A64C_CA_CA_NIL, 0),
   A64C_INSN ("add", 0xc2a00000, 0xffe00000, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_Rm_EXT), QL3_A64C_CA_CA_R, 0),
-  A64C_INSN ("sub", 0x02800000, 0xff800000, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_AIMM), QL3_A64C_CA_CA_NIL, 0),
+  A64C_INSN ("sub", 0x02800000, 0xff800000, addsub_imm, 0, OP3 (Cad_SP, Can_SP, A64C_AIMM), QL3_A64C_CA_CA_NIL, 0),
   A64C_INSN ("subs", 0xc2e09800, 0xffe0fc00, a64c, 0, OP3 (Rd, Can, Cam), QL3_A64C_X_CA_CA, F_HAS_ALIAS),
   CORE_INSN ("cmp",  0xc2e0981f, 0xffe0fc1f, a64c, 0, OP2 (Can, Cam), QL2_A64C_CA_CA, F_ALIAS),
   A64C_INSN ("alignd", 0xc2c01800, 0xffe07c00, a64c, 0, OP3 (Cad_SP, Can_SP, IMM_2), QL3_A64C_CA_CA_NIL, 0),