Merge tag 'irqchip-gic-v5-host' into kvmarm/next

GICv5 initial host support

Add host kernel support for the new arm64 GICv5 architecture, which is
quite a departure from the previous ones.

Include support for the full gamut of the architecture (interrupt
routing and delivery to CPUs, wired interrupts, MSIs, and interrupt
translation).

* tag 'irqchip-gic-v5-host': (32 commits)
  arm64: smp: Fix pNMI setup after GICv5 rework
  arm64: Kconfig: Enable GICv5
  docs: arm64: gic-v5: Document booting requirements for GICv5
  irqchip/gic-v5: Add GICv5 IWB support
  irqchip/gic-v5: Add GICv5 ITS support
  irqchip/msi-lib: Add IRQ_DOMAIN_FLAG_FWNODE_PARENT handling
  irqchip/gic-v3: Rename GICv3 ITS MSI parent
  PCI/MSI: Add pci_msi_map_rid_ctlr_node() helper function
  of/irq: Add of_msi_xlate() helper function
  irqchip/gic-v5: Enable GICv5 SMP booting
  irqchip/gic-v5: Add GICv5 LPI/IPI support
  irqchip/gic-v5: Add GICv5 IRS/SPI support
  irqchip/gic-v5: Add GICv5 PPI support
  arm64: Add support for GICv5 GSB barriers
  arm64: smp: Support non-SGIs for IPIs
  arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability
  arm64: cpucaps: Rename GICv3 CPU interface capability
  arm64: Disable GICv5 read/write/instruction traps
  arm64/sysreg: Add ICH_HFGITR_EL2
  arm64/sysreg: Add ICH_HFGWTR_EL2
  ...

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --cc arch/arm64/kernel/cpufeature.c
index 72ccf9ed4d05289c287126db987294ec4330a1b8,2fa26129762c547458b15fc674af701c7cb251a4..4dece9ca68bc6be6ce47861a046b9f6434d57195
--- 1/arch/arm64/kernel/cpufeature.c
--- 2/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -3063,13 -3061,13 +3063,20 @@@ static const struct arm64_cpu_capabilit
                .matches = has_pmuv3,
        },
  #endif
 +      {
 +              .desc = "SCTLR2",
 +              .capability = ARM64_HAS_SCTLR2,
 +              .type = ARM64_CPUCAP_SYSTEM_FEATURE,
 +              .matches = has_cpuid_feature,
 +              ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP)
 +      },
+       {
+               .desc = "GICv5 CPU interface",
+               .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
+               .capability = ARM64_HAS_GICV5_CPUIF,
+               .matches = has_cpuid_feature,
+               ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP)
+       },
        {},
  };
  

diff --cc arch/arm64/tools/cpucaps
Simple merge