[Morello] Implement LDUR/STUR fallback for LDR/STR in altbase mode

Give the ops saner names instead of _2, _3, etc.

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* config/tc-aarch64.c (parse_operand): Reuse ADDR_UIMM12 code
	in CAPADDR_UIMM9.
	(try_to_encode_as_unscaled_ldst, fix_insn): Add support for
	altbase loads and stores.
	* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
	* testsuite/gas/aarch64/morello_ldst.d: Likewise.
	* testsuite/gas/aarch64/morello_ldst.s: Likewise.

include/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* opcode/aarch64.h (aarch64_op): Add members for altbase LDUR
	and STUR.  Rename existing LDUR ops.

opcodes/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Change OP of LDUR/STUR
	instructions.
	* aarch64-opc-2.c: Regenerate.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 29498187fab10de5d5744d6e7b20dd8e0bd3f09c..f6ad769d5ca14f97df0d0de8f168c251ed654b08 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * config/tc-aarch64.c (parse_operand): Reuse ADDR_UIMM12 code
+       in CAPADDR_UIMM9.
+       (try_to_encode_as_unscaled_ldst, fix_insn): Add support for
+       altbase loads and stores.
+       * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
+       * testsuite/gas/aarch64/morello_ldst.d: Likewise.
+       * testsuite/gas/aarch64/morello_ldst.s: Likewise.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b2ac36fbf9bfc672b51be40aea221270ffaccdfd..c17168098ef4eef4211bde833a8034c43f1a790b 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6728,28 +6728,16 @@ addr_simm:
 
        case AARCH64_OPND_CAPADDR_UIMM9:
          po_misc_or_fail (parse_cap_address (&str, info, opcode->iclass));
-         if (info->addr.pcrel || info->addr.offset.is_reg
-             || !info->addr.preind || info->addr.writeback)
-           {
-             set_syntax_error (_("invalid addressing mode"));
-             goto failure;
-           }
          if (inst.reloc.type != BFD_RELOC_UNUSED)
            {
              set_syntax_error (_("relocation not allowed"));
              goto failure;
            }
-         if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
-           info->addr.offset.imm = inst.reloc.exp.X_add_number;
-         else
-           {
-             set_syntax_error (_("Invalid offset constant"));
-             goto failure;
-           }
-         break;
+         goto addr_uimm;
 
        case AARCH64_OPND_ADDR_UIMM12:
          po_misc_or_fail (parse_address (&str, info));
+addr_uimm:
          if (info->addr.pcrel || info->addr.offset.is_reg
              || !info->addr.preind || info->addr.writeback)
            {
@@ -7971,8 +7959,13 @@ try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
   int idx;
   enum aarch64_op new_op;
   const aarch64_opcode *new_opcode;
+  enum aarch64_opnd target;
+
+  gas_assert (instr->opcode->iclass == ldst_pos
+             || instr->opcode->iclass == ldst_altbase);
 
-  gas_assert (instr->opcode->iclass == ldst_pos);
+  target = (instr->opcode->iclass == ldst_pos ? AARCH64_OPND_ADDR_SIMM9
+           : AARCH64_OPND_CAPADDR_SIMM9);
 
   switch (instr->opcode->op)
     {
@@ -7983,17 +7976,19 @@ try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
     case OP_STRH_POS: new_op = OP_STURH; break;
     case OP_LDRSH_POS: new_op = OP_LDURSH; break;
     case OP_LDR_POS: new_op = OP_LDUR; break;
-    case OP_LDR_POS_2: new_op = OP_LDUR_2; break;
-    case OP_LDR_POS_3: new_op = OP_LDUR_3; break;
-    case OP_LDR_POS_4: new_op = OP_LDUR_4; break;
     case OP_STR_POS: new_op = OP_STUR; break;
-    case OP_STR_POS_2: new_op = OP_STUR_2; break;
-    case OP_STR_POS_3: new_op = OP_STUR_3; break;
-    case OP_STR_POS_4: new_op = OP_STUR_4; break;
     case OP_LDRF_POS: new_op = OP_LDURV; break;
     case OP_STRF_POS: new_op = OP_STURV; break;
     case OP_LDRSW_POS: new_op = OP_LDURSW; break;
     case OP_PRFM_POS: new_op = OP_PRFUM; break;
+    case OP_LDR_POS_C: new_op = OP_LDUR_C; break;
+    case OP_STR_POS_C: new_op = OP_STUR_C; break;
+    case OP_LDRB_POS_A:new_op = OP_LDURB_A; break;
+    case OP_STRB_POS_A: new_op = OP_STURB_A; break;
+    case OP_LDR_POS_AC: new_op = OP_LDUR_AC; break;
+    case OP_LDR_POS_AX: new_op = OP_LDUR_AX; break;
+    case OP_STR_POS_AC: new_op = OP_STUR_AC; break;
+    case OP_STR_POS_AX: new_op = OP_STUR_AX; break;
     default: new_op = OP_NIL; break;
     }
 
@@ -8008,11 +8003,11 @@ try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
 
   aarch64_replace_opcode (instr, new_opcode);
 
-  /* Clear up the ADDR_SIMM9's qualifier; otherwise the
+  /* Clear up the address operand's qualifier; otherwise the
      qualifier matching may fail because the out-of-date qualifier will
      prevent the operand being updated with a new and correct qualifier.  */
   idx = aarch64_operand_index (instr->opcode->operands,
-                              AARCH64_OPND_ADDR_SIMM9);
+                              target);
   gas_assert (idx == 1);
   instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 
@@ -8217,6 +8212,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
       fix_mov_imm_insn (fixP, buf, new_inst, value);
       break;
 
+    case AARCH64_OPND_CAPADDR_UIMM9:
     case AARCH64_OPND_A64C_ADDR_SIMM9:
     case AARCH64_OPND_A64C_ADDR_SIMM7:
     case AARCH64_OPND_ADDR_SIMM7:
@@ -8251,7 +8247,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
          put_aarch64_insn (buf, new_inst->value);
          break;
        }
-      else if (new_inst->opcode->iclass == ldst_pos
+      else if ((new_inst->opcode->iclass == ldst_pos
+               || new_inst->opcode->iclass == ldst_altbase)
               && try_to_encode_as_unscaled_ldst (new_inst))
        {
          put_aarch64_insn (buf, new_inst->value);

diff --git a/gas/testsuite/gas/aarch64/morello_ldst-c64.d b/gas/testsuite/gas/aarch64/morello_ldst-c64.d
index 9bbcfb75ab2d4928221a4bb7169e2375de4c031d..5b6562ee49bae68a97a9d8d490d9599672ae0c44 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst-c64.d
+++ b/gas/testsuite/gas/aarch64/morello_ldst-c64.d
@@ -370,3 +370,47 @@ Disassembly of section \.text:
 .*:    825ff7e4        strb    w4, \[sp, #511\]
 .*:    824207e4        strb    w4, \[sp, #32\]
 .*:    824007e4        strb    w4, \[sp\]
+.*:    a25f0304        ldur    c4, \[c24, #-16\]
+.*:    a2500304        ldur    c4, \[c24, #-256\]
+.*:    a21f0304        stur    c4, \[c24, #-16\]
+.*:    a2100304        stur    c4, \[c24, #-256\]
+.*:    a25f03e4        ldur    c4, \[csp, #-16\]
+.*:    a25003e4        ldur    c4, \[csp, #-256\]
+.*:    a21f03e4        stur    c4, \[csp, #-16\]
+.*:    a21003e4        stur    c4, \[csp, #-256\]
+.*:    e2df0d84        ldur    c4, \[x12, #-16\]
+.*:    e2d00d84        ldur    c4, \[x12, #-256\]
+.*:    e2df0584        ldur    x4, \[x12, #-16\]
+.*:    e2d00584        ldur    x4, \[x12, #-256\]
+.*:    e29f0584        ldur    w4, \[x12, #-16\]
+.*:    e2900584        ldur    w4, \[x12, #-256\]
+.*:    e29f0d84        stur    c4, \[x12, #-16\]
+.*:    e2900d84        stur    c4, \[x12, #-256\]
+.*:    e2df0184        stur    x4, \[x12, #-16\]
+.*:    e2d00184        stur    x4, \[x12, #-256\]
+.*:    e29f0184        stur    w4, \[x12, #-16\]
+.*:    e2900184        stur    w4, \[x12, #-256\]
+.*:    e2df0fe4        ldur    c4, \[sp, #-16\]
+.*:    e2d00fe4        ldur    c4, \[sp, #-256\]
+.*:    e2df07e4        ldur    x4, \[sp, #-16\]
+.*:    e2d007e4        ldur    x4, \[sp, #-256\]
+.*:    e29f07e4        ldur    w4, \[sp, #-16\]
+.*:    e29007e4        ldur    w4, \[sp, #-256\]
+.*:    e29f0fe4        stur    c4, \[sp, #-16\]
+.*:    e2900fe4        stur    c4, \[sp, #-256\]
+.*:    e2df03e4        stur    x4, \[sp, #-16\]
+.*:    e2d003e4        stur    x4, \[sp, #-256\]
+.*:    e29f03e4        stur    w4, \[sp, #-16\]
+.*:    e29003e4        stur    w4, \[sp, #-256\]
+.*:    e21ff584        ldurb   w4, \[x12, #-1\]
+.*:    e21f0584        ldurb   w4, \[x12, #-16\]
+.*:    e2100584        ldurb   w4, \[x12, #-256\]
+.*:    e21ff184        sturb   w4, \[x12, #-1\]
+.*:    e21f0184        sturb   w4, \[x12, #-16\]
+.*:    e2100184        sturb   w4, \[x12, #-256\]
+.*:    e21ff7e4        ldurb   w4, \[sp, #-1\]
+.*:    e21f07e4        ldurb   w4, \[sp, #-16\]
+.*:    e21007e4        ldurb   w4, \[sp, #-256\]
+.*:    e21ff3e4        sturb   w4, \[sp, #-1\]
+.*:    e21f03e4        sturb   w4, \[sp, #-16\]
+.*:    e21003e4        sturb   w4, \[sp, #-256\]

diff --git a/gas/testsuite/gas/aarch64/morello_ldst.d b/gas/testsuite/gas/aarch64/morello_ldst.d
index 73b6f1141bef9d1f07d571b21f26541baba228c0..19c9c60b5350913f6c1e2e00080a66a3010593f5 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst.d
+++ b/gas/testsuite/gas/aarch64/morello_ldst.d
@@ -369,3 +369,47 @@ Disassembly of section \.text:
 .*:    825ff7e4        strb    w4, \[csp, #511\]
 .*:    824207e4        strb    w4, \[csp, #32\]
 .*:    824007e4        strb    w4, \[csp\]
+.*:    a25f0164        ldur    c4, \[x11, #-16\]
+.*:    a2500164        ldur    c4, \[x11, #-256\]
+.*:    a21f0164        stur    c4, \[x11, #-16\]
+.*:    a2100164        stur    c4, \[x11, #-256\]
+.*:    a25f03e4        ldur    c4, \[sp, #-16\]
+.*:    a25003e4        ldur    c4, \[sp, #-256\]
+.*:    a21f03e4        stur    c4, \[sp, #-16\]
+.*:    a21003e4        stur    c4, \[sp, #-256\]
+.*:    e2df0ea4        ldur    c4, \[c21, #-16\]
+.*:    e2d00ea4        ldur    c4, \[c21, #-256\]
+.*:    e2df06a4        ldur    x4, \[c21, #-16\]
+.*:    e2d006a4        ldur    x4, \[c21, #-256\]
+.*:    e29f06a4        ldur    w4, \[c21, #-16\]
+.*:    e29006a4        ldur    w4, \[c21, #-256\]
+.*:    e29f0ea4        stur    c4, \[c21, #-16\]
+.*:    e2900ea4        stur    c4, \[c21, #-256\]
+.*:    e2df02a4        stur    x4, \[c21, #-16\]
+.*:    e2d002a4        stur    x4, \[c21, #-256\]
+.*:    e29f02a4        stur    w4, \[c21, #-16\]
+.*:    e29002a4        stur    w4, \[c21, #-256\]
+.*:    e2df0fe4        ldur    c4, \[csp, #-16\]
+.*:    e2d00fe4        ldur    c4, \[csp, #-256\]
+.*:    e2df07e4        ldur    x4, \[csp, #-16\]
+.*:    e2d007e4        ldur    x4, \[csp, #-256\]
+.*:    e29f07e4        ldur    w4, \[csp, #-16\]
+.*:    e29007e4        ldur    w4, \[csp, #-256\]
+.*:    e29f0fe4        stur    c4, \[csp, #-16\]
+.*:    e2900fe4        stur    c4, \[csp, #-256\]
+.*:    e2df03e4        stur    x4, \[csp, #-16\]
+.*:    e2d003e4        stur    x4, \[csp, #-256\]
+.*:    e29f03e4        stur    w4, \[csp, #-16\]
+.*:    e29003e4        stur    w4, \[csp, #-256\]
+.*:    e21ff6a4        ldurb   w4, \[c21, #-1\]
+.*:    e21f06a4        ldurb   w4, \[c21, #-16\]
+.*:    e21006a4        ldurb   w4, \[c21, #-256\]
+.*:    e21ff2a4        sturb   w4, \[c21, #-1\]
+.*:    e21f02a4        sturb   w4, \[c21, #-16\]
+.*:    e21002a4        sturb   w4, \[c21, #-256\]
+.*:    e21ff7e4        ldurb   w4, \[csp, #-1\]
+.*:    e21f07e4        ldurb   w4, \[csp, #-16\]
+.*:    e21007e4        ldurb   w4, \[csp, #-256\]
+.*:    e21ff3e4        sturb   w4, \[csp, #-1\]
+.*:    e21f03e4        sturb   w4, \[csp, #-16\]
+.*:    e21003e4        sturb   w4, \[csp, #-256\]

diff --git a/gas/testsuite/gas/aarch64/morello_ldst.s b/gas/testsuite/gas/aarch64/morello_ldst.s
index 89b2cdb3d1b0ae9c253810b21783a774f0dfdaf5..0cf1ae704854f6b0f96cee53753ab1bbafd4a8c9 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst.s
+++ b/gas/testsuite/gas/aarch64/morello_ldst.s
@@ -217,3 +217,34 @@ morello_alt_imm ALTSP
        .endm
 morello_alt_uimmw w4, ALTVAREG
 morello_alt_uimmw w4, ALTSP
+
+// Substitute LDR/STR with negative immediate with LDUR/STUR.
+       .macro morello_uimm_sub xnsp
+         .irp op, ldr, str
+           \op    c4, [\xnsp, #-16]
+           \op    c4, [\xnsp, #-256]
+         .endr
+       .endm
+morello_uimm_sub VAREG
+morello_uimm_sub SP_
+
+       .macro morello_alt_uimm_sub xnsp
+         .irp op, ldr, str
+           .irp reg, c4, x4, w4
+             \op    \reg, [\xnsp, #-16]
+             \op    \reg, [\xnsp, #-256]
+           .endr
+         .endr
+       .endm
+morello_alt_uimm_sub ALTVAREG
+morello_alt_uimm_sub ALTSP
+
+       .macro morello_alt_uimmb_sub wt, xnsp
+         .irp op, ldrb, strb
+           \op    \wt, [\xnsp, #-1]
+           \op    \wt, [\xnsp, #-16]
+           \op    \wt, [\xnsp, #-256]
+         .endr
+       .endm
+morello_alt_uimmb_sub w4, ALTVAREG
+morello_alt_uimmb_sub w4, ALTSP

diff --git a/include/ChangeLog b/include/ChangeLog
index eac30ef0d4f14cb9366d1f6ce4cb010151aaf9cb..a6a169a25bdc060a5693803fcaa68c9898660ea5 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * opcode/aarch64.h (aarch64_op): Add members for altbase LDUR
+       and STUR.  Rename existing LDUR ops.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * opcode/aarch64.c (F_NOSHIFT): New flag.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a147b8ccb1eb05a8eb1acf3ae0981038c1d5f061..69a236a8670b0f2cfde26f2a80da72ad69b88ba4 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -690,12 +690,6 @@ enum aarch64_op
   OP_LDRSH_POS,
   OP_STR_POS,
   OP_LDR_POS,
-  OP_STR_POS_2,
-  OP_LDR_POS_2,
-  OP_STR_POS_3,
-  OP_LDR_POS_3,
-  OP_STR_POS_4,
-  OP_LDR_POS_4,
   OP_STRF_POS,
   OP_LDRF_POS,
   OP_LDRSW_POS,
@@ -709,17 +703,29 @@ enum aarch64_op
   OP_LDURSH,
   OP_STUR,
   OP_LDUR,
-  OP_LDUR_2,
-  OP_STUR_2,
-  OP_LDUR_3,
-  OP_STUR_3,
-  OP_LDUR_4,
-  OP_STUR_4,
   OP_STURV,
   OP_LDURV,
   OP_LDURSW,
   OP_PRFUM,
 
+  OP_STRB_POS_A,
+  OP_LDRB_POS_A,
+  OP_STR_POS_C,
+  OP_LDR_POS_C,
+  OP_STR_POS_AC,
+  OP_LDR_POS_AC,
+  OP_STR_POS_AX,
+  OP_LDR_POS_AX,
+
+  OP_STURB_A,
+  OP_LDURB_A,
+  OP_STUR_C,
+  OP_LDUR_C,
+  OP_STUR_AC,
+  OP_LDUR_AC,
+  OP_STUR_AX,
+  OP_LDUR_AX,
+
   OP_LDR_LIT,
   OP_LDR_LIT_2,
   OP_LDRV_LIT,

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 159c19f26f956e8fcfaa52a5152c9e8dafc717be..434b0ee343b302c89acdb49f39c38b0fa9bcd68e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Change OP of LDUR/STUR
+       instructions.
+       * aarch64-opc-2.c: Regenerate.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * aarch64-asm.c (aarch64_ins_addr_uimm): Shift only if

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index f938d4873f3686f306ef134cf06ed7c88be8085c..972cc7713e4e7342008a204b7f66b039e6ea1a29 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -280,12 +280,6 @@ static const unsigned op_enum_table [] =
   896,
   897,
   898,
-  1275,
-  1274,
-  1301,
-  1296,
-  1302,
-  1297,
   892,
   893,
   899,
@@ -298,16 +292,26 @@ static const unsigned op_enum_table [] =
   929,
   930,
   931,
-  1282,
-  1283,
-  1306,
-  1310,
-  1307,
-  1311,
   925,
   926,
   932,
   933,
+  1316,
+  1314,
+  1275,
+  1274,
+  1301,
+  1296,
+  1302,
+  1297,
+  1330,
+  1329,
+  1283,
+  1282,
+  1310,
+  1306,
+  1311,
+  1307,
   987,
   1273,
   988,

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 9abc02025b0898878a39684d2904611538e6dddb..eeb8fd77d45bc94caa1e03d361431bec5ded0d48 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4065,16 +4065,16 @@ struct aarch64_opcode aarch64_opcode_table[] =
   A64C_INSN ("stp", 0x22800000, 0xbfc00000, ldstpair_indexed, 0, OP3 (Cat, Cat2, A64C_ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0),
 
   A64C_INSN ("ldr", 0x82000000, 0xffc00000, loadlit, OP_LDR_LIT_2, OP2 (Cat, ADDR_PCREL17), QL2_A64C_CA_PCREL, 0),
-  A64C_INSN ("ldr", 0xc2400000, 0xffc00000, ldst_pos, OP_LDR_POS_2, OP2 (Cat, ADDR_UIMM12), QL2_A64C_CA_ADDR, 0),
-  A64C_INSN ("str", 0xc2000000, 0xffc00000, ldst_pos, OP_STR_POS_2, OP2 (Cat, ADDR_UIMM12), QL2_A64C_CA_ADDR, 0),
+  A64C_INSN ("ldr", 0xc2400000, 0xffc00000, ldst_pos, OP_LDR_POS_C, OP2 (Cat, ADDR_UIMM12), QL2_A64C_CA_ADDR, 0),
+  A64C_INSN ("str", 0xc2000000, 0xffc00000, ldst_pos, OP_STR_POS_C, OP2 (Cat, ADDR_UIMM12), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("ldr", 0xa2400400, 0xffe00400, ldst_imm9, 0, OP2 (Cat, A64C_ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("str", 0xa2000400, 0xffe00400, ldst_imm9, 0, OP2 (Cat, A64C_ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("ldr", 0xa2600800, 0xffe00c00, ldst_regoff, 0, OP2 (Cat, ADDR_REGOFF), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("str", 0xa2200800, 0xffe00c00, ldst_regoff, 0, OP2 (Cat, ADDR_REGOFF), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("ldtr", 0xa2400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("sttr", 0xa2000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
-  A64C_INSN ("ldur", 0xa2400000, 0xffe00c00, ldst_unscaled, OP_LDUR_2, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
-  A64C_INSN ("stur", 0xa2000000, 0xffe00c00, ldst_unscaled, OP_STUR_2, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
+  A64C_INSN ("ldur", 0xa2400000, 0xffe00c00, ldst_unscaled, OP_LDUR_C, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
+  A64C_INSN ("stur", 0xa2000000, 0xffe00c00, ldst_unscaled, OP_STUR_C, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
 
   A64C_INSN ("ldct", 0xc2c4b000, 0xfffffc00, a64c, 0, OP2 (Rt, ADDR_SIMPLE), QL2_A64C_X_ADDR, 0),
   A64C_INSN ("stct", 0xc2c49000, 0xfffffc00, a64c, 0, OP2 (Rt, ADDR_SIMPLE), QL2_A64C_X_ADDR, 0),
@@ -4092,28 +4092,28 @@ struct aarch64_opcode aarch64_opcode_table[] =
   A64C_INSN ("stlr", 0x421f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Cat, CAPADDR_SIMPLE), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("stlr", 0x423ffc00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
   A64C_INSN ("stlrb", 0x423f7c00, 0xfffffc00, ldstexcl, 0, OP2 (Wt, CAPADDR_SIMPLE), QL2_A64C_W_CAPADDR, 0),
-  A64C_INSN ("ldr", 0x82600000, 0xffe00c00, ldst_altbase, OP_LDR_POS_3, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
-  A64C_INSN ("ldr", 0x82600800, 0xffe00800, ldst_altbase, OP_LDR_POS_4, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
+  A64C_INSN ("ldr", 0x82600000, 0xffe00c00, ldst_altbase, OP_LDR_POS_AC, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
+  A64C_INSN ("ldr", 0x82600800, 0xffe00800, ldst_altbase, OP_LDR_POS_AX, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
   A64C_INSN ("ldr", 0xc2e00c00, 0xffe00c00, ldst_altbase, 0, OP2 (Cat, CAPADDR_REGOFF), QL2_A64C_CA_CAPADDR, 0),
   A64C_INSN ("ldr", 0x82e00000, 0xffe00800, ldst_altbase, 0, OP2 (Rsz, CAPADDR_REGOFF), QL2_A64C_R_CAPADDR, 0),
   A64C_INSN ("ldr", 0x82e00800, 0xffe00800, ldst_altbase, 0, OP2 (Ft, CAPADDR_REGOFF), QL2_A64C_FP_CAPADDR, 0),
-  A64C_INSN ("str", 0x82400000, 0xffe00c00, ldst_altbase, OP_STR_POS_3, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
-  A64C_INSN ("str", 0x82400800, 0xffe00800, ldst_altbase, OP_STR_POS_4, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
+  A64C_INSN ("str", 0x82400000, 0xffe00c00, ldst_altbase, OP_STR_POS_AC, OP2 (Cat, CAPADDR_UIMM9), QL2_A64C_CA_CAPADDR, 0),
+  A64C_INSN ("str", 0x82400800, 0xffe00800, ldst_altbase, OP_STR_POS_AX, OP2 (Rsz, CAPADDR_UIMM9), QL2_A64C_R_CAPADDR, 0),
   A64C_INSN ("str", 0xc2e00400, 0xffe00c00, ldst_altbase, 0, OP2 (Cat, CAPADDR_REGOFF), QL2_A64C_CA_CAPADDR, 0),
   A64C_INSN ("str", 0x82a00000, 0xffe00800, ldst_altbase, 0, OP2 (Rsz, CAPADDR_REGOFF), QL2_A64C_R_CAPADDR, 0),
   A64C_INSN ("str", 0x82a00800, 0xffe00800, ldst_altbase, 0, OP2 (Ft, CAPADDR_REGOFF), QL2_A64C_FP_CAPADDR, 0),
-  A64C_INSN ("ldur", 0xe2c00c00, 0xffe00c00, ldst_altbase, OP_LDUR_3, OP2 (Cat, CAPADDR_SIMM9), QL2_A64C_CA_CAPADDR, 0),
-  A64C_INSN ("ldur", 0xe2800400, 0xffa00c00, ldst_altbase, OP_LDUR_4, OP2 (Rsz2, CAPADDR_SIMM9), QL2_A64C_R_CAPADDR, 0),
+  A64C_INSN ("ldur", 0xe2c00c00, 0xffe00c00, ldst_altbase, OP_LDUR_AC, OP2 (Cat, CAPADDR_SIMM9), QL2_A64C_CA_CAPADDR, 0),
+  A64C_INSN ("ldur", 0xe2800400, 0xffa00c00, ldst_altbase, OP_LDUR_AX, OP2 (Rsz2, CAPADDR_SIMM9), QL2_A64C_R_CAPADDR, 0),
   A64C_INSN ("ldur", 0xe2200400, 0xff200c00, ldst_altbase, 0, OP2 (Fsz, CAPADDR_SIMM9), QL_S_2SAME, 0),
   A64C_INSN ("ldur", 0xe2200c00, 0xffe00c00, ldst_altbase, 0, OP2 (St, CAPADDR_SIMM9), QL_I2SAMEQ, 0),
-  A64C_INSN ("stur", 0xe2800c00, 0xffe00c00, ldst_altbase, OP_STUR_3, OP2 (Cat, CAPADDR_SIMM9), QL2_A64C_CA_CAPADDR, 0),
-  A64C_INSN ("stur", 0xe2800000, 0xffa00c00, ldst_altbase, OP_STUR_4, OP2 (Rsz2, CAPADDR_SIMM9), QL2_A64C_R_CAPADDR, 0),
+  A64C_INSN ("stur", 0xe2800c00, 0xffe00c00, ldst_altbase, OP_STUR_AC, OP2 (Cat, CAPADDR_SIMM9), QL2_A64C_CA_CAPADDR, 0),
+  A64C_INSN ("stur", 0xe2800000, 0xffa00c00, ldst_altbase, OP_STUR_AX, OP2 (Rsz2, CAPADDR_SIMM9), QL2_A64C_R_CAPADDR, 0),
   A64C_INSN ("stur", 0xe2200000, 0xff200c00, ldst_altbase, 0, OP2 (Fsz, CAPADDR_SIMM9), QL_S_2SAME, 0),
   A64C_INSN ("stur", 0xe2200800, 0xffe00c00, ldst_altbase, 0, OP2 (St, CAPADDR_SIMM9), QL_I2SAMEQ, 0),
 
-  A64C_INSN ("ldrb", 0x82600400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
+  A64C_INSN ("ldrb", 0x82600400, 0xffe00c00, ldst_altbase, OP_LDRB_POS_A, OP2 (Wt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
   A64C_INSN ("ldrb", 0x82c00000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
-  A64C_INSN ("strb", 0x82400400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
+  A64C_INSN ("strb", 0x82400400, 0xffe00c00, ldst_altbase, OP_STRB_POS_A, OP2 (Wt, CAPADDR_UIMM9), QL2_B_ADDR, F_NOSHIFT),
   A64C_INSN ("strb", 0x82800000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
 
   A64C_INSN ("ldrsb", 0x82c00400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_B_ADDR, 0),
@@ -4130,8 +4130,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
   A64C_INSN ("ldrh", 0x82c00c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_H_ADDR, 0),
   A64C_INSN ("strh", 0x82800c00, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_REGOFF), QL2_H_ADDR, 0),
 
-  A64C_INSN ("ldurb", 0xe2000400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
-  A64C_INSN ("sturb", 0xe2000000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
+  A64C_INSN ("ldurb", 0xe2000400, 0xffe00c00, ldst_altbase, OP_LDURB_A, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
+  A64C_INSN ("sturb", 0xe2000000, 0xffe00c00, ldst_altbase, OP_STURB_A, OP2 (Wt, CAPADDR_SIMM9), QL2_B_ADDR, 0),
   A64C_INSN ("ldurh", 0xe2400400, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_H_ADDR, 0),
   A64C_INSN ("sturh", 0xe2400000, 0xffe00c00, ldst_altbase, 0, OP2 (Wt, CAPADDR_SIMM9), QL2_H_ADDR, 0),