RISC-V: Add riscv{32,64}be with big endian as default

gcc/
	* common/config/riscv/riscv-common.c
	(TARGET_DEFAULT_TARGET_FLAGS): Set default endianness.
	* config.gcc (riscv32be-*, riscv64be-*): Set
	TARGET_BIG_ENDIAN_DEFAULT to 1.
	* config/riscv/elf.h (LINK_SPEC): Change -melf* value
	depending on default endianness.
	* config/riscv/freebsd.h (LINK_SPEC): Likewise.
	* config/riscv/linux.h (LINK_SPEC): Likewise.
	* config/riscv/riscv.c (TARGET_DEFAULT_TARGET_FLAGS): Set
	default endianness.
	* config/riscv/riscv.h (DEFAULT_ENDIAN_SPEC): New macro.

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 6bbe25dba89074e691ae9e17a755314e5b462c6c..34b74e52a2d148f82598153c79928935e9f3c14a 100644 (file)
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -32,6 +32,11 @@ along with GCC; see the file COPYING3.  If not see
 #include "config/riscv/riscv-protos.h"
 #include "config/riscv/riscv-subset.h"
 
+#ifdef  TARGET_BIG_ENDIAN_DEFAULT
+#undef  TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
+#endif
+
 /* Type for implied ISA info.  */
 struct riscv_implied_info_t
 {

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 9cecc140c83f1ccd9561b80ac2fbddd52ad2b8d1..ed6203b2efc8e1ed55e8eb761734f3ff83207658 100644 (file)
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2468,6 +2468,11 @@ riscv*-*-linux*)
        tmake_file="${tmake_file} riscv/t-riscv riscv/t-linux"
        gnu_ld=yes
        gas=yes
+       case $target in
+       riscv32be-*|riscv64be-*)
+               tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+               ;;
+       esac
        # Force .init_array support.  The configure script cannot always
        # automatically detect that GAS supports it, yet we require it.
        gcc_cv_initfini_array=yes
@@ -2491,6 +2496,11 @@ riscv*-*-elf* | riscv*-*-rtems*)
        tmake_file="${tmake_file} riscv/t-riscv"
        gnu_ld=yes
        gas=yes
+       case $target in
+       riscv32be-*|riscv64be-*)
+               tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+               ;;
+       esac
        # Force .init_array support.  The configure script cannot always
        # automatically detect that GAS supports it, yet we require it.
        gcc_cv_initfini_array=yes
@@ -2500,6 +2510,11 @@ riscv*-*-freebsd*)
        tmake_file="${tmake_file} riscv/t-riscv"
        gnu_ld=yes
        gas=yes
+       case $target in
+       riscv32be-*|riscv64be-*)
+               tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+               ;;
+       esac
        # Force .init_array support.  The configure script cannot always
        # automatically detect that GAS supports it, yet we require it.
        gcc_cv_initfini_array=yes

diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h
index 973efdaed7b6431b2801244f987bfd9dc37f678b..7e65e499031179252b08670e59c36cfa3874b131 100644 (file)
--- a/gcc/config/riscv/elf.h
+++ b/gcc/config/riscv/elf.h
@@ -18,7 +18,7 @@ along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
 #define LINK_SPEC "\
--melf" XLEN_SPEC "lriscv \
+-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
 %{mno-relax:--no-relax} \
 %{mbig-endian:-EB} \
 %{mlittle-endian:-EL} \

diff --git a/gcc/config/riscv/freebsd.h b/gcc/config/riscv/freebsd.h
index f3aca9f76734fe92c290a80ccda04d0f37c0a8d0..6018e7bb764d2dd204a27d40180d93645da8a03d 100644 (file)
--- a/gcc/config/riscv/freebsd.h
+++ b/gcc/config/riscv/freebsd.h
@@ -40,7 +40,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef LINK_SPEC
 #define LINK_SPEC "                                            \
-  -melf" XLEN_SPEC "lriscv                                     \
+  -melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv                  \
   %{p:%nconsider using `-pg' instead of `-p' with gprof (1)}   \
   %{v:-V}                                                      \
   %{assert*} %{R*} %{rpath*} %{defsym*}                                \

diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
index e74f5d3f914255136641af02b76709b2b5fa1d16..fce5b896e6e5cd39dbfebd87ba7de366ba855cef 100644 (file)
--- a/gcc/config/riscv/linux.h
+++ b/gcc/config/riscv/linux.h
@@ -58,7 +58,7 @@ along with GCC; see the file COPYING3.  If not see
   "%{mabi=ilp32:_ilp32}"
 
 #define LINK_SPEC "\
--melf" XLEN_SPEC "lriscv" LD_EMUL_SUFFIX " \
+-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \
 %{mno-relax:--no-relax} \
 %{mbig-endian:-EB} \
 %{mlittle-endian:-EL} \

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index de8308c3af08ebdd4877fb2ece2b6146266e7486..99b843867b5bc6dadaa772a89b29556765386a0d 100644 (file)
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5526,6 +5526,11 @@ riscv_asan_shadow_offset (void)
 #undef TARGET_ASAN_SHADOW_OFFSET
 #define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
 
+#ifdef TARGET_BIG_ENDIAN_DEFAULT
+#undef  TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
+#endif
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 0b667d2e8b9172e813abff703197206d17193c0a..3cc3e864a3ed3772426296e8209b7baae4166efe 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -30,6 +30,12 @@ along with GCC; see the file COPYING3.  If not see
 /* Target CPU versions for D.  */
 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions
 
+#ifdef TARGET_BIG_ENDIAN_DEFAULT
+#define DEFAULT_ENDIAN_SPEC    "b"
+#else
+#define DEFAULT_ENDIAN_SPEC    "l"
+#endif
+
 /* Default target_flags if no switches are specified  */
 
 #ifndef TARGET_DEFAULT