spi: cadence_qspi: Fix odd byte write issue in STIG mode

Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG
mode for all ops with small payload") the utilization of STIG mode
has been implemented for read and write operations involving less
than 8 bytes of data.

However, following this commit, encountering timeout issues occurs when
writing odd bytes of data in DDR mode, as indicated below:
"jedec_spi_nor flash@0: flash operation timed out
SF: 3 bytes @ 0x0 Written: ERROR -110"

To resolve this issue, the number of bytes to write has been updated
specifically for DDR mode.

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250704040444.671604-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index b579699d2ebf2031531f4ddec6bbd37e1bb1c07a..76569a8019bdfe50832198e89ff9faa8b677fc67 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -554,6 +554,9 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
        void *reg_base = priv->regbase;
        u8 opcode;
 
+       if (priv->dtr)
+               txlen += txlen & 1;
+
        if (priv->dtr)
                opcode = op->cmd.opcode >> 8;
        else