KVM: arm64: nv: Add additional trap setup for CPTR_EL2

We need to teach KVM a couple of new tricks. CPTR_EL2 and its
VHE accessor CPACR_EL1 need to be handled specially:

- CPACR_EL1 is trapped on VHE so that we can track the TCPAC
  and TTA bits

- CPTR_EL2.{TCPAC,E0POE} are propagated from L1 to L2

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240620164653.1130714-15-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
index fa6c27b6ad9959942ee791cacf21a422fae9dc3d..f680182971145a26989efbef8a8f6777d2a984b5 100644 (file)
--- a/arch/arm64/kvm/hyp/vhe/switch.c
+++ b/arch/arm64/kvm/hyp/vhe/switch.c
@@ -87,11 +87,23 @@ static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
                __activate_traps_fpsimd32(vcpu);
        }
 
+       if (!vcpu_has_nv(vcpu))
+               goto write;
+
+       /*
+        * The architecture is a bit crap (what a surprise): an EL2 guest
+        * writing to CPTR_EL2 via CPACR_EL1 can't set any of TCPAC or TTA,
+        * as they are RES0 in the guest's view. To work around it, trap the
+        * sucker using the very same bit it can't set...
+        */
+       if (vcpu_el2_e2h_is_set(vcpu) && is_hyp_ctxt(vcpu))
+               val |= CPTR_EL2_TCPAC;
+
        /*
         * Layer the guest hypervisor's trap configuration on top of our own if
         * we're in a nested context.
         */
-       if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
+       if (is_hyp_ctxt(vcpu))
                goto write;
 
        cptr = vcpu_sanitised_cptr_el2(vcpu);
@@ -115,6 +127,11 @@ static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
        if (!(SYS_FIELD_GET(CPACR_ELx, ZEN, cptr) & BIT(0)))
                val &= ~CPACR_ELx_ZEN;
 
+       if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
+               val |= cptr & CPACR_ELx_E0POE;
+
+       val |= cptr & CPTR_EL2_TCPAC;
+
 write:
        write_sysreg(val, cpacr_el1);
 }