arm64: dts: rockchip: add QNAP TS233 devicetree

The TS233 is a 2 bay NAS similar to the TS433. Architecture-wise it really
seems to be the same minus the additional PCIe connected components the
TS433 has.

So it just uses two of the SoCs SATA ports and the SoC's gigabit ethernet.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20251112214206.423244-6-heiko@sntech.de

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 73bd126efc4c32d690eed00445dced2723c5edd7..f7729e08be72b90ba5b6b00f2ecc773bb18dcf2a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -144,6 +144,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts
new file mode 100644 (file)
index 0000000..f16d1c6
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
+ */
+
+/dts-v1/;
+
+#include "rk3568-qnap-tsx33.dtsi"
+
+/ {
+       model = "Qnap TS-233-2G NAS System 2-Bay";
+       compatible = "qnap,ts233", "rockchip,rk3568";
+
+       aliases {
+               ethernet0 = &gmac0;
+       };
+};
+
+/* connected to sata2 */
+&combphy2 {
+       status = "okay";
+};
+
+&gmac0 {
+       assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+       assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+       assigned-clock-rates = <0>, <125000000>;
+       clock_in_out = "output";
+       phy-handle = <&rgmii_phy0>;
+       phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk
+                    &gmac0_rgmii_bus>;
+       status = "okay";
+};
+
+&i2c1 {
+       /* eeprom for vital-product-data on the backplane */
+       eeprom@56 {
+               compatible = "giantec,gt24c04a", "atmel,24c04";
+               reg = <0x56>;
+               label = "VPD_BP";
+               num-addresses = <2>;
+               pagesize = <16>;
+               read-only;
+       };
+};
+
+&leds {
+       led-1 {
+               color = <LED_COLOR_ID_GREEN>;
+               function = LED_FUNCTION_DISK;
+               gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+               label = "hdd2:green:disk";
+               linux,default-trigger = "disk-activity";
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdd2_led_pin>;
+       };
+};
+
+&mcu {
+       compatible = "qnap,ts233-mcu";
+};
+
+&mdio0 {
+       rgmii_phy0: ethernet-phy@3 {
+               /* Motorcomm YT8521 phy */
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x3>;
+               pinctrl-0 = <&eth_phy0_reset_pin>;
+               pinctrl-names = "default";
+               reset-assert-us = <10000>;
+               reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&pinctrl {
+       gmac0 {
+               eth_phy0_reset_pin: eth-phy0-reset-pin {
+                       rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+
+       leds {
+               hdd2_led_pin: hdd2-led-pin {
+                       rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};
+
+&sata2 {
+       status = "okay";
+};
+
+&usb2phy1 {
+       status = "okay";
+};
+
+/* connected to usb_host1_ehci/ohci */
+&usb2phy1_host {
+       phy-supply = <&vcc5v0_host>;
+       status = "okay";
+};
+
+/* connected to usb_host0_ehci/ohci */
+&usb2phy1_otg {
+       phy-supply = <&vcc5v0_host>;
+       status = "okay";
+};
+
+/* right port backside */
+&usb_host0_ehci {
+       status = "okay";
+};
+
+&usb_host0_ohci {
+       status = "okay";
+};
+
+/* left port backside */
+&usb_host1_ehci {
+       status = "okay";
+};
+
+&usb_host1_ohci {
+       status = "okay";
+};