{
struct hl_device *hdev = dev_get_drvdata(dev);
- return sprintf(buf, "0x%08x\n",
- le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_version));
+ return sprintf(buf, "0x%08x%08x\n",
+ le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_timestamp),
+ le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_version));
}
static ssize_t cpucp_kernel_ver_show(struct device *dev,
* (0 = fully functional, 1 = lower-half is not functional,
* 2 = upper-half is not functional)
* @sec_info: security information
+ * @cpld_timestamp: CPLD programmed F/W timestamp.
* @pll_map: Bit map of supported PLLs for current ASIC version.
* @mme_binning_mask: MME binning mask,
* bits [0:6] <==> dcore0 mme fma
__u8 substrate_version;
__u8 eq_health_check_supported;
struct cpucp_security_info sec_info;
- __le32 reserved2;
+ __le32 cpld_timestamp;
__u8 pll_map[PLL_MAP_LEN];
__le64 mme_binning_mask;
__u8 fw_os_version[VERSION_MAX_LEN];