--- /dev/null
+From aa8e4f22ab7773352ba3895597189b8097f2c307 Mon Sep 17 00:00:00 2001
+From: "David E. Box" <david.e.box@linux.intel.com>
+Date: Wed, 27 Aug 2014 14:40:39 -0700
+Subject: x86/iosf: Add Kconfig prompt for IOSF_MBI selection
+
+From: "David E. Box" <david.e.box@linux.intel.com>
+
+commit aa8e4f22ab7773352ba3895597189b8097f2c307 upstream.
+
+Fixes an error in having the iosf build as 'default m'. On X86 SoC's the iosf
+sideband is the only way to access information for some registers, as opposed to
+through MSR's on other Intel architectures. While selecting IOSF_MBI is
+preferred, it does mean carrying extra code on non-SoC architectures. This
+exports the selection to the user, allowing those driver writers to compile out
+iosf code if it's not being built.
+
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Link: http://lkml.kernel.org/r/1409175640-32426-2-git-send-email-david.e.box@linux.intel.com
+Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
+Cc: William Dauchy <william@gandi.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/Kconfig | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/Kconfig
++++ b/arch/x86/Kconfig
+@@ -2440,9 +2440,19 @@ config X86_DMA_REMAP
+ depends on STA2X11
+
+ config IOSF_MBI
+- tristate
+- default m
++ tristate "Intel System On Chip IOSF Sideband support"
+ depends on PCI
++ ---help---
++ Enables sideband access to mailbox registers on SoC's. The sideband is
++ available on the following platforms. This list is not meant to be
++ exclusive.
++ - BayTrail
++ - Cherryview
++ - Braswell
++ - Quark
++
++ You should say Y if you are running a kernel on one of these
++ platforms.
+
+ source "net/Kconfig"
+