+2012-10-11 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/alpha/alpha.md (DWI): New mode attribute.
+ (*sadd<modesuffix>): Macroize insn from *saddl and *saddq using
+ I48MODE mode iterator.
+ (addv<mode>3): Macroize insn from addvsi3 and addvdi3 using
+ I48MODE mode iterator.
+ (neg<mode>2): Macroize insn from negsi2 and negdi2 using
+ I48MODE mode iterator.
+ (negv<mode>2): Macroize insn from negvsi2 and negvdi2 using
+ I48MODE mode iterator.
+ (sub<mode>3): Macroize insn from subsi3 and subdi3 using
+ I48MODE mode iterator.
+ (*ssub<modesuffix>): Macroize insn from *ssubl and *ssubq using
+ I48MODE mode iterator.
+ (subv<mode>3): Macroize insn from subvsi3 and subvdi3 using
+ I48MODE mode iterator.
+ (mul<mode>3): Macroize insn from mulsi3 and muldi3 using
+ I48MODE mode iterator.
+ (mulv<mode>3): Macroize insn from mulvsi3 and mulvdi3 using
+ I48MODE mode iterator.
+ (*iornot<mode>3): Macroize insn from *iornotsi3 and *iornotdi3 using
+ I48MODE mode iterator.
+ (*xornot<mode>3): Macroize insn from *xornotsi3 and *xornotdi3 using
+ I48MODE mode iterator.
+
2012-10-11 Jason Merrill <jason@redhat.com>
* configure.ac (gcc_cv_as_aix_ref): Fix typo.
2012-10-10 Segher Boessenkool <segher@kernel.crashing.org>
- * config/rs6000/rs6000.h (PRINT_OPERAND_PUNCT_VALID_P):
- Delete '.'.
+ * config/rs6000/rs6000.h (PRINT_OPERAND_PUNCT_VALID_P): Delete '.'.
2012-10-10 Jakub Jelinek <jakub@redhat.com>
(lto_write_tree): Adjust.
(output_eh_region): Likewise.
(output_struct_function_base): Likewise.
- * lto-streamer.c (lto_streamer_hooks_init): Initialize location
- hooks.
+ * lto-streamer.c (lto_streamer_hooks_init): Initialize location hooks.
* lto-streamer.h (lto_input_location): Adjust prototype.
(lto_output_location): Likewise.
* streamer-hooks.h (struct streamer_hooks): Adjust prototype
(rs6000_print_options_internal): New function for expanded
-mdebug=reg option printing to print both the ISA options, and the
builtins that are enabled.
- (rs6000_print_isa_options): New function to print the ISA
- options.
+ (rs6000_print_isa_options): New function to print the ISA options.
(rs6000_print_builtin_options): New function to print the builtin
functions enabled.
2012-10-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config.gcc: Enable zEC12 for with-arch and with-tune
- configure switches.
+ configure switches.
* common/config/s390/s390-common.c (processor_flags_table): Add
zEC12 entry.
* config/s390/2827.md: New file.
Set parameter defaults for zEC12.
(legitimate_reload_fp_constant_p): Adjust comment.
(preferred_la_operand_p): Adjust comment.
- (s390_expand_insv): Generate insv pattern without CC clobber for
- zEC12.
+ (s390_expand_insv): Generate insv pattern without CC clobber for zEC12.
(s390_adjust_priority): Add zEC12 check.
(s390_issue_rate): Return 2 for zEC12.
(s390_reorg): Enable code optimizations for zEC12.
(*movsf_insn): Likewise.
(*movdf_insn_sp64): Likewise.
(*mov<VM32:mode>_insn): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
- (*mov<VM64:mode>_insn_sp64): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
- (*mov<VM64:mode>_insn_sp32): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
+ (*mov<VM64:mode>_insn_sp64): Likewise, use 'fsrc2s'
+ instead of 'fsrc1s'.
+ (*mov<VM64:mode>_insn_sp32): Likewise, use 'fsrc2s'
+ instead of 'fsrc1s'.
(VIS logical instructions): Mark as visl.
(pdist_vis): Use 'pdist'.
(pditsn<mode>_vis): Use 'pdistn'.
* Makefile.in (fold-const.o): Add depencence on hash-table.h.
(dse.o): Likewise.
(cfg.o): Likewise.
- * fold-const.c (fold_checksum_tree): Change to new type-safe hash table.
+ * fold-const.c (fold_checksum_tree): Change to new
+ type-safe hash table.
* (print_fold_checksum): Likewise.
* cfg.c (var bb_original): Likewise.
* (var bb_copy): Likewise.
* (var loop_copy): Likewise.
* hash-table.h (template hash_table): Constify parameters for find...
and remove_elt... member functions.
- (hash_table::empty) Correct size expression.
- (hash_table::clear_slot) Correct deleted entry assignment.
+ (hash_table::empty) Correct size expression.
+ (hash_table::clear_slot) Correct deleted entry assignment.
* dse.c (var rtx_group_table): Change to new type-safe hash table.
2012-10-09 Steven Bosscher <steven@gcc.gnu.org>
;; Other mode iterators
(define_mode_iterator I12MODE [QI HI])
(define_mode_iterator I48MODE [SI DI])
+(define_mode_attr DWI [(SI "DI") (DI "TI")])
(define_mode_attr modesuffix [(SI "l") (DI "q")])
;; Where necessary, the suffixes _le and _be are used to distinguish between
operands[7] = gen_lowpart (SImode, operands[5]);
})
-(define_insn "addvsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
- (match_operand:SI 2 "sext_add_operand" "rI,O")))
- (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
- (sign_extend:DI (match_dup 2)))
- (sign_extend:DI (plus:SI (match_dup 1)
- (match_dup 2))))
- (const_int 0))]
- ""
- "@
- addlv %r1,%2,%0
- sublv %r1,%n2,%0")
-
(define_expand "adddi3"
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "register_operand" "")
FAIL;
})
-(define_insn "*saddl"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
- (match_operand:SI 2 "const48_operand" "I,I"))
- (match_operand:SI 3 "sext_add_operand" "rI,O")))]
+(define_insn "*sadd<modesuffix>"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
+ (plus:I48MODE
+ (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
+ (match_operand:I48MODE 2 "const48_operand" "I,I"))
+ (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))]
""
"@
- s%2addl %1,%3,%0
- s%2subl %1,%n3,%0")
+ s%2add<modesuffix> %1,%3,%0
+ s%2sub<modesuffix> %1,%n3,%0")
(define_insn "*saddl_se"
[(set (match_operand:DI 0 "register_operand" "=r,r")
operands[8] = gen_lowpart (SImode, operands[6]);
})
-(define_insn "*saddq"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
- (match_operand:DI 2 "const48_operand" "I,I"))
- (match_operand:DI 3 "sext_add_operand" "rI,O")))]
- ""
- "@
- s%2addq %1,%3,%0
- s%2subq %1,%n3,%0")
-
-(define_insn "addvdi3"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
- (match_operand:DI 2 "sext_add_operand" "rI,O")))
- (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
- (sign_extend:TI (match_dup 2)))
- (sign_extend:TI (plus:DI (match_dup 1)
- (match_dup 2))))
+(define_insn "addv<mode>3"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
+ (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ")
+ (match_operand:I48MODE 2 "sext_add_operand" "rI,O")))
+ (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1))
+ (sign_extend:<DWI> (match_dup 2)))
+ (sign_extend:<DWI> (plus:I48MODE (match_dup 1)
+ (match_dup 2))))
(const_int 0))]
""
"@
- addqv %r1,%2,%0
- subqv %r1,%n2,%0")
+ add<modesuffix>v %r1,%2,%0
+ sub<modesuffix>v %r1,%n2,%0")
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
+(define_insn "neg<mode>2"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))]
""
- "subl $31,%1,%0")
+ "sub<modesuffix> $31,%1,%0")
(define_insn "*negsi_se"
[(set (match_operand:DI 0 "register_operand" "=r")
""
"subl $31,%1,%0")
-(define_insn "negvsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (neg:SI (match_operand:SI 1 "register_operand" "r")))
- (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
- (sign_extend:DI (neg:SI (match_dup 1))))
+(define_insn "negv<mode>2"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r")))
+ (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1)))
+ (sign_extend:<DWI> (neg:I48MODE (match_dup 1))))
(const_int 0))]
""
- "sublv $31,%1,%0")
+ "sub<modesuffix>v $31,%1,%0")
-(define_insn "negdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
+(define_insn "sub<mode>3"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
+ (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
""
- "subq $31,%1,%0")
-
-(define_insn "negvdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (neg:DI (match_operand:DI 1 "register_operand" "r")))
- (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
- (sign_extend:TI (neg:DI (match_dup 1))))
- (const_int 0))]
- ""
- "subqv $31,%1,%0")
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
- (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
- ""
- "subl %r1,%2,%0")
+ "sub<modesuffix> %r1,%2,%0")
(define_insn "*subsi_se"
[(set (match_operand:DI 0 "register_operand" "=r")
""
"subl %r1,%2,%0")
-(define_insn "subvsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
- (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
- (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
- (sign_extend:DI (match_dup 2)))
- (sign_extend:DI (minus:SI (match_dup 1)
- (match_dup 2))))
- (const_int 0))]
- ""
- "sublv %r1,%2,%0")
-
-(define_insn "subdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
- (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
- ""
- "subq %r1,%2,%0")
-
-(define_insn "*ssubl"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
- (match_operand:SI 2 "const48_operand" "I"))
- (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
+(define_insn "*ssub<modesuffix>"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (minus:I48MODE
+ (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
+ (match_operand:I48MODE 2 "const48_operand" "I"))
+ (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))]
""
- "s%2subl %1,%3,%0")
+ "s%2sub<modesuffix> %1,%3,%0")
(define_insn "*ssubl_se"
[(set (match_operand:DI 0 "register_operand" "=r")
""
"s%2subl %1,%3,%0")
-(define_insn "*ssubq"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
- (match_operand:DI 2 "const48_operand" "I"))
- (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
- ""
- "s%2subq %1,%3,%0")
-
-(define_insn "subvdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
- (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
- (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
- (sign_extend:TI (match_dup 2)))
- (sign_extend:TI (minus:DI (match_dup 1)
- (match_dup 2))))
+(define_insn "subv<mode>3"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
+ (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
+ (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1))
+ (sign_extend:<DWI> (match_dup 2)))
+ (sign_extend:<DWI> (minus:I48MODE (match_dup 1)
+ (match_dup 2))))
(const_int 0))]
""
- "subqv %r1,%2,%0")
+ "sub<modesuffix>v %r1,%2,%0")
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
- (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
+(define_insn "mul<mode>3"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
+ (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
""
- "mull %r1,%2,%0"
+ "mul<modesuffix> %r1,%2,%0"
[(set_attr "type" "imul")
- (set_attr "opsize" "si")])
+ (set_attr "opsize" "<mode>")])
(define_insn "*mulsi_se"
[(set (match_operand:DI 0 "register_operand" "=r")
[(set_attr "type" "imul")
(set_attr "opsize" "si")])
-(define_insn "mulvsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
- (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
- (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
- (sign_extend:DI (match_dup 2)))
- (sign_extend:DI (mult:SI (match_dup 1)
- (match_dup 2))))
+(define_insn "mulv<mode>3"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
+ (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
+ (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1))
+ (sign_extend:<DWI> (match_dup 2)))
+ (sign_extend:<DWI> (mult:I48MODE (match_dup 1)
+ (match_dup 2))))
(const_int 0))]
""
- "mullv %r1,%2,%0"
+ "mul<modesuffix>v %r1,%2,%0"
[(set_attr "type" "imul")
- (set_attr "opsize" "si")])
-
-(define_insn "muldi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
- (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
- ""
- "mulq %r1,%2,%0"
- [(set_attr "type" "imul")])
-
-(define_insn "mulvdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
- (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
- (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
- (sign_extend:TI (match_dup 2)))
- (sign_extend:TI (mult:DI (match_dup 1)
- (match_dup 2))))
- (const_int 0))]
- ""
- "mulqv %r1,%2,%0"
- [(set_attr "type" "imul")])
+ (set_attr "opsize" "<mode>")])
(define_expand "umuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "")
"ornot $31,%1,%0"
[(set_attr "type" "ilog")])
-(define_insn "*iornotsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
- (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
- ""
- "ornot %r2,%1,%0"
- [(set_attr "type" "ilog")])
-
-(define_insn "*iornotdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
- (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
+(define_insn "*iornot<mode>3"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (ior:I48MODE (not:I48MODE
+ (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI"))
+ (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))]
""
"ornot %r2,%1,%0"
[(set_attr "type" "ilog")])
eqv %r1,%N2,%0"
[(set_attr "type" "ilog")])
-(define_insn "*xornotsi3"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
- (match_operand:SI 2 "register_operand" "rI"))))]
- ""
- "eqv %r1,%2,%0"
- [(set_attr "type" "ilog")])
-
-(define_insn "*xornotdi3"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
- (match_operand:DI 2 "register_operand" "rI"))))]
+(define_insn "*xornot<mode>3"
+ [(set (match_operand:I48MODE 0 "register_operand" "=r")
+ (not:I48MODE (xor:I48MODE
+ (match_operand:I48MODE 1 "register_operand" "%rJ")
+ (match_operand:I48MODE 2 "register_operand" "rI"))))]
""
"eqv %r1,%2,%0"
[(set_attr "type" "ilog")])
projects / thirdparty / gcc.git / commitdiff
