RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]

Just notice the unalignment operand for strided load/store pattern when
bugfix the strided load/store memory alias, would like to make it align.

gcc/ChangeLog:

	* config/riscv/autovec.md: Align the operand for strided
	load/store pattern.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 2529dc77f22109a054ae673a2e08558de0b042f4..88c0f00e0ea47781e98cfb8091bb2680c64bdbf8 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2903,7 +2903,7 @@
 ;; == Strided Load/Store
 ;; =========================================================================
 (define_expand "mask_len_strided_load_<mode>"
-  [(match_operand:V_VLS     0 "register_operand")
+  [(match_operand:V_VLS 0 "register_operand")
    (match_operand       1 "pmode_reg_or_0_operand")
    (match_operand       2 "pmode_reg_or_0_operand")
    (match_operand:<VM>  3 "vector_mask_operand")
@@ -2919,7 +2919,7 @@
 (define_expand "mask_len_strided_store_<mode>"
   [(match_operand       0 "pmode_reg_or_0_operand")
    (match_operand       1 "pmode_reg_or_0_operand")
-   (match_operand:V_VLS     2 "register_operand")
+   (match_operand:V_VLS 2 "register_operand")
    (match_operand:<VM>  3 "vector_mask_operand")
    (match_operand       4 "autovec_length_operand")
    (match_operand       5 "const_0_operand")]