arm64: dts: renesas: r9a09g057: Add RTC node

Add RTC node to Renesas RZ/V2H ("R9A09G057") SoC DTSI.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251107210706.45044-4-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 92fc0cac6a65966259ff4e8f1baf83f134cf2d11..4df32d7e999818c94f8392130b70ee0e36293e89 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -621,6 +621,21 @@
                        status = "disabled";
                };
 
+               rtc: rtc@11c00800 {
+                       compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
+                       reg = <0 0x11c00800 0 0x400>;
+                       interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 525 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 526 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "alarm", "period", "carry";
+                       clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>;
+                       clock-names = "bus", "counter";
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x79>, <&cpg 0x7a>;
+                       reset-names = "rtc", "rtest";
+                       status = "disabled";
+               };
+
                scif: serial@11c01400 {
                        compatible = "renesas,scif-r9a09g057";
                        reg = <0 0x11c01400 0 0x400>;