--- /dev/null
+From 20ea2397d389b510ccc3c5166a66c5d7601711b5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 3 Nov 2022 17:31:00 -0700
+Subject: cxl/region: Recycle region ids
+
+From: Dan Williams <dan.j.williams@intel.com>
+
+[ Upstream commit 8f401ec1c8975eabfe4c089de91cbe058deabf71 ]
+
+At region creation time the next region-id is atomically cached so that
+there is predictability of region device names. If that region is
+destroyed and then a new one is created the region id increments. That
+ends up looking like a memory leak, or is otherwise surprising that
+identifiers roll forward even after destroying all previously created
+regions.
+
+Try to reuse rather than free old region ids at region release time.
+
+While this fixes a cosmetic issue, the needlessly advancing memory
+region-id gives the appearance of a memory leak, hence the "Fixes" tag,
+but no "Cc: stable" tag.
+
+Cc: Ben Widawsky <bwidawsk@kernel.org>
+Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Fixes: 779dd20cfb56 ("cxl/region: Add region creation support")
+Reviewed-by: Dave Jiang <dave.jiang@intel.com>
+Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>
+Link: https://lore.kernel.org/r/166752186062.947915.13200195701224993317.stgit@dwillia2-xfh.jf.intel.com
+Signed-off-by: Dan Williams <dan.j.williams@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/cxl/core/region.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
+index 6b7fb955a05a..78344e4d4215 100644
+--- a/drivers/cxl/core/region.c
++++ b/drivers/cxl/core/region.c
+@@ -1533,9 +1533,24 @@ static const struct attribute_group *region_groups[] = {
+
+ static void cxl_region_release(struct device *dev)
+ {
++ struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent);
+ struct cxl_region *cxlr = to_cxl_region(dev);
++ int id = atomic_read(&cxlrd->region_id);
++
++ /*
++ * Try to reuse the recently idled id rather than the cached
++ * next id to prevent the region id space from increasing
++ * unnecessarily.
++ */
++ if (cxlr->id < id)
++ if (atomic_try_cmpxchg(&cxlrd->region_id, &id, cxlr->id)) {
++ memregion_free(id);
++ goto out;
++ }
+
+ memregion_free(cxlr->id);
++out:
++ put_device(dev->parent);
+ kfree(cxlr);
+ }
+
+@@ -1597,6 +1612,11 @@ static struct cxl_region *cxl_region_alloc(struct cxl_root_decoder *cxlrd, int i
+ device_initialize(dev);
+ lockdep_set_class(&dev->mutex, &cxl_region_key);
+ dev->parent = &cxlrd->cxlsd.cxld.dev;
++ /*
++ * Keep root decoder pinned through cxl_region_release to fixup
++ * region id allocations
++ */
++ get_device(dev->parent);
+ device_set_pm_not_required(dev);
+ dev->bus = &cxl_bus_type;
+ dev->type = &cxl_region_type;
+--
+2.35.1
+
--- /dev/null
+From ed6f87a1e743a08eec31afab43dcbc8c74a83aed Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 28 Sep 2022 15:44:38 -0400
+Subject: drm/amd/display: Acquire FCLK DPM levels on DCN32
+
+From: Dillon Varone <Dillon.Varone@amd.com>
+
+[ Upstream commit d6170e418d1d3ae7e98cb6d96d1444e880131bbf ]
+
+[Why & How]
+Acquire FCLK DPM levels to properly construct DML clock limits. Further
+add new logic to keep number of indices for each clock in clk_mgr.
+
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: e59843c4cdd6 ("drm/amd/display: Limit dcn32 to 1950Mhz display clock")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 41 ++++++++++++-------
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 15 ++++++-
+ 2 files changed, 41 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+index f0f3f66629cc..f4c7bbd9961a 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+@@ -156,7 +156,7 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
+ {
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ unsigned int num_levels;
+- unsigned int num_dcfclk_levels, num_dtbclk_levels, num_dispclk_levels;
++ struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
+
+ memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
+ clk_mgr_base->clks.p_state_change_support = true;
+@@ -180,27 +180,28 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
+ /* DCFCLK */
+ dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
+ &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
+- &num_levels);
+- num_dcfclk_levels = num_levels;
++ &num_entries_per_clk->num_dcfclk_levels);
+
+ /* SOCCLK */
+ dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
+ &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
+- &num_levels);
++ &num_entries_per_clk->num_socclk_levels);
++
+ /* DTBCLK */
+ if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch)
+ dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
+ &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
+- &num_levels);
+- num_dtbclk_levels = num_levels;
++ &num_entries_per_clk->num_dtbclk_levels);
+
+ /* DISPCLK */
+ dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
+ &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
+- &num_levels);
+- num_dispclk_levels = num_levels;
++ &num_entries_per_clk->num_dispclk_levels);
++ num_levels = num_entries_per_clk->num_dispclk_levels;
+
+- if (num_dcfclk_levels && num_dtbclk_levels && num_dispclk_levels)
++ if (num_entries_per_clk->num_dcfclk_levels &&
++ num_entries_per_clk->num_dtbclk_levels &&
++ num_entries_per_clk->num_dispclk_levels)
+ clk_mgr->dpm_present = true;
+
+ if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
+@@ -370,7 +371,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
+ /* to disable P-State switching, set UCLK min = max */
+ if (!clk_mgr_base->clks.p_state_change_support)
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+- clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
++ clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
+ }
+
+ if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
+@@ -632,7 +633,7 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current
+ khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+ else
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+- clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
++ clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
+ } else {
+ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+ clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+@@ -648,22 +649,34 @@ static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
+ return;
+
+ dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
+- clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
++ clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
+ }
+
+ /* Get current memclk states, update bounding box */
+ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
+ {
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++ struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
+ unsigned int num_levels;
+
+ if (!clk_mgr->smu_present)
+ return;
+
+- /* Refresh memclk states */
++ /* Refresh memclk and fclk states */
+ dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
+ &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
+- &num_levels);
++ &num_entries_per_clk->num_memclk_levels);
++
++ dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
++ &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
++ &num_entries_per_clk->num_fclk_levels);
++
++ if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
++ num_levels = num_entries_per_clk->num_memclk_levels;
++ } else {
++ num_levels = num_entries_per_clk->num_fclk_levels;
++ }
++
+ clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
+
+ if (clk_mgr->dpm_present && !num_levels)
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index d9f1b0a4fbd4..591ab1389e3b 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -95,10 +95,23 @@ struct clk_limit_table_entry {
+ unsigned int wck_ratio;
+ };
+
++struct clk_limit_num_entries {
++ unsigned int num_dcfclk_levels;
++ unsigned int num_fclk_levels;
++ unsigned int num_memclk_levels;
++ unsigned int num_socclk_levels;
++ unsigned int num_dtbclk_levels;
++ unsigned int num_dispclk_levels;
++ unsigned int num_dppclk_levels;
++ unsigned int num_phyclk_levels;
++ unsigned int num_phyclk_d18_levels;
++};
++
+ /* This table is contiguous */
+ struct clk_limit_table {
+ struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
+- unsigned int num_entries;
++ struct clk_limit_num_entries num_entries_per_clk;
++ unsigned int num_entries; /* highest populated dpm level for back compatibility */
+ };
+
+ struct wm_range_table_entry {
+--
+2.35.1
+
--- /dev/null
+From bb7dfcf9824a48cbde67bbf4f5180f8901a7373d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 20 Oct 2022 11:46:44 -0400
+Subject: drm/amd/display: Limit dcn32 to 1950Mhz display clock
+
+From: Jun Lei <jun.lei@amd.com>
+
+[ Upstream commit e59843c4cdd68a369591630088171eeacce9859f ]
+
+[why]
+Hardware team recommends we limit dispclock to 1950Mhz for all DCN3.2.x
+
+[how]
+Limit to 1950 when initializing clocks.
+
+Tested-by: Mark Broadworth <mark.broadworth@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Jun Lei <jun.lei@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0.x
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+index f4c7bbd9961a..f3090ead9af5 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+@@ -157,6 +157,7 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ unsigned int num_levels;
+ struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
++ unsigned int i;
+
+ memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
+ clk_mgr_base->clks.p_state_change_support = true;
+@@ -205,18 +206,17 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
+ clk_mgr->dpm_present = true;
+
+ if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
+- unsigned int i;
+-
+ for (i = 0; i < num_levels; i++)
+ if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
+ < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
+ clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
+ = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
+ }
++ for (i = 0; i < num_levels; i++)
++ if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
++ clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
+
+ if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
+- unsigned int i;
+-
+ for (i = 0; i < num_levels; i++)
+ if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
+ < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
+--
+2.35.1
+
--- /dev/null
+From 4192cd9a4e3bf4b8c067d7820c5ed6112b780577 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 20 Oct 2022 11:46:48 -0400
+Subject: drm/amd/display: Set memclk levels to be at least 1 for dcn32
+
+From: Dillon Varone <Dillon.Varone@amd.com>
+
+[ Upstream commit 6cb5cec16c380be4cf9776a8c23b72e9fe742fd1 ]
+
+[Why]
+Cannot report 0 memclk levels even when SMU does not provide any.
+
+[How]
+When memclk levels reported by SMU is 0, set levels to 1.
+
+Tested-by: Mark Broadworth <mark.broadworth@amd.com>
+Reviewed-by: Martin Leung <Martin.Leung@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0.x
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+index f3090ead9af5..e7f1d5f8166f 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+@@ -667,6 +667,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
+ &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
+ &num_entries_per_clk->num_memclk_levels);
+
++ /* memclk must have at least one level */
++ num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
++
+ dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
+ &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
+ &num_entries_per_clk->num_fclk_levels);
+--
+2.35.1
+
--- /dev/null
+From 5aebf9b47bd21731d19e8f9c9dfcd336f9182c50 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Oct 2022 10:00:54 +0800
+Subject: drm/amdkfd: Fix NULL pointer dereference in svm_migrate_to_ram()
+
+From: Yang Li <yang.lee@linux.alibaba.com>
+
+[ Upstream commit 5b994354af3cab770bf13386469c5725713679af ]
+
+./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:985:58-62: ERROR: p is NULL but dereferenced.
+
+Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2549
+Reported-by: Abaci Robot <abaci@linux.alibaba.com>
+Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+index 6555d775a532..5b5a79ccb716 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+@@ -971,12 +971,10 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
+ out_unlock_svms:
+ mutex_unlock(&p->svms.lock);
+ out_unref_process:
++ pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr);
+ kfd_unref_process(p);
+ out_mmput:
+ mmput(mm);
+-
+- pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr);
+-
+ return r ? VM_FAULT_SIGBUS : 0;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From f9fe6f7a65db236a3392806bcba20110f97f15b7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Sep 2022 12:30:12 -0400
+Subject: drm/amdkfd: handle CPU fault on COW mapping
+
+From: Philip Yang <Philip.Yang@amd.com>
+
+[ Upstream commit e1f84eef313f4820cca068a238c645d0a38c6a9b ]
+
+If CPU page fault in a page with zone_device_data svm_bo from another
+process, that means it is COW mapping in the child process and the
+range is migrated to VRAM by parent process. Migrate the parent
+process range back to system memory to recover the CPU page fault.
+
+Signed-off-by: Philip Yang <Philip.Yang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: 5b994354af3c ("drm/amdkfd: Fix NULL pointer dereference in svm_migrate_to_ram()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 42 ++++++++++++++++--------
+ 1 file changed, 29 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+index b059a77b6081..6555d775a532 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+@@ -886,7 +886,7 @@ svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,
+ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
+ {
+ unsigned long addr = vmf->address;
+- struct vm_area_struct *vma;
++ struct svm_range_bo *svm_bo;
+ enum svm_work_list_ops op;
+ struct svm_range *parent;
+ struct svm_range *prange;
+@@ -894,29 +894,42 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
+ struct mm_struct *mm;
+ int r = 0;
+
+- vma = vmf->vma;
+- mm = vma->vm_mm;
++ svm_bo = vmf->page->zone_device_data;
++ if (!svm_bo) {
++ pr_debug("failed get device page at addr 0x%lx\n", addr);
++ return VM_FAULT_SIGBUS;
++ }
++ if (!mmget_not_zero(svm_bo->eviction_fence->mm)) {
++ pr_debug("addr 0x%lx of process mm is detroyed\n", addr);
++ return VM_FAULT_SIGBUS;
++ }
++
++ mm = svm_bo->eviction_fence->mm;
++ if (mm != vmf->vma->vm_mm)
++ pr_debug("addr 0x%lx is COW mapping in child process\n", addr);
+
+- p = kfd_lookup_process_by_mm(vma->vm_mm);
++ p = kfd_lookup_process_by_mm(mm);
+ if (!p) {
+ pr_debug("failed find process at fault address 0x%lx\n", addr);
+- return VM_FAULT_SIGBUS;
++ r = VM_FAULT_SIGBUS;
++ goto out_mmput;
+ }
+ if (READ_ONCE(p->svms.faulting_task) == current) {
+ pr_debug("skipping ram migration\n");
+- kfd_unref_process(p);
+- return 0;
++ r = 0;
++ goto out_unref_process;
+ }
+- addr >>= PAGE_SHIFT;
++
+ pr_debug("CPU page fault svms 0x%p address 0x%lx\n", &p->svms, addr);
++ addr >>= PAGE_SHIFT;
+
+ mutex_lock(&p->svms.lock);
+
+ prange = svm_range_from_addr(&p->svms, addr, &parent);
+ if (!prange) {
+- pr_debug("cannot find svm range at 0x%lx\n", addr);
++ pr_debug("failed get range svms 0x%p addr 0x%lx\n", &p->svms, addr);
+ r = -EFAULT;
+- goto out;
++ goto out_unlock_svms;
+ }
+
+ mutex_lock(&parent->migrate_mutex);
+@@ -940,8 +953,8 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
+
+ r = svm_migrate_vram_to_ram(prange, mm, KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU);
+ if (r)
+- pr_debug("failed %d migrate 0x%p [0x%lx 0x%lx] to ram\n", r,
+- prange, prange->start, prange->last);
++ pr_debug("failed %d migrate svms 0x%p range 0x%p [0x%lx 0x%lx]\n",
++ r, prange->svms, prange, prange->start, prange->last);
+
+ /* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */
+ if (p->xnack_enabled && parent == prange)
+@@ -955,9 +968,12 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
+ if (prange != parent)
+ mutex_unlock(&prange->migrate_mutex);
+ mutex_unlock(&parent->migrate_mutex);
+-out:
++out_unlock_svms:
+ mutex_unlock(&p->svms.lock);
++out_unref_process:
+ kfd_unref_process(p);
++out_mmput:
++ mmput(mm);
+
+ pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr);
+
+--
+2.35.1
+
--- /dev/null
+From 7fc210e520b99119e6305ec1e4fcd3c034b51cd0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 31 Aug 2022 00:24:36 +0300
+Subject: drm/i915: Allow more varied alternate fixed modes for panels
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+[ Upstream commit a5810f551d0a8c83b4817b53a446bd115e7182ce ]
+
+On some systems the panel reports alternate modes with
+different blanking periods. If the EDID reports them and VBT
+doesn't tell us otherwise then I can't really see why they
+should be rejected. So allow their use for the purposes of
+static DRRS.
+
+For seamless DRRS we still require a much more exact match
+of course. But that logic only kicks in when selecting the
+downclock mode (or in the future when determining whether
+we can do a seamless refresh rate change due to a user
+modeset).
+
+Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6374
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220830212436.2021-1-ville.syrjala@linux.intel.com
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+Stable-dep-of: 12caf46cf4fc ("drm/i915/sdvo: Grab mode_config.mutex during LVDS init to avoid WARNs")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/i915/display/intel_panel.c | 25 ++++++----------------
+ 1 file changed, 6 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
+index 237a40623dd7..cb44984bb9a2 100644
+--- a/drivers/gpu/drm/i915/display/intel_panel.c
++++ b/drivers/gpu/drm/i915/display/intel_panel.c
+@@ -81,15 +81,14 @@ static bool is_alt_drrs_mode(const struct drm_display_mode *mode,
+ mode->clock != preferred_mode->clock;
+ }
+
+-static bool is_alt_vrr_mode(const struct drm_display_mode *mode,
+- const struct drm_display_mode *preferred_mode)
++static bool is_alt_fixed_mode(const struct drm_display_mode *mode,
++ const struct drm_display_mode *preferred_mode)
+ {
+ return drm_mode_match(mode, preferred_mode,
+ DRM_MODE_MATCH_FLAGS |
+ DRM_MODE_MATCH_3D_FLAGS) &&
+ mode->hdisplay == preferred_mode->hdisplay &&
+- mode->vdisplay == preferred_mode->vdisplay &&
+- mode->clock != preferred_mode->clock;
++ mode->vdisplay == preferred_mode->vdisplay;
+ }
+
+ const struct drm_display_mode *
+@@ -172,19 +171,7 @@ int intel_panel_compute_config(struct intel_connector *connector,
+ return 0;
+ }
+
+-static bool is_alt_fixed_mode(const struct drm_display_mode *mode,
+- const struct drm_display_mode *preferred_mode,
+- bool has_vrr)
+-{
+- /* is_alt_drrs_mode() is a subset of is_alt_vrr_mode() */
+- if (has_vrr)
+- return is_alt_vrr_mode(mode, preferred_mode);
+- else
+- return is_alt_drrs_mode(mode, preferred_mode);
+-}
+-
+-static void intel_panel_add_edid_alt_fixed_modes(struct intel_connector *connector,
+- bool has_vrr)
++static void intel_panel_add_edid_alt_fixed_modes(struct intel_connector *connector)
+ {
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ const struct drm_display_mode *preferred_mode =
+@@ -192,7 +179,7 @@ static void intel_panel_add_edid_alt_fixed_modes(struct intel_connector *connect
+ struct drm_display_mode *mode, *next;
+
+ list_for_each_entry_safe(mode, next, &connector->base.probed_modes, head) {
+- if (!is_alt_fixed_mode(mode, preferred_mode, has_vrr))
++ if (!is_alt_fixed_mode(mode, preferred_mode))
+ continue;
+
+ drm_dbg_kms(&dev_priv->drm,
+@@ -255,7 +242,7 @@ void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
+ {
+ intel_panel_add_edid_preferred_mode(connector);
+ if (intel_panel_preferred_fixed_mode(connector) && (has_drrs || has_vrr))
+- intel_panel_add_edid_alt_fixed_modes(connector, has_vrr);
++ intel_panel_add_edid_alt_fixed_modes(connector);
+ intel_panel_destroy_probed_modes(connector);
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 8106fb963dc3e9b518ffb30a57735a6114288d76 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Oct 2022 13:11:29 +0300
+Subject: drm/i915/sdvo: Grab mode_config.mutex during LVDS init to avoid WARNs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+[ Upstream commit 12caf46cf4fc92b1c3884cb363ace2e12732fd2f ]
+
+drm_mode_probed_add() is unhappy about being called w/o
+mode_config.mutex. Grab it during LVDS fixed mode setup
+to silence the WARNs.
+
+Cc: stable@vger.kernel.org
+Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7301
+Fixes: aa2b88074a56 ("drm/i915/sdvo: Fix multi function encoder stuff")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20221026101134.20865-4-ville.syrjala@linux.intel.com
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+(cherry picked from commit a3cd4f447281c56377de2ee109327400eb00668d)
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/i915/display/intel_sdvo.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
+index 282820fe55b5..6b471fc297bd 100644
+--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
++++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
+@@ -2900,8 +2900,12 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
+ intel_panel_add_vbt_sdvo_fixed_mode(intel_connector);
+
+ if (!intel_panel_preferred_fixed_mode(intel_connector)) {
++ mutex_lock(&i915->drm.mode_config.mutex);
++
+ intel_ddc_get_modes(connector, &intel_sdvo->ddc);
+ intel_panel_add_edid_fixed_modes(intel_connector, false);
++
++ mutex_unlock(&i915->drm.mode_config.mutex);
+ }
+
+ intel_panel_init(intel_connector);
+--
+2.35.1
+
--- /dev/null
+From b2ab400df0bdefb1cd54e53022a94a251b24ff35 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Sep 2022 21:06:13 +0300
+Subject: drm/i915: Simplify intel_panel_add_edid_alt_fixed_modes()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+[ Upstream commit d372ec94a018c3a19dad71e2ee3478126394d9fc ]
+
+Since commit a5810f551d0a ("drm/i915: Allow more varied alternate
+fixed modes for panels") intel_panel_add_edid_alt_fixed_modes()
+no longer considers vrr vs. drrs separately. So no reason to
+pass them as separate parameters either.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220927180615.25476-2-ville.syrjala@linux.intel.com
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+(cherry picked from commit eb89e83c152b122a94e79527d63cb7c79823c37e)
+Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Stable-dep-of: 12caf46cf4fc ("drm/i915/sdvo: Grab mode_config.mutex during LVDS init to avoid WARNs")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
+ drivers/gpu/drm/i915/display/intel_lvds.c | 3 +--
+ drivers/gpu/drm/i915/display/intel_panel.c | 4 ++--
+ drivers/gpu/drm/i915/display/intel_panel.h | 2 +-
+ drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
+ 5 files changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
+index d4492b6d23d2..21ba510716b6 100644
+--- a/drivers/gpu/drm/i915/display/intel_dp.c
++++ b/drivers/gpu/drm/i915/display/intel_dp.c
+@@ -5233,7 +5233,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
+ encoder->devdata, IS_ERR(edid) ? NULL : edid);
+
+ intel_panel_add_edid_fixed_modes(intel_connector,
+- intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
++ intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE ||
+ intel_vrr_is_capable(intel_connector));
+
+ /* MSO requires information from the EDID */
+diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
+index 730480ac3300..c0bec3e0f0ae 100644
+--- a/drivers/gpu/drm/i915/display/intel_lvds.c
++++ b/drivers/gpu/drm/i915/display/intel_lvds.c
+@@ -972,8 +972,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
+
+ /* Try EDID first */
+ intel_panel_add_edid_fixed_modes(intel_connector,
+- intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
+- false);
++ intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE);
+
+ /* Failed to get EDID, what about VBT? */
+ if (!intel_panel_preferred_fixed_mode(intel_connector))
+diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
+index cb44984bb9a2..1e008922b95d 100644
+--- a/drivers/gpu/drm/i915/display/intel_panel.c
++++ b/drivers/gpu/drm/i915/display/intel_panel.c
+@@ -238,10 +238,10 @@ static void intel_panel_destroy_probed_modes(struct intel_connector *connector)
+ }
+
+ void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
+- bool has_drrs, bool has_vrr)
++ bool use_alt_fixed_modes)
+ {
+ intel_panel_add_edid_preferred_mode(connector);
+- if (intel_panel_preferred_fixed_mode(connector) && (has_drrs || has_vrr))
++ if (intel_panel_preferred_fixed_mode(connector) && use_alt_fixed_modes)
+ intel_panel_add_edid_alt_fixed_modes(connector);
+ intel_panel_destroy_probed_modes(connector);
+ }
+diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
+index b087c0c3cc6d..4a94bd0eae3b 100644
+--- a/drivers/gpu/drm/i915/display/intel_panel.h
++++ b/drivers/gpu/drm/i915/display/intel_panel.h
+@@ -41,7 +41,7 @@ int intel_panel_fitting(struct intel_crtc_state *crtc_state,
+ int intel_panel_compute_config(struct intel_connector *connector,
+ struct drm_display_mode *adjusted_mode);
+ void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
+- bool has_drrs, bool has_vrr);
++ bool use_alt_fixed_modes);
+ void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector);
+ void intel_panel_add_vbt_sdvo_fixed_mode(struct intel_connector *connector);
+ void intel_panel_add_encoder_fixed_mode(struct intel_connector *connector,
+diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
+index b5f65b093c10..282820fe55b5 100644
+--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
++++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
+@@ -2901,7 +2901,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
+
+ if (!intel_panel_preferred_fixed_mode(intel_connector)) {
+ intel_ddc_get_modes(connector, &intel_sdvo->ddc);
+- intel_panel_add_edid_fixed_modes(intel_connector, false, false);
++ intel_panel_add_edid_fixed_modes(intel_connector, false);
+ }
+
+ intel_panel_init(intel_connector);
+--
+2.35.1
+
--- /dev/null
+From a5f5d2c7e1afe2fae389115bccbf732ae63e2b3d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Oct 2022 11:06:10 +0800
+Subject: KVM: debugfs: Return retval of simple_attr_open() if it fails
+
+From: Hou Wenlong <houwenlong.hwl@antgroup.com>
+
+[ Upstream commit 180418e2eb33be5c8d0b703c843e0ebc045aef80 ]
+
+Although simple_attr_open() fails only with -ENOMEM with current code
+base, it would be nicer to return retval of simple_attr_open() directly
+in kvm_debugfs_open().
+
+No functional change intended.
+
+Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
+Message-Id: <69d64d93accd1f33691b8a383ae555baee80f943.1665975828.git.houwenlong.hwl@antgroup.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ virt/kvm/kvm_main.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
+index 4c5259828efd..b76c775f61f9 100644
+--- a/virt/kvm/kvm_main.c
++++ b/virt/kvm/kvm_main.c
+@@ -5404,6 +5404,7 @@ static int kvm_debugfs_open(struct inode *inode, struct file *file,
+ int (*get)(void *, u64 *), int (*set)(void *, u64),
+ const char *fmt)
+ {
++ int ret;
+ struct kvm_stat_data *stat_data = (struct kvm_stat_data *)
+ inode->i_private;
+
+@@ -5415,15 +5416,13 @@ static int kvm_debugfs_open(struct inode *inode, struct file *file,
+ if (!kvm_get_kvm_safe(stat_data->kvm))
+ return -ENOENT;
+
+- if (simple_attr_open(inode, file, get,
+- kvm_stats_debugfs_mode(stat_data->desc) & 0222
+- ? set : NULL,
+- fmt)) {
++ ret = simple_attr_open(inode, file, get,
++ kvm_stats_debugfs_mode(stat_data->desc) & 0222
++ ? set : NULL, fmt);
++ if (ret)
+ kvm_put_kvm(stat_data->kvm);
+- return -ENOMEM;
+- }
+
+- return 0;
++ return ret;
+ }
+
+ static int kvm_debugfs_release(struct inode *inode, struct file *file)
+--
+2.35.1
+
thunderbolt-add-dp-out-resource-when-dp-tunnel-is-discovered.patch
drm-i915-gvt-add-missing-vfio_unregister_group_dev-call.patch
m68k-rework-bi_virt_rng_seed-as-bi_rng_seed.patch
+kvm-debugfs-return-retval-of-simple_attr_open-if-it-.patch
+drm-i915-allow-more-varied-alternate-fixed-modes-for.patch
+drm-i915-simplify-intel_panel_add_edid_alt_fixed_mod.patch
+drm-i915-sdvo-grab-mode_config.mutex-during-lvds-ini.patch
+drm-amd-display-acquire-fclk-dpm-levels-on-dcn32.patch
+drm-amd-display-limit-dcn32-to-1950mhz-display-clock.patch
+drm-amd-display-set-memclk-levels-to-be-at-least-1-f.patch
+drm-amdkfd-handle-cpu-fault-on-cow-mapping.patch
+drm-amdkfd-fix-null-pointer-dereference-in-svm_migra.patch
+cxl-region-recycle-region-ids.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
